Uart/Sio Serial Output Data Register (Tdr0) - Fujitsu F2MC-8FX Hardware Manual

20.5.5

UART/SIO Serial Output Data Register (TDR0)

The UART/SIO serial output data register (TDR0) is used to output (transmit) serial data.
UART/SIO Serial Output Data Register (TDR0)
Figure 20.5-6 shows the bit configuration of the UART/SIO serial output data register.
Address
0059 TDR0
H
R/W : Readable/writable (Read value is the same as write value)
This register holds data to be transmitted. The register accepts a write when the transmission data register
empty (TDRE) bit contains "1". An attempt to write to the bit is ignored when the bit contains "0".
When this register is updated at writting complete the transmission data and TDRE=0 (without depending
on TXE of the UART/SIO serial mode control register is "1" or "0"), the transmission operation is
initialized by writing "0" to TXE, TDRE becomes "1", and the update of this register becomes possible.
Moreover, when "0" is written in TXE without the starting transmission (when the transmission data is
written in TDR, and it has not transmitted TXE to "1" yet), TCPL is not set in "1". The transmission data is
transferred to the shift register for the transmission, it is converted into the serial data, and it is transmitted
from the serial data output terminal.
When transmit data is written to the UART/SIO serial output data register (TDR0), the transmission data
register empty bit (TDRE) is set to "0". Upon completion of transfer of transmit data to the transmission
shift register, the transmission data register empty bit (TDRE) is set to "1", allowing the next piece of
transmit data to be written. At this time, an interrupt occurs if transmission data register empty interrupts
have been enabled. Write the next piece of transmit data when transmit data empty occurs or the transmit
data empty (TDRE) bit is set to "1".
When the character bit length (CBL1, 0) is set to shorter than 8 bits, the excess upper bits (beyond the set
bit length) are ignored.
Note:
The data in this register cannot be updated when TDRE in UART/SIO serial status data register is
"0".
When this register is updated at writting complete the transmission data and TDRE=0 (without
depending on TXE of the UART/SIO serial mode control register 2 is "1" or "0"), the transmission
operation is initialized by writing "0" to TXE, TDRE becomes "1", and the update of this register
becomes possible.
Moreover, when "0" is written in TXE without the starting transmission (when the transmission data is
written in TDR, and it has not transmitted TXE to "1" yet), TCPL is not set in "1". And, to change
data, please write it after making TDRE "1" once by writing TXE =0.
Figure 20.5-6 UART/SIO Serial Output Data Register (TDR0)
bit7 bit6 bit5
TD7 TD6 TD5
R/W R/W R/W
bit4 bit3 bit2
TD4 TD3 TD2 TD1
R/W R/W R/W R/W
CHAPTER 20 UART/SIO
bit1 bit0 Initial value
TD0 00000000
R/W
B
341