Fujitsu F2MC-8FX Hardware Manual page 168

CHAPTER 9 I/O PORT
Behavior during LCDC segment output
• Sets the DDR register bit corresponding to the LCDC segment output pin to "0".
• Prohibit output in pins jointly used by other peripheral functions.
• In the LCDC enable registers (LCDCE 1 to 6), select all common pins and segment pins you will use.
Operation of the input level selection register
• Writing "1" to the bit2 of ILSR3 changes Port E from the hysteresis input level to the automotive input
level. When the bit2 of ILSR3 is "0", it should be the hysteresis input level.
Table 9.11-4 shows the pin states of the port.
Table 9.11-4 Pin State of Port E
Normal operation
Operating Sleep
state Stop (SPL=0)
Watch (SPL=0)
I/O port/
Pin state
peripheral function I/O
SPL: Pin state specification bit in standby control register (STBC:SPL)
Hi-Z: High impedance
*: "Input enabled" means the state that the operation of the input gate close to the pin is disabled.
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Stop (SPL=1)
Watch (SPL=1)
Hi-Z
(the pull-up setting is enabled)
Input cutoff
(If external interrupts are enabled,
the external interrupt can be input.)
At reset
Hi-Z
Input enabled*