Nested Interrupts - Fujitsu F2MC-8FX Hardware Manual

8.1.3

Nested Interrupts

You can set different interrupt levels for two or more interrupt requests from peripheral
resources in the interrupt level setting registers (ILR0 to ILR5) to process the nested
interrupts.
Nested Interrupts
If an interrupt request of higher-priority interrupt level occurs while an interrupt service routine is being
executed, the CPU halts processing of the current interrupt and accepts the higher-priority interrupt request.
The interrupt level can be set to 0 to 3. If it is set to 3, the CPU will accept no interrupt request.
[Example: Nested interrupts]
To assign higher priority to external interrupts over timer interrupts as an example of processing nested-
interrupts, set the timer interrupt and external interrupt levels to 2 and 1, respectively. If an external
interrupt occurs while a timer interrupt is being processed with these settings in use, the interrupts are
processed as shown in Figure 8.1-3.
Initialize peripheral (1)
resources.
Timer interrupt occurs. (2)
Resume main program. (8)
• While a timer interrupt is being processed, the interrupt level bits in the condition code register (CCR:
IL1, IL0) hold the same value as that of the interrupt level setting registers (ILR0 to ILR5)
corresponding to the current timer interrupt (level 2 in this example). If an interrupt request with a
higher-priority interrupt level (level 1 in the example) occurs, the higher-priority interrupt is processed
preferentially.
• To temporarily disable nested interrupt processing while a timer interrupt is being processed, set the
interrupt enable flag in the condition code register to disable interrupts (CCR:I = 0) or set the interrupt
level bits (CCR: IL1, IL0) to "00
• Executing the interrupt return instruction (RETI) after interrupt processing is completed restores the
program counter (PC) and program status (PS) values saved in a stack and resumes the processing of the
interrupted program.
Restoring the program status (PS) also restores the condition code register (CCR) to its value existing
prior to the interrupt.
Figure 8.1-3 Example of Processing Nested Interrupts
Main Program Timer Interrupt Processing
Interrupt level 2
(CCR:IL1,IL0=10 )
B
Suspend
Resume
".
B
External Interrupt Processing
Interrupt level 1
(CCR:IL1,IL0=01 )
B
(3) External interrupt
(4)
occurs.
(5)
(6) Process timer interrupt.
(7) Return from timer interrupt.
CHAPTER 8 INTERRUPTS
Process external interrupt.
Return from external interrupt.
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