Chapter 26 Clock Supervisor - Fujitsu F2MC-8FX Hardware Manual

Table 26.3-1 Functions of Bits in Clock Supervisor Control Register (CSVCR)
Bit name
bit7 Reserved bit
MM:
bit6 Main clock halt
detection bit
SM:
bit5 Sub clock halt
detection bit
RCE:
bit4 CR clock oscillation
enable bit
MSVE:
bit3 Main clock monitoring
enable bit
SSVE:
bit2 Sub clock monitoring
enable bit
SRST:
bit1 Reset generation
enable bit
bit0 Reserved bit
Note:
When the power is turned on, the clock supervisor starts monitoring after the oscillation stabilization
wait time for the main clock elapses. The oscillation stabilization wait time of the main clock must
therefore be longer than the time required for the clock supervisor to start operating.
This bit is reserved.
Write "0" to this bit. The read value is always "0".
This bit is read-only, and this bit indicates that a main clock oscillation halt has been detected.
When set to "1": The bit indicates that a main clock oscillation halt has been detected.
When set to "0": The bit indicates that no main clock oscillation halt has been detected.
Writing "1" to this bit does not affect the operation.
This bit is read-only, and this bit indicates that a sub clock oscillation halt has been detected.
When set to "1": The bit indicates that a sub clock oscillation halt has been detected.
When set to "0": The bit indicates that no sub clock oscillation halt has been detected.
Writing "1" to this bit does not affect the operation.
This bit enables CR oscillation.
When set to "1": The bit enables oscillation.
When set to "0": The bit disables oscillation.
Before writing "0" to this bit, make sure that the clock monitor function has been disabled with the
MM and SM bits set to "0".
This bit enables the monitoring of main clock oscillation.
When set to "1": The bit enables main clock monitoring.
When set to "0": The bit disables main clock monitoring.
This bit is set to "1" only when a power-on reset occurs.
This bit enables the monitoring of sub clock oscillation.
When set to "1": The bit enables sub clock monitoring.
When set to "0": The bit disables sub clock monitoring.
This bit is set to "1" only when a power-on reset occurs.
This bit enables reset output upon transition to sub mode.
When set to "1": The bit causes a reset upon transition to sub clock mode with the sub clock halted
in main clock mode.
When set to "0": The bit prevents a reset upon transition to sub clock mode with the sub clock
halted in main clock mode.
This bit is reserved.
Write "0" to this bit. The read value is always "0".

CHAPTER 26 CLOCK SUPERVISOR

Function
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