Fujitsu F2MC-8FX Hardware Manual page 581

Figure C.2-3 shows a summary of the instruction.
DIVU A
This instruction divides the 16-bit value in T by the unsigned 16-bit value in A, and stores the 16-bit result
and the 16-bit remainder in A and T, respectively. When the value in A before execution of instruction is
"0", the Z flag becomes "1" to indicate zero-division is executed. The instruction does not change other
flags, and therefore care must be taken when a branch may occur depending on the result of a division.
Figure C.2-4 shows a summary of the instruction.
XCHW A, PC
This instruction swaps the contents of A and PC, resulting in a branch to the address contained in A before
execution of the instruction. After the instruction is executed, A becomes the address that follows the
address where the operation code of "XCHW A, PC" is stored. This instruction is effective especially when
it is used in the main routine to specify a table for use in a subroutine.
Figure C.2-5 shows a summary of the instruction.
When this instruction is executed, the content of A reaches the same value as the address where the
following instruction is stored, rather than the address where operation code of this instruction is stored.
Therefore, in Figure C.2-5, the value "1235
operation code of "XCHW A, PC" is stored. This is why "1235
Figure C.2-6 shows an assembler language example.
Figure C.2-3 MULU A
(Before executing)
A 5 6 7 8
H
T 1 2 3 4
H
Figure C.2-4 DIVU A
(Before executing)
A 1 2 3 4
H
T 5 6 7 8
H
Figure C.2-5 XCHW A, PC
(Before executing)
A 5 6 7 8
H
1 2 3 4
PC
H
" stored in A corresponds to the address where the following
H
APPENDIX C Instruction Overview
(After executing)
A 1 8 6 0
H
T 1 2 3 4
H
(After executing)
A 0 0 0 4
H
T 0 D A 8
H
(After executing)
A 1 2 3 5
H
5 6 7 8
PC
H
" is stored instead of "1234
H
".
H
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