Fujitsu F2MC-8FX Hardware Manual page 412

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CHAPTER 22 I C
Acknowledgment
An acknowledgment is sent by the receiver in the ninth clock cycle for data byte transfer by the sender
based on the following conditions.
An address acknowledgment is generated in the following cases.
• The received address matches the address set in IAAR0, and the address acknowledgment is output
automatically (IBCR00:AACKX = 0).
• A general call address (00H) is received and the general call address acknowledgment output is enabled
(IBCR10:GACKE = 1).
A data acknowledge bit used when data is received can be enabled or disabled by the IBCR10:DACKE bit.
In master mode, a data acknowledgment is generated if IBCR10:DACKE = 1. In slave mode, a data
acknowledgment is generated if an address acknowledgment has already been generated and
IBCR10:DACKE = 1. The received acknowledgment is saved in IBSR0:LRB in the ninth SCL0 cycle.
• If the data ACK depends on the content of received data (such as packet error checking used by the SM
bus), control the data ACK by setting the data ACK enable bit (IBCR10:DACKE) after writing "1" to
the IBCR00:INTS bit (for example, by a previous transfer completion interrupt) so that the latest
received data can be read.
• The latest data ACK (IBSR0:LRB) can be read after the ACK has been received (IBSR0:LRB must be
read during the transfer completion interrupt triggered by the ninth SCL0 cycle). Accordingly, if ACK is
read when the IBCR00:INTS bit is "1", you must write "0" to this bit in the transfer completion interrupt
triggered by the eighth SCL0 cycle so that another transfer completion interrupt will be triggered by the
ninth SCL0 cycle.
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