Reset Source Register (Rsrr) - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 7 RESET
7.2

Reset Source Register (RSRR)

The reset source register indicates the source or factor causing a reset that has been
generated.
Configuration of Reset Source Register (RSRR)
Address
0009
R0/WX : Undefined bit (Read value is "0", writting has no effect on operation)
R/WX : Read only (Readable, writting has no effect on operation)
- : Unused
X : Indeterminate
88
Figure 7.2-1 Reset Source Register (RSRR)
Bit7
Bit6 Bit5
- HWDR CSVR
H
R0/WX R/WX R/WX
Bit4
Bit3 Bit2
EXTS WDTR PONR
R/WX R/WX R/WX
Software reset flag bit
SWR
Read
0 -
1 Factor is software reset
Hardware reset flag bit
HWR
Read
0 -
1 Factor is hardware reset
Power-on reset flag bit
PONR
Read
0 -
1 Factor is power-on reset
Watchdog reset flag bit
WDTR
Read
0 -
1 Factor is watchdog reset
External reset flag bit
EXTS
Read
0 -
1 Factor is external reset
Clock supervisor reset flag bit
CSVR
Read
-
0
Factor is clock supervisor reset
1
Hardware Watchdog reset flag bit
HWDR
Read
-
0
Factor is hardware watchdog
1
reset
Initial value
Bit1 Bit0
xxxxxxxx
HWR SWR
R/WX R/WX
Write
Operation is not
affected
Write
Operation is not
affected
Write
Operation is not
affected
Write
Operation is not
affected
Write
Operation is not
affected
Write
Operation is not
affected
Write
Operation is not
affected
B