Fujitsu F2MC-8FX Hardware Manual page 260

CHAPTER 16 8/16-BIT COMPOSITE TIMER
Table 16.5-2 Functional Description of Each Bit of 8/16-bit Composite Timer 00/01 Control Status Register
1 (2 / 2)
Bit name
BF:
bit3
Data register full flag
IF:
bit2 Timer reload/overflow
flag
SO:
bit1 Timer output initial
value bit
OE:
bit0
Timer output enable bit
246
• This bit is set to "1" when a count value is stored in the 8/16-bit composite timer 00/01 data
register (T00DR/T01DR) upon completion of pulse width measurement in PWC timer function.
• This bit is set to "0" when the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) is read
during 8-bit operation.
• The 8/16-bit composite timer 00/01 data register (T00DR/T01DR) holds data with this bit
containing "1". Even when the next edge is detected with this bit containing "1", the count value is
not transferred to the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) and thus the
next measurement result is lost.
However, as the exception, when the H-pulse and cycle measurement (T00CR0/T01CR0: F3, F2,
F1, F0="1001 ") is selected, the H-pulse measurement result is transferred to the 8/16-bit
B
composite timer 00/01 data register (T00DR/T01DR) with this bit set to "1". The cycle
measurement result is not transferred to the 8/16-bit composite timer 00/01 data register with the
bit set to "1". For cycle measurement, therefore, the H-pulse measurement result must be read
before the cycle is completed. Note also that the result of H-pulse measurement or cycle
measurement is lost unless read before the completion of the next H pulse.
• The BF bit in the T00CR1 (timer 00) register is set to "0" when the T01DR (timer 01) register is
read during 16-bit operation.
• The BF bit in T01CR1 (timer 01) register is set to "0" during 16-bit operation.
• This bit is "0" when any timer function other than the PWC timer function has been selected.
• Writing to this bit has no effects on the operation.
This bit detects a match with a count value or a counter overflow.
• The bit is set to "1" when the 8/16-bit composite timer 00/01 data register (T00DR/T01DR) value
matches the count value during interval timer function (both one-shot and continuous mode) or
PWM timer function (variable-cycle mode).
• The bit is set to "1" when a counter overflow occurs during PWC or input capture function.
• This bit always returns "1" to a read-modify-write instruction.
• Writing "0" to the bit sets it to "0".
• Writing "1" to this bit has no effects on the operation.
• The bit is "0" when the PWM function (variable-cycle mode) has been selected.
• The IF bit in the T01CR1 (timer 01) register is "0" during 16-bit operation.
Writing to this bit sets the timer output (TMCR0:TO1/TO0) initial value. The value in this bit is
reflected in the timer output when the timer operation enable bit (T00CR1/T01CR1:STA) changes
from "0" to "1".
• During 16-bit operation (TMCR0:MOD = 1), use the SO bit in the T00CR1 (timer 00) register to
set the timer output initial value. In this case, the value of the S bit in the other register is
meaningless.
• An attempt to write to this bit is nullified during timer operation (T00CR1/T01CR1:STA = 1).
During 16-bit operation, however, a value can be written to the SO bit in the T01CR1 (timer 01)
register even during timer operation but it has no direct effect on the timer output.
• The value of this bit is meaningless when the PWM timer function (either fixed-cycle or variable-
cycle mode) or input capture function has been selected.
This bit enables or disabled timer output.
Writing "1" : supplies timer output (TMCR0:T01/TO0) to the external pin.
Writing "0" : prevents the timer output from being supplied to the external pin. In this case, the
external pin serves as a general-purpose port.
Function