Fujitsu F2MC-8FX Hardware Manual page 76

CHAPTER 6 CLOCK CONTROLLER
Notes:
• Set the standby mode after making sure that the transition to clock mode has been completed by comparing
the values of the clock mode monitor bits (SYCC:SCM1,0) and clock mode setting bits (SYCC:SCS1,0) in
the system clock control register.
• If you write "1" simultaneously to two or more of the stop bit (STP), sleep bit (SLP), software reset bit
(SRST), and watch bit (TMD), priority is given to them in the following order:
(1) Software reset bit (SRST)
(2) Stop bit (STP)
(3) Watch bit (TMD)
(4) Sleep bit (SLP)
When released from the standby mode, the device returns to the normal operating status.
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