Fujitsu F2MC-8FX Hardware Manual page 215

Counter value
(count down)
7FFF
H
Count value detected in
WATR:SWT3, 2, 1, 0
Count value detected in
WPCR:WTC1, 0
0000
H
1) Power-on reset
WTIF bit
WTIE bit
2) SLP bit
(STBC register)
3) STP bit
(STBC register)
• When setting interval time select bits in the watch prescaler control register (WPCR:WTC1, 0) to "11" (2
• WPCR:WTC1,0W: Interval time select bits in watch prescaler control register
• WPCR:WCLR
: Watch timer initialization bit in watch prescaler control register
• WPCR:WTIF
: Watch interrupt request flag bit in watch prescaler control register
• WPCR:WTIE
: Watch interrupt request enable bit in watch prescaler control register
• STBC:SLP
: Sleep bit in standby control register
• STBC:STP
: Stop bit in standby control register
• WATR:SWT
: Subclock oscillation stabilization wait time select bit in oscillation stabilization wait time setup register
Setup Procedure Example
The watch prescaler is set up in the following procedure:
Initial setup
1) Set the interrupt level.
2) Set the interval time.
3) Enable interrupts.
4) Clear the counter.
Processing interrupts
1) Clear the interrupt request flag.
2) Process any interrupt.
Figure 13.5-1 Operating Examples of Watch Prescaler
Subclock oscillation
4) Counter clear
stabilization wait time
Clear at interval
Interval cycle
(WPCR:WTC1, 0 = 11B)
(WPCR:WCLR = 1)
setup
Sleep
Sleep cancelled by
watch interrupt (WIRQ)
Stop cancelled by external interrupt
14
x 2/F )
CL
(ILR5)
(WPCR:WTC1, WTC0)
(WPCR:WTIE = 1)
(WPCR:WCLR = 1)
(WPCR:WTIF = 0)
CHAPTER 13 WATCH PRESCALER
Subclock oscillation
Clear by transferring
stabilization wait time
to stop mode
Clear in interrupt
processing routine
Stop
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