Fujitsu F2MC-8FX Hardware Manual page 100

CHAPTER 7 RESET
Overview of Reset Operation
During reset
Mode fetch
Normal
operation
(Run state)
In the case of a power-on reset/low-voltage detection reset, and a reset when in subclock mode or stop
mode, the CPU performs mode fetch after the main clock oscillation stabilization wait time has elapsed. If
the external reset input is not cleared after the oscillation stabilization wait time has elapsed, the CPU
performs mode fetch after the external reset input is cleared.
Effect of Reset on RAM Contents
When a reset occurs, the CPU halts the operation of the command currently being executed, and enters the
reset status. During RAM access execution, however, RAM access protection causes an internal reset signal
to be generated in synchronization with the machine clock, after RAM access has ended. This function
prevents a word-data write operation from being cut off by a reset after one byte.
Pin State During a Reset
When a reset occurs, all of the I/O ports and peripheral resource pins remain in a high impedance state until
setup is performed by software after the reset is released.
86
Figure 7.1-1 Reset Operation Flow
Software reset
Watchdog reset
Suppress resets
during RAM access
Subclock mode
During operation in
sub-PLL clock mode
NO
YES
Main clock oscillation
stabilization wait time
Reset state
External reset input
Suppress resets
during RAM access
In subclock mode,
or stop mode
NO
YES
Main clock oscillation
stabilization wait time
Reset state
Released from
external reset
YES
Capture mode data.
Capture reset vector.
Capture instruction code from the
address indicated by reset vector
and execute the instruction.
Power-on reset/
low-voltage detection
reset
Main clock oscillation
stabilization wait time
Reset state
NO