Fujitsu F2MC-8FX Hardware Manual page 353

Table 20.5-3 Functional Description of Each Bit of UART/SIO Serial Status and Data Register (SSR0)
Bit name
bit7, 6 Unused
PER:
bit5
Parity error flag
OVE:
bit4
Overrun error flag
FER:
bit3
Framing error flag
RDRF:
bit2 Receive data register
full
TCPL:
bit1 Transmission
completion flag
TDRE:
bit0 Transmission data
register empty
These bits are not used.
• Reading always returns "0".
• Writing to the bits has no effect on operation.
This flag detects a parity error in receive data.
• The bit is set when a parity error occurs during reception. Writing "0" to the RERC bit clears this
flag.
• If error detection and clearing by RERC occur at the same time, the error flag is set preferentially.
This flag detects an overrun error in receive data.
• The flag is set when an overrun error occurs during reception. Writing "0" to the RERC bit clears
this flag.
• If error detection and clearing by RERC occur at the same time, the error flag is set preferentially.
This flag detects a framing error in receive data.
• The bit is set when a framing error occurs during reception. Writing "0" to the RERC bit clears this
flag.
• If error detection and clearing by RERC occur at the same time, the error flag is set preferentially.
This flag indicates the status of the UART/SIO serial input data register.
• The bit is set to "1" when receive data is loaded to the serial input data register.
• The bit is cleared to "0" when data is read from the serial input data register.
This flag indicates the data transmission status.
• The bit is set to "1" upon completion of serial transmission. Note, however, that the bit is not set to
"1" even upon completion of transmission when the UART/SIO serial output data register contains
data to be transmitted in succession.
• Writing "0" to this bit clears its flag.
• If events to set and clear the flag occur at the same time, it is set preferentially.
• Writing "1" to this bit has no effect on operation.
This flag indicates the status of the UART/SIO serial output data register.
• The bit is set to "0" when transmit data is written to the serial output register.
• The bit is set to "1" when data is loaded to the transmission shift register and transmission starts.
CHAPTER 20 UART/SIO
Function
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