Fujitsu F2MC-8FX Hardware Manual page 569

Table A-1 MB95170J Series (4 / 6)
Register
Address
abbreviation
007C
ILR3
H
007D
ILR4
H
007E
ILR5
H
007F
-
H
0F80
WRARH0
H
0F81
WRARL0
H
0F82
WRDR0
H
0F83
WRARH1
H
0F84
WRARL1
H
0F85
WRDR1
H
0F86
WRARH2
H
0F87
WRARL2
H
0F88
WRDR2
H
0F89
H
to
0F91
H
0F92
T01CR0
H
0F93
T00CR0
H
0F94
T01DR
H
0F95
T00DR
H
0F96
TMCR0
H
0F97
T11CR0
H
0F98
T10CR0
H
0F99
T11DR
H
0F9A
T10DR
H
0F9B
TMCR1
H
0F9C
H
to -
0FA3
H
0FA4
PDCRH3
H
0FA5
PDCRL3
H
0FA6
PCSRH3
H
0FA7
PCSRL3
H
0FA8
PDUTH3
H
0FA9
PDUTL3
H
0FAA
PDCRH0
H
0FAB
PDCRL0
H
0FAC
PCSRH0
H
0FAD
PCSRL0
H
Register name
Interrupt level setting register 3
Interrupt level setting register 4
Interrupt level setting register 5
Wild register address setup register upper ch.0
Wild register address setup register lower ch.0
Wild register data setup register ch.0
Wild register address setup register upper ch.1
Wild register address setup register lower ch.1
Wild register data setup register ch.1
Wild register address setup register upper ch.2
Wild register address setup register lower ch.2
Wild register data setup register ch.2
8/16-bit composite timer 01 control status register 0 ch.0
8/16-bit composite timer 00 control status register 0 ch.0
8/16-bit composite timer 01 data register ch.0
8/16-bit composite timer 00 data register ch.0
8/16-bit composite timer 00/01 timer mode control register ch.0
8/16-bit composite timer 11 control status register 0 ch.1
8/16-bit composite timer 10 control status register 0 ch.1
8/16-bit composite timer 11 data register ch.1
8/16-bit composite timer 10 data register ch.1
8/16-bit composite timer 10/11 timer mode control register ch.1
16-bit PPG down counter register upper ch.3
16-bit PPG down counter register lower ch.3
16-bit PPG cycle setting buffer register upper ch.3
16-bit PPG cycle setting buffer register lower ch.3
16-bit duty setting buffer register upper ch.3
16-bit duty setting buffer register lower ch.3
16-bit PPG down counter register upper ch.0
16-bit PPG down counter register lower ch.0
16-bit PPG cycle setting buffer register upper ch.0
16-bit PPG cycle setting buffer register lower ch.0
(Vacancy)
(Vacancy)
(Vacancy)
APPENDIX A I/O Map
Initial
R/W
value
11111111
R/W
B
11111111
R/W
B
11111111
R/W
B
- -
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
00000000
R/W
B
- -
00000000
R
B
00000000
R
B
11111111
R/W
B
11111111
R/W
B
11111111
R/W
B
11111111
R/W
B
00000000
R
B
00000000
R
B
11111111
R/W
B
11111111
R/W
B
555