Interrupts Of Uart/Sio - Fujitsu F2MC-8FX Hardware Manual

CHAPTER 20 UART/SIO
20.6

Interrupts of UART/SIO

The UART/SIO has six interrupt-related bits: error flag bits (PER, OVE, FER), receive
data register full bit (RDRF), transmission data register empty bit (TDRE), and
transmission completion flag (TCPL).
Interrupts of UART/SIO
Table 20.6-1 lists the UART/SIO interrupt control bits and interrupt sources.
Table 20.6-1 UART/SIO Interrupt Control Bits and Interrupt Sources
Item
Interrupt request
SSR: TDRE
flag bit
Interrupt request
SMC2: TEIE
enable bit
Transmission data
Interrupt source
register empty
Transmission Interrupt
When transmit data is written to the UART/SIO serial output data register (TDR), the data is transferred to
the transmission shift register. When the next piece of data can be written, the TDRE bit is set to "1". At
this time, an interrupt request to the interrupt controller occurs when transmit data register empty interrupt
enable bit has been enabled (SMC2:TEIE = 1).
The TCPL bit is set to "1" upon completion of transmission of all pieces of transmit data. At this time, an
interrupt request to the interrupt controller occurs when transmission completion interrupt enable bit has
been enabled (SMC2:TCIE = 1).
Reception Interrupt
If the data is inputted successfully up to the stop bit, the RDRF bit is set to 1. If an overrun, parity, or
framing error occurs, the corresponding error flag bit (PER, OVE, or FER) is set to "1".
These bits are set when a stop bit is detected. If reception interrupt enable bit has been enabled (SMC2:RIE
= 1), an interrupt request to the interrupt controller will be generated.
CHAPTER 8 INTERRUPTS describes the interrupt request numbers and vector tables for all peripheral
functions.
Registers and Vector Table Related to UART/SIO Interrupts
Table 20.6-2 Registers and Vector Table Related to UART/SIO Interrupts
Interrupt
source
ch.0
ch: channel
342
SSR: TCPL SSR: RDRF
SMC2: TCIE SMC2: RIE
Transmission
Receive data full
completion
Interrupt level setting register
Interrupt
request No.
Register
IRQ4 ILR1
Description
SSR: PER
SMC2: RIE
Parity error
Setting bit
L04
SSR: OVE SSR: FER
SMC2: RIE SMC2: RIE
Overrun error Framing error
Vector table address
Upper Lower
FFF2 FFF3
H H