Interrupts; Interrupt Requests From Peripheral Functions - Fujitsu F2MC-8L F202RA Hardware Manual

CHAPTER 3 CPU
3.4

Interrupts

The MB89202/F202RA series supports 12 interrupt request inputs corresponding to
peripheral functions and allows an interrupt level to be assigned to each of the inputs.
The interrupt controller compares levels of interrupts generated by peripheral functions
when output of interrupt requests is allowed for peripheral functions. The CPU performs
the interrupt operation according to its interrupt acceptance settings. The CPU cancels
standby mode on reception of an interrupt request, then returns to the interrupt
operation or normal operation.
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Interrupt Requests from Peripheral Functions

Table 3.4-1 lists the interrupt requests that correspond to peripheral functions. When the CPU accepts an
interrupt, the CPU takes a branch to the interrupt processing routine using the address in the interrupt
vector table corresponding to the interrupt request as the branch address.
The interrupt level setting registers (ILR1, 2, 3, and 4) allow one of four interrupt processing intensities to
be assigned to each interrupt request.
Interrupt requests with levels equal to or less than that of an interrupt request being handled in the interrupt
processing routine are usually handled after the current interrupt processing routine ends. If interrupt
requests with the same assigned level are generated simultaneously, IRQ0 has priority.
Table 3.4-1 Interrupt Requests and Interrupt Vectors (1/2)
Interrupt request
IRQ0 (External interrupt INT10)
IRQ1 (External interrupt INT11)
IRQ2 (External interrupt INT12)
IRQ3 (8/16-bit capture timer/counter's timer)
IRQ4 (8/16-bit capture timer/counter's capture)
IRQ5 (Transmission with UART)
IRQ6 (Reception with UART)
IRQ7 (Time-base timer)
IRQ8 (A/D converter)
IRQ9 (8-bit PWM)
IRQA (External interrupt 2)
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Address in the
Names of bits in
vector table
the interrupt
level setting
Upper Lower
registers
digits digits
FFFA FFFB
H H
FFF8 FFF9
H H
FFF6 FFF7
H H
FFF4 FFF5
H H
FFF2 FFF3
H H
FFF0 FFF1
H H
FFEE FFEF
H H
FFEC FFED
H H
FFEA FFEB
H H
FFE8 FFE9
H H
FFE6 FFE7
H H
Priority at
identical level (at
simultaneous
occurrence)
L01, L00
High
L11, L10
L21, L20
L31, L30
L41, L40
L51, L50
L61, L60
L71, L70
L81, L80
L91, L90
Low
LA1, LA0