I 2 C Post Code Headers - Intel SR870BN4 - Server Platform - 0 MB RAM Product Manual

Fault Resilient Boot (FRB3) disable (Jumper pins 4 and 5)
Switch 1
S8A1
Recovery Boot:
Switch 2
Clear Password:
Switch 3
Clear CMOS:
Switch 4
Not Used
• Switch 5
BMC Update:
2
I C Post Code Headers
Both the I/O riser and the memory board have 5-pin headers (with the fourth pin removed) for the
2
I C POST-code card. The headers are J3A1 on the I/O riser card and J6C1 on the memory board.
2
The I C signals are from the ICH2's SMB bus. The data and clock signals are pulled up to 3.3 V
standby. Table 46 shows the pin assignments.
Table 46. J3A1 and J6C1 I
Pin Signal
1 12 V Standby
2 SMBDATA
3 SMBCLK
4 NC – pin removed
5 Ground
266
Switch 1 controls whether the system attempts to boot using BIOS
programmed in flash memory. By default, the system does not perform a
recovery boot using the BIOS.
OFF: System boots from BIOS programmed in flash memory. (Default
Setting)
ON: System initiates BIOS recovery boot procedure
Switch 2 controls whether a stored password is retained or cleared during a
system reset. By default the system retains this password.
OFF: Retains the System Password on Reset (Default Setting)
ON: Clears the System Password on Reset
Switch 3 controls whether settings stored in CMOS non-volatile memory
(NVRAM) are retained during a system reset. By default, the system does
not keep the default values in this register. You can configure switch 3 to
clear CMOS and restore the system defaults.
OFF: Keep current values in the CMOS Register (Default setting)
ON: Clear the CMOS Register and Restore the System Default Values
Switch 5 controls whether the BMC is in a firmware transfer mode and forces
an update to the BMC code.
OFF BMC Programming non-Forced (Default setting in production)
ON: BMC Programming Forced (Default setting in pre-beta)
2
C Post Code Headers
Intel® SR870BN4 Server System Product Guide