A Post Error Codes And Messages - Intel SR870BN4 - Server Platform - 0 MB RAM Product Manual

A POST Error Codes and Messages

Table 49 lists POST codes issued by SAL to I/O Port 0x80/0x81 during boot. The POST codes are
listed in the order of occurrence.
Depending on the code flow, some of the following POST codes will be displayed on an I
card connected to the memory board and/or I/O board. This port 80 card is a custom device
2
attached to I C ports in two different places on the server. One port 80 device serves the north flash
ROM and the other serves the south flash ROM.
NOTE
Some POST codes are not displayed here because of timing and interaction
delays with the BMC.
The SR870BN4 server employs a novel POST code scheme utilizing port 80h and 81h. This gives
the SR870BN4 16 bits to encode.
The following rules apply to the POST code encoding:
Bit 15: 1 – IA64 code being executed, 0 – IA32 code being executed
Bit 14: 1 – system stopped due to known failure, 0 – progress indication
All other module bits remain unmodified
Bit 13: 1 – fault or trap (no change in module numbers), 0 – normal execution
In case of fault or trap, only bit 13 is set and other bits are left on modified. This allows detection
of which module produced the fault.
Bit 12: Reserved
Bit 11-4: Module type
Bit 3-0: Sub module type
The module number and sub-module number are in 4-bit boundary to allow us to decode quickly by
the numbers. The module number identifies the major module such as Memory, PCI, ACPI and
etc. The sub-module identifies the sub-function such as SPD read in progress, ECC error, or
DIMM mismatch for Memory module.
Module names and numbers are listed in the following tables.
(Secret Decoder: Bit 11:8 – 0xF stack-less code being executed, 0xD-0x0 – memory is available.)
268 Intel® SR870BN4 Server System Product Guide
2
C debug