Figure 136. Main Board Jumper Locations; I 2 C Post Code Headers; Table 21. J3A1 And J6C1 I - Intel SR4850HW4 - Server Platform - 0 MB RAM Product Manual

Name
BMC RESET
FWHID
2
I C POST Code Headers
The main board has a 5-pin header (with the fourth pin removed) for the I
headers are J3A1 on the I/O riser card and J6C1 on the Memory board. The I
SMB bus in the Intel® 82801EB I/O Controller Hub 5. The data and clock signals are pulled up to
3.3 V standby. Table 21 shows the pin assignments.
Table 21. J3A1 and J6C1 I
Pin Signal
1 12 V Standby
2 SMBDATA
3 SMBCLK
4 NC – pin removed
5 Ground
Intel® Server Platforms SR4850HW4 & SR4850HW4/M Product Guide
Location Default
J8C2 Stuff
Empty
J8C3 Stuff
Empty

Figure 136. Main Board Jumper Locations

2
C POST Code Headers
Stuffed Jumper State
(Default in Bold)
1 – 2 = BMC enabled
2 – 3 = BMC Disabled
1-2 = Enables BMC controls FWHID swap
2-3 = Force FWHID swap
2
C POST-code card. The
2
C signals are from the
245