System Interconnection; Figure 133. Interconnect Block Diagram - Intel SR4850HW4 - Server Platform - 0 MB RAM Product Manual

System Interconnection

Front Panel Connectors
BASEBOARD
Aux. IPMB
Connector
Hot-swap
Backplane
Header
ICMB
Transceiver
Header
BBD COM1
EMP
5V
12V
3.3V
-12V
1.25V
3.3V Standby
LVDS-A Term
LVDS-B Term
Intel® Server Platforms SR4850HW4 & SR4850HW4/M Product Guide
DIMM SPD (16)
spkr
FRU EEPROM
DUAL
TCO
NIC
Chip Set
PCI PME
INTELLIGENT PLATFORM MANAGEMENT BUS (IPMB)
BASEBOARD
MANAGEMENT
CONTROLLER
(BMC)
System I/F
PORTS
SMM SMS
I/F I/F
System LPC Bus

Figure 133. Interconnect Block Diagram

FRU EEPROM
Temp Sensor
PROCESSOR SOCKETS(4)
Thermal Trip
CPU 'Core' Temp
CPU OEM NV CPU Voltage
CPU FRU
Baseboard
Temp 1
Logic 2.5V
FANs (6)
Non-volatile, read-write storage
SYSTEM SENSOR FRU INFO
EVENT DATA & CONFIG
LOG RECORDS DEFAULTS
- Chassis ID
CODE
RAM
(updateable) - Baseboard ID
- Power State
IMM
To Power
Distribution
Board
231