Subroutine Instructions; Interrupt Control Instructions - Omron SYSMAC CS1D-PD Series Operation Manual

Instruction Execution Times and Number of Steps

9-5-17 Subroutine Instructions

Instruction Mnemonic Code Length
SUBROU- SBS
TINE CALL
SUBROU- SBN
TINE ENTRY
SUBROU- RET
TINE
RETURN
MACRO MCRO
GLOBAL GSBN
SUBROU-
TINE CALL
GLOBAL GRET
SUBROU-
TINE ENTRY
GLOBAL GSBS
SUBROU-
TINE
RETURN

9-5-18 Interrupt Control Instructions

Instruction Mnemonic Code Length
SET INTER- MSKS
RUPT MASK
READ MSKR
INTER-
RUPT MASK
CLEAR CLI
INTERRUPT
DISABLE DI
INTER-
RUPTS
ENABLE EI
INTER-
RUPTS
Note
394
(steps)
CPU6@HA
(See
(Duplex CPU)
note 1.)
091 2 5.40
092 2 ---
093 1 0.86
099 4 21.7
751 2 ---
752 1 0.86
750 2 1.26
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
(steps)
CPU6@HA
(See
(Duplex CPU)
note 1.)
690 3 ---
(See note 2.)
692 3 ---
(See note 2.)
691 3 ---
(See note 2.)
693 1 15.3
694 1 15.0
1. When a double-length operand is used, add 1 to the value shown in the
length column in the following table.
2. Not supported by Duplex CPU Systems.
Execution time (µs)
CPU6@H CPU@@SA CPU6@S
(Duplex CPU) (Single (Single
CPU)
1.26 5.40 1.26
--- --- ---
0.86 0.86 0.86
23.3 21.7 23.3
--- --- ---
0.86 0.86 0.86
1.26 1.26 1.26
Execution time (µs)
CPU6@H CPU@@SA CPU6@S
(Duplex CPU) (Single (Single
CPU)
--- 26.2 25.6
(See note 2.)
--- 11.4 11.9
(See note 2.)
--- 31.1 27.4
(See note 2.)
15.0 15.3 15.0
19.5 15.0 19.5
Section 9-5
Conditions
CPU4@S
(Single
CPU) CPU)
1.96 ---
--- ---
1.60 ---
23.3 ---
--- ---
1.60 ---
1.96 ---
Conditions
CPU4@S
(Single
CPU) CPU)
38.4 ---
11.9 ---
41.3 ---
16.8 ---
21.8 ---