Logic Instructions - Omron SYSMAC CS1D-PD Series Operation Manual

Instruction Execution Times and Number of Steps
Instruction Mnemonic Code Length
ASCII-TO-4- NUM4
DIGIT NUM-
BER
ASCII-TO-8- NUM8
DIGIT NUM-
BER
ASCII-TO- NUM16
16-DIGIT
NUMBER
Note

9-5-11 Logic Instructions

Instruction Mnemonic Code Length
LOGICAL ANDW
AND
DOUBLE ANDL
LOGICAL
AND
LOGICAL ORW
OR
DOUBLE ORWL
LOGICAL
OR
EXCLUSIVE XORW
OR
DOUBLE XORL
EXCLUSIVE
OR
EXCLUSIVE XNRW
NOR
DOUBLE XNRL
EXCLUSIVE
NOR
COMPLE- COM
MENT
DOUBLE COML
COMPLE-
MENT
(steps)
CPU6@HA
(See
(Duplex CPU)
note 1.)
604 3 11.4
605 3 11.7
606 3 11.5
1. When a double-length operand is used, add 1 to the value shown in the
length column in the following table.
2. Not supported by Duplex CPU Systems.
3. Not supported by CS1D-CPU@@H/P and CS1D-CPU@@S.
(steps)
CPU6@HA
(See
(Duplex CPU)
note 1.)
034 4 0.20
610 4 0.36
035 4 0.22
611 4 0.36
036 4 0.22
612 4 0.36
037 4 0.22
613 4 0.36
029 2 0.28
614 2 0.48
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
Execution time (µs)
CPU6@H CPU@@SA CPU6@S
(Duplex CPU) (Single (Single
CPU)
--- 11.3 ---
(See note 3.) (See
note 3.)
11.6
11.4
Execution time (µs)
CPU6@H CPU@@SA CPU6@S
(Duplex CPU) (Single (Single
CPU)
0.18 0.18 0.18
0.32 0.32 0.32
0.22 0.22 0.22
0.32 0.32 0.32
0.22 0.22 0.22
0.32 0.32 0.32
0.22 0.22 0.22
0.32 0.32 0.32
0.22 0.22 0.22
0.40 0.40 0.40
Section 9-5
Conditions
CPU4@S
(Single
CPU) CPU)
---
(See
note 3.)
Conditions
CPU4@S
(Single
CPU) CPU)
0.20 ---
0.34 ---
0.32 ---
0.34 ---
0.32 ---
0.34 ---
0.32 ---
0.34 ---
0.32 ---
0.56 ---
387