Timer And Counter Instructions - Omron SYSMAC CS1D-PD Series Operation Manual

Instruction Execution Times and Number of Steps
9-5-4

Timer and Counter Instructions

Instruction Mnemonic Code Length
TIMER TIM
TIMX
COUNTER CNT
CNTX
HIGH- TIMH
SPEED
TIMHX
TIMER
ONE-MS TMHH
TIMER
TMHHX
ACCUMU- TTIM
LATIVE
TIMER
TTIMX
LONG TIML
TIMER
TIMLX
MULTI-OUT- MTIM
PUT TIMER
MTIMX
REVERS- CNTR
IBLE
CNTRX
COUNTER
RESET CNR
TIMER/
COUNTER
CNRX
(steps)
CPU6@HA
(See
(Duplex CPU)
note 1.)
--- 3 0.72
550 3 0.72
--- 3 0.72
546 3 0.72
015 3 0.72
551 3 0.72
540 3 12.9
552 3 12.9
087 3 13.9
9.8
7.4
555 3 13.9
9.8
7.4
542 4 7.4
6.0
553 4 7.4
6.0
543 4 18.0
5.6
554 4 18.0
5.6
012 3 13.6
548 3 13.6
545 3 9.4
3.92 ms
547 3 9.4
3.92 ms
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
Execution time (µs)
CPU6@H CPU@@SA CPU6@S
(Duplex CPU) (Single (Single
CPU)
0.56 0.56 0.56
0.56 0.56 0.56
0.56 0.56 0.56
0.56 0.56 0.56
0.88 0.60 0.88
0.88 0.60 0.88
12.5 0.86 0.86
12.5 0.86 0.86
16.1 13.2 16.1
10.9 9.4 10.9
8.5 7.3 8.5
16.1 13.2 16.1
10.9 9.4 10.9
8.5 7.3 8.5
7.6 7.3 7.6
6.2 6.0 6.2
7.6 7.3 7.6
6.2 6.0 6.2
20.9 16.2 20.9
5.6 5.6 5.6
20.9 16.2 20.9
5.6 5.6 5.6
16.9 13.6 16.9
16.9 13.6 16.9
9.9 8.8 9.9
4.16 ms 3.06 ms 4.16 ms 4.16 ms When resetting
9.9 8.8 9.9
4.16 ms 3.06 ms 4.16 ms 4.16 ms When resetting
Section 9-5
Conditions
CPU4@S
(Single
CPU) CPU)
0.88 ---
0.88 ---
0.88 ---
0.88 ---
1.14 ---
1.14 ---
1.12 ---
1.12 ---
17.0 ---
11.4 When resetting
8.7 When interlock-
ing
17.0 ---
11.4 When resetting
8.7 When interlock-
ing
10.0 ---
6.5 When interlock-
ing
10.0 ---
6.5 When interlock-
ing
23.3 ---
5.8 When resetting
23.3 ---
5.8 When resetting
19.0 ---
19.0 ---
10.6 When resetting 1
word
1,000 words
10.6 When resetting 1
word
1,000 words
377