Increment/Decrement Instructions - Omron SYSMAC CS1D-PD Series Operation Manual

Instruction Execution Times and Number of Steps
Instruction Mnemonic Code Length
SHIFT N-BIT NSFL
DATA LEFT
SHIFT N-BIT NSFR
DATA
RIGHT
SHIFT N- NASL
BITS LEFT
DOUBLE NSLL
SHIFT N-
BITS LEFT
SHIFT N- NASR
BITS RIGHT
DOUBLE NSRL
SHIFT N-
BITS RIGHT
9-5-8

Increment/Decrement Instructions

Instruction Mnemonic Code Length
INCRE- ++
MENT
BINARY
OUBLE ++L
INCRE-
MENT
BINARY
−−
DECRE-
MENT
BINARY
−−L
DOUBLE
DECRE-
MENT
BINARY
INCRE- ++B
MENT BCD
DOUBLE ++BL
INCRE-
MENT BCD
−−B
DECRE-
MENT BCD
−−BL
DOUBLE
DECRE-
MENT BCD
382
(steps)
CPU6@HA
(See
(Duplex CPU)
note 1.)
578 4 4.3
37.5
579 4 4.9
74.2
580 3 0.19
582 3 0.37
581 3 0.20
583 3 0.38
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
(steps)
CPU6@HA
(See
(Duplex CPU)
note 1.)
590 2 0.25
591 2 0.44
592 2 0.25
593 2 0.44
594 2 6.5
595 2 5.3
596 2 6.5
597 2 5.5
Note When a double-length operand is used, add 1 to the value shown in the length
column in the following table.
Execution time (µs)
CPU6@H CPU@@SA CPU6@S
(Duplex CPU) (Single (Single
CPU)
7.5 4.3 7.5
40.3 37.5 40.3
7.5 4.9 7.5
50.5 45.6 50.5
0.22 0.19 0.22
0.40 0.37 0.40
0.22 0.20 0.22
0.40 0.38 0.40
Execution time (µs)
CPU6@H CPU@@SA CPU6@S
(Duplex CPU) (Single (Single
CPU)
0.22 0.22 0.22
0.40 0.40 0.40
0.22 0.22 0.22
0.40 0.40 0.40
6.4 6.5 6.4
5.6 5.2 5.6
6.3 6.5 6.3
5.3 5.4 5.3
Section 9-5
Conditions
CPU4@S
(Single
CPU) CPU)
8.3 Shifting 1 bit
45.4 Shifting 1,000
bits
8.3 Shifting 1 bit
55.3 Shifting 1,000
bits
0.32 ---
0.56 ---
0.32 ---
0.56 ---
Conditions
CPU4@S
(Single
CPU) CPU)
0.32 ---
0.56 ---
0.32 ---
0.56 ---
4.5 ---
4.9 ---
4.6 ---
4.7 ---