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Cat. No. W405-E1-16

SYSMAC CS Series

CS1D-CPUHA/H CPU Units

CS1D-CPUSA/S CPU Units

CS1D-DPL01/02D Duplex Unit

CS1D-PA/PD Power Supply Unit

CS1D Duplex System

OPERATION MANUAL

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Summary of Contents for Omron SYSMAC CS1D-PD Series

Page 1 Cat. No. W405-E1-16 SYSMAC CS Series CS1D-CPUHA/H CPU Units CS1D-CPUSA/S CPU Units CS1D-DPL01/02D Duplex Unit CS1D-PA/PD Power Supply Unit CS1D Duplex System OPERATION MANUAL...
Page 2 No patent liability is assumed with respect to the use of the information contained herein. Moreover, because OMRON is constantly striving to improve its high-quality products, the information contained in this manual is subject to change without notice. Every precaution has been taken in the preparation of this manual. Neverthe- less, OMRON assumes no responsibility for errors or omissions.
Page 3 CS1D-CPUHA/H CPU Units CS1D-CPUSA/S CPU Units CS1D-DPL01/02D Duplex Unit CS1D-PA/PD Power Supply Unit CS1D Duplex System Operation Manual Revised September 2024...
Page 5 OMRON Product References All OMRON products are capitalized in this manual. The word “Unit” is also capitalized when it refers to an OMRON product, regardless of whether or not it appears in the proper name of the product.
Page 6 Example for Unit version 2.0 Lot No. 031001 0000 Ver.2.0 OMRON Corporation MADE IN JAPAN • CS1-H, CJ1-H, and CJ1M CPU Units (except for low-end models) manu- factured on or before November 4, 2003 do not have a unit version given on the CPU Unit (i.e., the location for the unit version shown above is...
Page 7 Unit version Use the above display to confirm the unit version of the CPU Unit. Unit Manufacturing Information In the IO Table Window, right-click and select Unit Manufacturing informa- tion - CPU Unit. The following Unit Manufacturing information Dialog Box will be displayed. Unit version Use the above display to confirm the unit version of the CPU Unit connected online.
Page 8 CPU Units on which no unit version is given Units on which a version is given (Ver. @.@) Lot No. XXXXXX XXXX Ver. @.@ Lot No. XXXXXX XXXX OMRON Corporation MADE IN JAPAN OMRON Corporation MADE IN JAPAN Meaning CS1H-CPU67H CPU Unit Ver. @.@ Designating individual CPU Pre-Ver.
Page 9 System Configuration Support by Unit Version System configuration CS1D-CPU@@HA/H/P CS1D-CPU@@SA/S Pre-Ver. 1.1 Ver. 1.1 Ver. 1.2 Ver. 1.3 Ver. 1.4 Ver. 4.0 Ver. 2.0 Ver. 2.1 Ver. 4.0 Duplex CPU, Dual I/O Expansion System Duplex CPU, Single I/O Expansion System Single CPU System 1.
Page 10 Function CS1D-CPU@@H/P CS1D-CPU@@HA CS1D- CS1D- CPU@@S CPU@@SA Duplex-CPU Systems Single CPU Systems Pre- Ver. Ver. Ver. 1.3 Ver. 4.0 Ver. 2.0 Ver.4.0 Ver. 1.1 to 1.4 to 2.1 With Without Duplex CPU Duplex CPU Compatible Compatible Setting Setting Setting First Slot Words OK for OK for up to 64...
Page 11 Function CS1D-CPU@@H/P CS1D- CS1D-CPU@@S CS1D- CPU@@HA CPU@@SA Duplex-CPU Systems Single CPU Systems Pre-Ver. Ver. 1.4 Ver. 4.0 Ver. 2.0 Ver. 2.1 Ver.4.0 1.1 to 1.3 PLC Setup: Communications Instruction Setting within FB: Retransmission Cycle Response Monitor Time: Communications Instruction within FB DeviceNet Communications Instruc- tion within FB Serial Gateway Function (Conversion from...
Page 12 Unit Versions and Programming Devices The following tables show the relationship between unit versions and CX-Pro- grammer versions. Unit Versions and Programming Devices OK: Available, ---: Unavailable CPU Unit Functions CX-Programmer Program- ming Ver. 3.3 Ver. 4.0 Ver. 6.1 Ver. 7.0 Ver.
Page 13 Device Type Setting The unit version does not affect the setting made for the device type on the CX-Programmer. Select the device type as shown in the following table regardless of the unit version of the CPU Unit. Series CPU Unit group CPU Unit model Device type setting on CX-Programmer Ver.
Page 14 Troubleshooting Problems with Unit Versions on the CX-Programmer Problem Cause Solution An attempt was made using CX- Check the program or change Programmer version 4.0 or higher the CPU Unit being down- to download a program contain- loaded to a CPU Unit Ver. 2.0 ing instructions supported only by or later.
Page 15 TABLE OF CONTENTS PRECAUTIONS ........xxv Intended Audience .
Page 16 TABLE OF CONTENTS SECTION 5 Installation and Wiring ......159 Fail-safe Circuits ............Installation .
Page 17 TABLE OF CONTENTS 8-19 Task Flags ............. . . 8-20 Condition Flags .
Page 18 TABLE OF CONTENTS Revision History ........631 xviii...
Page 19 About this Manual: This manual describes the installation and operation of the CS1D Duplex Programmable Controllers (PLCs) and includes the sections described below. The CS Series and CJ Series are subdivided as shown in the following table. Unit CS Series CJ Series CPU Units CS1-H CPU Units: CS1H-CPU@@H...
Page 20 About this Manual, Continued Name Cat. No. Contents SYSMAC CS Series W405 Provides an outline of and describes the design, CS1D-CPU@@HA/H CPU Units installation, maintenance, and other basic operations CS1D-CPU@@SA/S CPU Units for a Duplex System based on CS1D CPU Units. CS1D-DPL01/02D Duplex Unit (This manual) CS1D-PA/PD@@@ Power Supply Unit...
Page 21 Omron’s exclusive warranty is that the Products will be free from defects in materials and workmanship for a period of twelve months from the date of sale by Omron (or such other period expressed in writing by Omron). Omron disclaims all other warranties, express or implied.
Page 22 Disclaimers Performance Data Data presented in Omron Company websites, catalogs and other materials is provided as a guide for the user in determining suitability and does not constitute a warranty. It may represent the result of Omron’s test conditions, and the user must correlate it to actual application requirements. Actual per- formance is subject to the Omron’s Warranty and Limitations of Liability.
Page 23 xxiii...
Page 24 xxiv...
Page 25 PRECAUTIONS This section provides general precautions for using the CS1D Programmable Controllers (PLCs) and related devices, including the CS1D-CPUHA/H CPU Units for Duplex CPU Systems, CS1D-CPUSA/S CPU Units for Single CPU Systems, CS1D-DPL01 Duplex Unit, and CS1D-PA/PD Power Supply Unit. The information contained in this section is important for the safe and reliable application of Programmable Controllers.
Page 26 It is extremely important that a PLC and all PLC Units be used for the speci- fied purpose and under the specified conditions, especially in applications that can directly or indirectly affect human life. You must consult with your OMRON representative before applying a PLC System to the above-men- tioned applications. Safety Precautions The CPU Unit refreshes I/O even when the program is stopped (i.e., even in...
Page 27 Safety Precautions Do not touch any of the terminals or terminal blocks while the power is being supplied. Doing so may result in electric shock. Do not attempt to disassemble, repair, or modify any Units. Any attempt to do so may result in malfunction, fire, or electric shock. Do not touch the Power Supply Unit while power is being supplied or immedi- ately after power has been turned OFF.
Page 28 Safety Precautions Security measures to prevent unauthorized access Take the following measures to prevent unauthorized access to our products. • Install physical controls so that only authorized personnel can access control systems and equipment. • Reduce connections to control systems and equipment via networks to prevent access from untrusted devices.
Page 29 Safety Precautions Confirm safety before transferring data files stored in the file memory (Mem- ory Card or EM file memory) to the I/O area (CIO) of the CPU Unit using a peripheral tool. Otherwise, the devices connected to the output unit may mal- function regardless of the operation mode of the CPU Unit.
Page 30 Operating Environment Precautions Operating Environment Precautions Do not operate the control system in the following locations: • Locations subject to direct sunlight. • Locations subject to temperatures or humidity outside the range specified in the specifications. • Locations subject to condensation as the result of severe changes in tem- perature.
Page 31 Application Precautions Application Precautions Observe the following precautions when using the PLC System. • Do not use the C200H/CS-series Power Supply Units (C200H-P) in a CS1D PLC. System operation will not be dependable and may stop. • Do not use a CS1D Power Supply Unit (CS1D-PA/PD) for any PLC other than a CS1D PLC.
Page 32 Application Precautions • When replacing a Duplex Unit online in a Duplex CPU, Dual I/O Expan- sion System, always follow the procedure provided in this operation man- ual. • When replacing a Connecting Cable or Expansion Unit online in a Duplex CPU, Dual I/O Expansion System, always follow the procedure provided in this operation manual.
Page 33 Application Precautions • Always turn OFF the reserved pin (RSV) of the Duplex Unit's Communi- cations Setting DIP Switch. • Never connect pin 6 (5-V power supply) on the RS-232C port on the CPU Unit to any device other than an NT-AL001, CJ1W-CIF11 Adapter, or NV3W-M20L Programmable Terminal.
Page 34 Application Precautions will be written to the EM Area. Refer to information on file operations in the CS/CJ Series Programming Manual for details. • Always turn ON power to the PLC before turning ON power to the control system. If the PLC power supply is turned ON after the control power sup- ply, temporary errors may result in control system signals because the output terminals on DC Output Units and other Units will momentarily turn ON when power is turned ON to the PLC.
Page 35 Application Precautions • Do not apply voltages or connect loads to the Output Units in excess of the maximum switching capacity. Excess voltage or loads may result in burning. • Disconnect the functional ground terminal when performing withstand voltage tests. Not disconnecting the functional ground terminal may result in burning.
Page 36 Application Precautions • When replacing parts, be sure to confirm that the rating of a new part is correct. Not doing so may result in malfunction or burning. • Before touching a Unit, be sure to first touch a grounded metallic object in order to discharge any static build-up.
Page 37 Concepts EMC Directives OMRON devices that comply with EU Directives also conform to the related EMC standards so that they can be more easily built into other devices or the overall machine. The actual products have been checked for conformity to EMC standards (see the following note).
Page 38 Conformance to EU Directives Relay Output Noise Reduction Methods The CS1D Duplex PLCs conforms to the Common Emission Standards (EN61000-6-4) of the EMC Directives. However, noise generated by relay output switching may not satisfy these Standards. In such a case, a noise filter must be connected to the load side or other appropriate countermeasures must be provided external to the PLC.
Page 39 Conformance to EU Directives Circuit Current Characteristic Required element The diode connected in parallel with The reversed dielectric strength value Diode method the load changes energy accumulated of the diode must be at least 10 times by the coil into a current, which then as large as the circuit voltage value.
Page 40 Conformance to EU Directives...
Page 41 SECTION 1 Features and System Configuration This section introduces the features and system configuration of a CS1D Duplex PLC System. CS1D Duplex System Overview and Features ......1-1-1 CS1D Duplex System Overview .
Page 42 Section 1-1 CS1D Duplex System Overview and Features CS1D Duplex System Overview and Features 1-1-1 CS1D Duplex System Overview The CS1D Duplex System is a highly reliable Programmable Controller (PLC) System. By providing duplex CPU Units, Power Supply Units, and Communi- cations Units, the CS1D can continue control operations and be restored with no need to shut down the entire system in the event of an error or malfunction.
Page 43 Section 1-1 CS1D Duplex System Overview and Features Duplex CPU, Single I/O Expansion System Duplex Unit Communications Units CS1D CPU Units for (Controller Link Units) Duplex CPU Systems CS1D Power Supply Units DPL01 DPL STATUS ERR/ALM ACTIVE ERR/ALM CPU STATUS BKUP ACTIVE BKUP...
Page 44 Section 1-1 CS1D Duplex System Overview and Features 1. There is no need to incorporate special programming for duplex opera- 1,2,3... tions, such as programming to switch when an error occurs, and thus there is no need for the duplex setup to be considered in individual parameter settings.
Page 45 Section 1-1 CS1D Duplex System Overview and Features Identical unit numbers and node addresses Identical unit numbers and node addresses System with duplex communications System with duplex communications Fiber-optic cable (ring connection) CLK: Controller Link Unit CPU: CPU Unit DPL: Duplex Unit PSU: Power Supply Unit System with duplex communications System without duplex communications...
Page 46 Section 1-1 CS1D Duplex System Overview and Features Note A Duplex CPU, Dual I/O Expansion System requires compatible Duplex Units, CPU Backplane, Expansion Backplanes, I/O Control Units, I/O Interface Units, and Duplex CPU Units with unit version 1.3 or later. Duplex Connecting Cables When the Connecting Cable between the CPU Rack and Expansion Racks is duplexed, the system can continue operating through the second Cable if one...
Page 47 Function blocks can be created with CX-Programmer Ver. 9.7 or higher by the user and pasted into normal programs. The standard function blocks provided by OMRON in the OMRON FB Library can also be pasted into normal pro- grams. Function blocks enable standard processing to be simply inserted into a program as a single unit.
Page 48 Section 1-1 CS1D Duplex System Overview and Features Text String Support in Function Blocks Text strings can be used in ST programming to easily create text string processing programs. Production 06/05/28 File name log file Black Black: 9 LineA.txt created. White: 18 White Blue: 7...
Page 49 Section 1-1 CS1D Duplex System Overview and Features • Program index files (CX-Programmer section names, section comments, and program comments) CX-Programmer Ver. 9.7 or later Comment/section data can be stored in the actual PLC when downloading projects. Project CPU Unit Symbol table file Transfer Comment file...
Page 50 Section 1-1 CS1D Duplex System Overview and Features Free Running Timer The system timers used after the power is turned ON are contained in the fol- lowing Auxiliary Area words. Name Address Function Access 10-ms Incrementing A000 This word contains the system timer Read-only Free Running Timer used after the power is turned ON.
Page 51 Section 1-2 System Configuration • Special Instructions for function blocks: GET VARIABLE ID instruction (GETID): Outputs the FINS command variable type (data area) code and word address for the specified variable or address. • Numerical value to ASCII conversion instructions and ASCII to numerical value conversion instructions: 4/8/16-digit numerical value to ASCII data conversion instruction (STR4/ STR8/STR16):...
Page 52 Section 1-2 System Configuration Details on the CPU Units are provided in this manual. For details on the Loop Control Boards, refer to the Loop Control Boards Operation Manual (W406) and the Loop Control Board Function Block Reference Manual (W407). 2.
Page 53 Section 1-2 System Configuration 1.2 or earlier is mounted, an I/O bus error will occur and the system will not operate. Name Model number Contents Duplex Unit CS1D-DPL02D The Duplex Unit is the Unit that controls duplex system operation. It (Especially for a monitors for errors and switches operation when an error occurs.
Page 54 Section 1-2 System Configuration CS1D CPU Rack for a Duplex CPU, Single I/O Expansion System 2) CS1D-CPU65H/67H/65P/67P/ 1) CS1D-DPL01 67HA/68HA CPU Units for 4) CS1D-BC052 CPU 3) CS1D-PA207R Duplex Unit Duplex CPU Systems Backplane for Duplex CPU CS1D-PD024/025 Systems (See note.) Power Supply Units DPL01 DPL STATUS...
Page 55 Section 1-2 System Configuration CS1D CPU Rack for a Single CPU System CS1D-BC082S 1) CS1D-CPU@@SA/S CPU Unit 2) CS1D-PA207R CPU Backplane for Single CPU Systems CS1D-PD024/025 for Single CPU Systems (See note.) Power Supply Units ERR/ALM BKUP PRPHL COMM SYSMAC CS1D-CPU67H PROGRAMMABLE CONTROLLER MCPWR...
Page 56 Section 1-2 System Configuration CS1D-IC102D I/O Control Units CS1D-DPL02D CS1D-CPU@@HA/P/H CPU (See note.) Duplex Unit Units for Duplex CPU Systems (See note.) (unit version 1.3 or later) CS1D-BC042D CPU Backplane (see note) for Duplex CPU Systems CS1D CPU Rack CS1W-CN@@3 CS1 Connecting Cables Up to 3 Units can be mounted.
Page 57 Section 1-2 System Configuration CS1D-CPU@@SA/S CS1D-BC082S CS1D-CPU@@HA/P/H CPU Unit for CS1D-BC052 CPU CPU Backplane CPU Units for Single CPU Systems CS1D-DPL01 Backplane for for Single CPU Systems Duplex CPU Systems Duplex Unit Duplex CPU Systems CS1D CPU Rack CS1W-CN@@3 CS-series Connecting Maximum of 5 Units can be mounted.
Page 58 Section 1-2 System Configuration CS1D CPU Rack + CS1D Long-distance Expansion Racks for a Duplex CPU Single I/O Expansion System or Single CPU System The same Backplanes for Long-distance Expansion Racks are used in both Duplex CPU Single I/O Expansion Systems and Single CPU Systems. Use the following CS1D Expansion Backplane, which is specifically for the CS1D System.
Page 59 SECTION 2 Specifications, Nomenclature, and Functions This section provides the specifications, defines the nomenclature, and describes the functions of CS1D PLCs. Specifications ..........2-1-1 Individual Specifications .
Page 60 Units for Duplex CPU, Dual I/O Expansion Systems ....2-9-1 CS1D-IC102D I/O Control Unit ......2-9-2 CS1D-II102D I/O Interface Unit.
Page 61 Section 2-1 Specifications Specifications 2-1-1 Individual Specifications CS1D CPU Units Item Specifications Duplex CPU Systems Single CPU Systems Model number CS1D- CS1D- CS1D- CS1D- CS1D- CS1D- CS1D- CS1D- CS1D- CS1D- CPU67H CPU68H CPU65H CPU67H CPU44S CPU67S CPU42S CPU44S CPU65S CPU67S Number of I/O 5,120 points 5,120 points...
Page 62 Section 2-1 Specifications 2-1-2 Duplex Specifications System Configuration and Basic Functions Item Specifications Reference Functional The following CPU Units are equivalent in terms of basic functions (I/O points, 3-1-7 Duplex CPU Sys- equivalence program capacity, DM capacity, and instruction execution speed). tem Restrictions of existing CS1D-CPU68HA: No equivalent model...
Page 63 Section 2-1 Specifications Item Specifications Reference Duplex CS1D Duplex Mode A Duplex CPU System can be operated in either of the fol- 1-2-1 CS1D Duplex CPU Units lowing two modes: Systems (Supported Duplex Mode (DPL) only in Duplex The system operates with CS1D CPU Units and CS1D CPU Sys- Power Supply Units in duplex status.
Page 64 Section 2-1 Specifications Item Specifications Reference Duplex CS1D Operation with two Power is supplied to the Backplane simultaneously by two 3-2 Duplex Power Sup- Power Sup- CS1D Power Sup- CS1D Power Supply Units. (The load for each CS1D ply Units ply Units ply Units mounted Power Supply Unit is approximately one half.)
Page 65 Section 2-1 Specifications Specifications with Application Restrictions Item Specifications Reference Programming CX-Programmer CX-Programmer Ver. 3. or lower: 2-6-2 Precautions Device oper- when Connecting Pro- • The Duplex CPU System uses the CS1D-CPU@@H, ating restric- gramming Devices to so select “CS1H-H” as the device type. tions Duplex CPU Systems •...
Page 66 Section 2-1 Specifications Item Specifications Reference Restrictions The CS1D CPU Units for Duplex CPU Systems do not support any interrupt 3-1-7 Duplex CPU Sys- on interrupts functions. tem Restrictions (Duplex CPU Power OFF interrupt tasks, scheduled interrupt tasks, I/O interrupt tasks, and Appendix E Precau- Systems only) external interrupt tasks cannot be used in either Duplex or Simplex Mode.
Page 67 Section 2-1 Specifications 2-1-3 Common Specifications other than Duplex Specifications Item Specifications Reference Control method Stored program I/O control method Cyclic scan and immediate processing (by IORF only) are both supported. Note Immediate refresh cannot be used in CS1D Duplex-CPU Systems. It can be used in Single CPU Systems.
Page 68 Section 2-1 Specifications Item Specifications Reference Starting subroutines from mul- Supported (by global subroutines). Programming Manual (W394) tiple starts I/O Area 5,120: CIO 000000 to CIO 031915 (320 words from CIO Input bits The CIO Area (Core I/O) 0000 to CIO 0319) can be used Output bits Area...
Page 69 Section 2-1 Specifications Item Specifications Reference Internal I/O 4,800 (300 words): CIO 120000 to CIO 149915 (words 8-3 I/O Area (Core I/O) Area CIO 1200 to CIO 1499) Area, Work 37,504 (2,344 words): CIO 380000 to CIO 614315 (words Areas CIO 3800 to CIO 6143) These bits in the CIO Area are used as work bits in pro- gramming to control program execution.
Page 70 Section 2-1 Specifications Item Specifications Reference Extended Data Memory (EM) 32 Kwords per bank, 25 banks max.: E0_00000 to 8-16 Extended Data Memory Area E18_32767 max. (Not available on some CPU Units.) (E18) Area Used as a general-purpose data area for reading and writing data in word units (16 bits).
Page 71 Section 2-1 Specifications Function Specifications Reference Timing of special Data links for Controller Link Units and SYSMAC LINK 9-1-3 I/O Refreshing and Peripheral refreshing for CPU Units, remote I/O for DeviceNet Units, and other special Servicing Bus Units refreshing for CPU Bus Units is performed at the I/O refresh period and when the CPU BUS UNIT I/O REFRESH (DLNK(226)) instruction is executed.
Page 72 Section 2-1 Specifications Function Specifications Reference Error check User-defined errors (i.e., user can define fatal errors and Failure diagnosis: Programming non-fatal errors) Manual (W394) The FPD(269) instruction can be used to check the execu- Fatal and nonfatal errors: SECTION tion time and logic of each programming block. 10 Troubleshooting FAL and FALS instructions can be used with the CS1-H User-defined errors: Programming...
Page 73 Section 2-1 Specifications Function Specifications Reference Multiple-level commu- Duplex CPU Systems: 3 levels nications Single CPU Systems: 8 levels Note Communications are possible across up to eight levels only for the Controller Link and Ethernet net- works (and the CX-Integrator or CX-Net in CX-Pro- grammer version 4.0 or higher is required to set the routing tables).
Page 74 Section 2-1 Specifications Item Specifications CS1D Power Supply Unit CS1D-PA207R CS1D-PD024 CS1D-PD025 RUN output Contact configu- SPST-NO Not provided. Not provided. (See note 3.) ration Switch capacity 240 V AC, 2A (resistive load) 120 V AC, 0.5 A (induction load) 24 V DC, 2A (resistive load) 24 V DC, 2 A (induction...
Page 75 Section 2-2 Configuration Devices 4. The depth (D) is 123 mm for the CS1D-PD024. Configuration Devices 2-2-1 CPU Rack Expansion Patterns Duplex CPU, Dual I/O Expansion Systems CS1D-DPL02D CS1D-BC042D CPU Backplane CS1D-CPU65H/67H/65P/67P/ Duplex Unit for Duplex CPU Systems 67HA/68HA CPU Units for CS1D-PA207R Duplex CPU Systems CS1D-PD024/PD025...
Page 76 Section 2-2 Configuration Devices Rack Configurations Rack name Devices Remarks Two Units (or one) are CPU Rack for CPU Units for Duplex CPU Sys- Duplex CPU, Dual tems (unit version 1.3 or later) required. I/O Expansion Sys- (See note 1.) tems CS1D Power Supply Units Two Units (or one) are...
Page 77 Section 2-2 Configuration Devices Devices CPU Units Two CS1D CPU Units of the same model are required when using Duplex CPU Units in a Duplex CPU System. Name Model Specifications CPU Units for CS1D-CPU67HA I/O bits: 5,120; program capacity: 250 Ksteps; Duplex CPU Data memory: 448 Kwords System...
Page 78 Section 2-2 Configuration Devices Power Supply Units Two CS1D Power Supply Units are required for a duplex power supply config- uration. Name Model Specifications CS1D Power Supply CS1D- 100 to 120 V AC; 200 to 240 V AC (RUN Units PA207R output) Output capacity:...
Page 79 Section 2-2 Configuration Devices Name Model Specifications Programming Device XW2Z-200S-CV Connects IBM PC/AT or compatible Connecting Cables computers. (for RS-232C port) D-Sub 9-pin (Length: 2.0 m), Static- resistant connector used. XW2Z-500S-CV Connects IBM PC/AT or compatible computers. D-Sub 9-pin (Length: 5.0 m), Static- resistant connector used.
Page 80 Section 2-2 Configuration Devices Expansion Patterns CS1D CPU Rack + CS1D Expansion Racks (Duplex CPU, Dual I/O Expansion System) ■ Configuration with Duplex Connecting Cables CS1D-IC102D CS1D-DPL02D CS1D-CPU@@HA/P/H CPU I/O Control Units Duplex Unit Units for Duplex CPU Systems (unit version 1.3 or later) CS1D-BC042D CPU Backplane (see note) for CS1D CPU Rack...
Page 81 Section 2-2 Configuration Devices ■ Configuration with Single Connecting Cable CS1D-IC102D I/O Control Unit CS1D-DPL02D CS1D-CPU@@HA/P/H CPU Duplex Unit Units for Duplex CPU Systems (unit version 1.3 or later) CS1D-BC042D CPU Backplane for Duplex CPU Systems CS1D CPU Rack CS1W-CN@@3 CS1 Connecting Up to 4 Units can be mounted.
Page 82 Section 2-2 Configuration Devices CS1D CPU Rack + CS1D Expansion Racks (Duplex CPU, Single I/O Expansion System) CS1D-BC082S CS1D-CPU@@SA/S CS1D-BC052 CPU CS1D-CPU@@HA/P/ CPU Backplane for CPU Unit for Backplane for H CPU Units for CS1D-DPL01 Single CPU Systems Single CPU Systems Duplex CPU Systems Duplex CPU Systems Duplex Unit...
Page 83 Section 2-2 Configuration Devices CS1D CPU Rack + CS1D Long-distance Expansion Racks (Duplex CPU, Single I/O Expansion System) CS1D-CPU@@HA/P/ CS1D-CPU@@SA/S CS1D-BC082S CS1D-BC052 H CPU Unit CPU Backplane for CPU Unit for CS1D-DPL01 CPU Backplane for Single CPU Systems Single CPU Systems Duplex Unit Duplex CPU Systems CS1D...
Page 84 Section 2-2 Configuration Devices Model Number of Expansion Racks CS1D-CPU42S CS1D-CPU44S CS1D-CPU65S CS1D-CPU67S Rack Configurations Name Configuration Remarks CS1D Expansion CS1D Online Replacement One Backplane is required. Racks Expansion Backplane CS1D Power Supply Units Two Units (or one) are required. Duplex CPU, Dual I/O Expan- One (or two) CS1D I/O Con- sion System...
Page 85 Section 2-2 Configuration Devices CS1D Power Supply Units Two CS1D Power Supply Units are required for a duplex configuration. Name Model Specifications CS1D Power Supply CS1D-PA207R 100 to 120 V AC or 200 to 240 V AC Units (RUN output) Output capacity: 5 V DC, 7 A;...
Page 86 Section 2-2 Configuration Devices Devices for Long-distance Expansion Racks Name Model Specifications Remarks I/O Control Unit CS1W-IC102 Mounts to the leftmost slot on the CS1D CPU Rack to enable connecting CS1D Long-distance Expansion Racks. I/O Interface Unit CS1W-II102 Mounts to the leftmost slot on a Long-distance Expan- sion Rack.
Page 87 Section 2-2 Configuration Devices CS1D Configuration The following table shows the Units, Programming Devices, and Support Soft- Devices ware that can be used to configure a CS1D Duplex System. Note Always use the specified CS1D Units for the CPU Units, Power Supply Units, CPU Backplanes, and Expansion Backplanes.
Page 88 Section 2-2 Configuration Devices Name Model Support Remarks Duplex CPU, Duplex CPU, Single Dual I/O Single I/O Expansion Expansion System System System Expan- Online Replace- CS1D-BI082D Use specified CS1D Units sion ment Expan- (for a Duplex CPU, only. Back- sion Backplane Dual I/O Expansion CS-series Units cannot be planes...
Page 89 Section 2-2 Configuration Devices Name Model Support Remarks Duplex Single System System Basic I/O Units CS-series Basic I/O Units Yes CS1W-INT01 CS-series Restricted Can be used only as Standard I/O Interrupt Input Units Units in Duplex CPU Systems. C200H Basic I/O Units C200H I/O Units cannot be used.
Page 90 Section 2-3 Duplex Unit Name Model Support Remarks Duplex Single System System 0.3 m CS1W-CN313 Use to connect between Expansion series Racks or between Expansion Rack 0.7 m CS1W-CN713 Connect- and CPU Rack. CS1W-CN223 Cables CS1W-CN323 CS1W-CN523 10 m CS1W-CN133 12 m CS1W-CN133-B2 Long-...
Page 91 Section 2-3 Duplex Unit 2-3-2 Nomenclature DPL STATUS (Green/Red) Displays duplex status (green) and duplex error status (red). DPL02D L/ACTIVE CPU (Green) DPL STATUS ON when active CPU Unit is on the left. ACTIVE L/CPU STATUS (Green/Red) CPU STATUS Displays the operation mode (RUN, ACTIVE MONITOR, or PROGRAM) of the left CPU STATUS...
Page 92 Section 2-3 Duplex Unit Duplex Unit Operating Switch NO USE Setting Contents Application Turns ON power to Turns ON or OFF the Set to NO USE when the Duplex Unit. power supply to the replacing a Duplex Unit. Duplex Unit. while leaving the power NO USE Turns OFF power to...
Page 93 Section 2-3 Duplex Unit Initial Switch Press the Initial Switch to toggle between Duplex Mode and Simplex Mode after a CS1D CPU Unit has been replaced. INIT. Setting Contents Application The Mode Setting Reflects the status Press to return to Duplex Switch is enabled (Duplex/Simplex Mode) of the Mode after a CS1D CPU Unit...
Page 94 Section 2-3 Duplex Unit by peripheral bus to a baud rate other than those that are automatically de- tected, the auto-detection function will not work. 2. The order of automatic detection is as follows: 9,600 bps, 19,200 bps, 38,400 bps, and then 115,200 bps. If the Programming Device is in a mode other than peripheral bus, or if it is set by peripheral bus to a baud rate oth- er than those that are automatically detected, the auto-detection function will not work.
Page 95 Section 2-3 Duplex Unit Duplex Unit Indicators DPL01 DPL STATUS ACTIVE CPU STATUS ACTIVE CPU STATUS Indicator Status Contents Description DPL STATUS Green The System is operating The active and standby CPU Units are operating (ON) normally in Duplex Mode. normally in synchronization in Duplex Mode.
Page 96 Section 2-3 Duplex Unit Indicator Status Contents Description ACTIVE Green The left CPU Unit is active The left CPU Unit is the active (i.e., controlling) (ON) (ACT). CPU Unit. The left CPU Unit is on Either the left CPU Unit is on standby or the standby (STB).
Page 97 Section 2-3 Duplex Unit Indicator Status Contents Description ACTIVE Green The right CPU Unit is active The right CPU Unit is the active (i.e., controlling) (ON) (ACT). CPU Unit. The right CPU Unit is on Either the right CPU Unit is on standby or the standby (STB).
Page 98 Section 2-3 Duplex Unit Indicator Status when The following table shows the status of Duplex Unit indicators when errors Errors Occur occur during Duplex Mode operation (i.e., in either RUN Mode or MONITOR Mode). In this example, the left (L) CPU Unit is set as the active one (ACT.LEFT).
Page 99 Section 2-4 CPU Units CPU Units 2-4-1 Models Number of I/O Programming Data Memory Model Weight points (Number (DM + EM) of Expansion Racks) CPU Units for Duplex CPU 5,120 points 250 Ksteps 448 Kwords CS1D-CPU67HA 350 g max. Systems (7 Racks) 400 Ksteps 832 Kwords...
Page 100 Section 2-4 CPU Units 2-4-2 Components Inner Board Connector Install an Inner Lit green when the CPU Unit is Board. (See note.) operating normally in MONITOR or RUN mode. Peripheral Port Connects ERR/ALM Programming Lit read when a fatal error was Device (including discovered in self-diagnosis or a Programming...
Page 101 Section 2-4 CPU Units Indicators (LED) ERR/ALM BKUP PRPHL COMM Indicator Color Status Meaning Green CPU Unit is operating normally in MONITOR or RUN mode. Flashing DIP switch settings error. PLC has stopped operating while in PROGRAM mode, or has stopped operating due to a fatal error. ERR/ALM Red A fatal error has occurred (including FALS instruction execution), or a hardware error (CPU error) has...
Page 102 Section 2-4 CPU Units MCPWR BUSY OPEN PERIPHERAL Indicator Color Status Meaning MCPWR Green Power is being supplied to the Memory Card. Flashing Flashes once: Simple backup write, read, or verify normal. Flashes five times: Simple backup read error. Flashes three times: Simple backup read warning.
Page 103 Section 2-4 CPU Units Pin No. Setting Function Application Default 4 to 6 See below. Simple backup type Used to determine the simple backup type. (See note 3.) Normally turn this pin OFF. Always Keep set to Always OFF. Note If the power is turned on with Pin 7 and OFF.
Page 104 Section 2-4 CPU Units Note 1. When pin 1 is set to ON, writing is prohibited for the user program and all parameter data (PLC Setup, I/O table registration, etc.). Moreover, it is not possible to clear the user program or parameters even by executing a memory clear operation from a Programming Device.
Page 105 Section 2-4 CPU Units Memory Card, etc.). The user program and the Parameter Area data will thus not be lost even if battery voltage drops. CPU Unit Built-in RAM I/O Memory Area Backup Battery The battery life is 5 years at an Drive 1: EM file ambient temperature of 25⊕...
Page 106 Section 2-4 CPU Units 2-4-4 Battery Compartment and Peripheral Port Covers Opening the Battery Insert a small flat-blade screwdriver into the opening at the bottom of the bat- Compartment Cover tery compartment cover and lift open the cover. Insert a small flat-blade screwdriver into the opening at the bottom of the battery compartment cover and lift...
Page 107 Section 2-5 File Memory 2-4-5 Dimensions 104.3 100.5 ERR/ALM BKUP PRPHL COMM SYSMAC CS1D-CPU67H PROGRAMMABLE CONTROLLER OPEN MCPWR BUSY OPEN 130 134 PERIPHERAL PORT (Backplane) 22.3 File Memory For CS1D CPU Units, the Memory Card and a specified part of the EM Area can be used to store files.
Page 108 Section 2-5 File Memory 3. For precautions regarding the use of Memory Cards, refer to 5-1 File Mem- ory in the SYSMAC CS/CJ/NSJ Series Programmable Controllers Pro- gramming Manual (W394). 2-5-1 File Memory Functions in Duplex CPU Systems Only the Memory Card in the active CPU Unit is accessed, whereas EM file memory is accessed for both the active and standby CPU Units.
Page 109 Section 2-5 File Memory Memory Card Functions The following table shows the operations of the various Memory Card-related functions. Function Memory Card location Data unification Notes processing method Installed Installed in active in standby CPU Unit CPU Unit Writing to Memory Accessed.
Page 110 Section 2-5 File Memory EM File Memory-related The following table shows the operations of the EM file memory-related func- Functions tions. Function EM file memory Data matching method Note In active In standby CPU Unit CPU Unit Writing to EM file Accessed.
Page 111 Section 2-5 File Memory Simple Backup Files File type Contents File name Data files Words allocated to Special I/O BACKUP .IOM Units, CPU Bus Units, and Inner Boards in the DM Area CIO area BACKUPIO .IOR DM Area BACKUPDM .IOM EM area BACKUPE@ (@: .IOM...
Page 112 Section 2-5 File Memory 2-5-4 Using File Memory Note For details on using file memory, refer to the CS/CJ-series Programming Manual. Memory Cards Reading/Writing Files Using Programming Device File File name and extension Data transfer direction ∗∗∗∗∗∗∗∗.OBJ Program files Between CPU Unit and Mem- ory Card, ∗∗∗∗∗∗∗∗.IOM I/O memory files...
Page 113 Section 2-5 File Memory Reading and Replacing Program Files during Operation File File name and extension Data transfer direction ∗∗∗∗∗∗∗∗.OBJ Program files Memory Card to CPU Unit 1. Install a Memory Card into the CPU Unit. 1,2,3... 2. Set the following information: Program File Name (A654 to A657) and Pro- gram Password (A651).
Page 114 Section 2-5 File Memory Reading/Writing I/O Memory Files inside the EM File Memory Using (FREAD(700), FWRIT(701), and TWRIT(704)) Instruction for File Memory File File name and extension Data transfer direction ∗∗∗∗∗∗∗∗.IOM I/O memory files Between CPU Unit and EM file memory 1.
Page 115 Section 2-5 File Memory 1. Pull the top end of the Memory Card cover forward and remove from the 1,2,3... Unit. 2. Insert the Memory Card with the label facing to the right. (Insert with the ∆ on the Memory Card label and the on the CPU Unit facing each other.) Product label 3.
Page 116 Section 2-5 File Memory 2. Press the Memory Card eject button after the BUSY indicator is no longer lit. BUSY indicator BUSY Memory Card eject button 3. The Memory Card will eject from the compartment. 4. Remove the Memory Card cover when a Memory Card is not being used. Note 1.
Page 117 Section 2-6 Programming Devices Note When a Memory Card is inserted into a computer using a Memory Card Adapter, it can be used as a standard storage device, like a floppy disk or hard disk. Programming Devices 2-6-1 Overview There are two types of Programming Devices that can be used: the Hand- held Programming Consoles or the CX-Programmer, which is operated on a Windows computer.
Page 118 Section 2-6 Programming Devices CX-Programmer There are differences in functions depending on the version of CX-Program- mer connected to the CS1D PLC. These are listed in the following table. Duplex CPU Single CPU Remarks Programmer Systems Systems Version 2.@ or Not sup- Not sup- This version cannot be used for...
Page 119 Section 2-6 Programming Devices 2. If cables with model numbers ending in -V instead of -CV are used to con- nect the computer running the CX-Programmer to the RS-232C port (in- cluding when using a CS1W-CN118 Cable), a peripheral bus connection cannot be used.
Page 120 Section 2-6 Programming Devices Using an RS-232C Cable for an IBM PC/AT or Compatible Unit Unit port Computer Computer Serial Model Length Cable port communications notes mode CPU Units Built-in IBM PC/AT D-Sub, 9-pin, Host Link XW2Z-200S-V 2 m RS-232C or compatible male XW2Z-500S-V 5 m...
Page 121 Section 2-6 Programming Devices Peripheral Port Specifications Protocol PLC Setup and Duplex Unit DIP Switch Settings PRPHL Peripheral port settings (in PLC Setup) Default value: 0 hex NT Link: 2 hex Peripheral bus: 4 hex Host Link: 5 hex Programming Console or CX-Programmer through peripheral bus (automatically detects the Program- ming Device’s communications parameters) Host computer or CX- PT (NT Link)
Page 122 Plug (9-pin male) Hood Note Use the special cables provided from OMRON for all connections whenever possible. If cables are produced in-house, be sure they are wired correctly. External devices and the CPU Unit may be damaged if general purpose (e.g., computer to modem) cables are used or if wiring is not correct.
Page 123 Section 2-6 Programming Devices RS-232C Port Specifications Item Specification Communications method Half duplex Synchronization Start-stop Baud rate 0.3/0.6/1.2/2.4/4.8/9.6/19.2/38.4/57.6/115.2 kbps (See note.) Transmission distance 15 m max. Interface EIA RS-232C Protocol Host Link, NT Link, 1:N, No-protocol, or peripheral bus Note Baud rates for the RS-232C are specified only up to 19.2 kbps. The CS Series supports serial communications from 38.4 kbps to 115.2 kbps, but some com- puters cannot support these speeds.
Page 124 Section 2-6 Programming Devices 2. If connected to the RS-232C port of the standby CPU Unit, neither reading nor writing can be executed from the CX-Programmer. Reading only, how- ever, can be enabled by means of the Standby CPU Unit RS-232C Port Setting in the PLC Setup.
Page 125 Section 2-6 Programming Devices transmission path. When only the NT-AL001 is used, the total length of the transmission path can be a maximum of 500 m. Leaving a PT or Host Computer Connected Constantly to RS-232C Port If a PT (Programmable Terminal) or host computer (running SCADA software) is left connected constantly for monitoring a Duplex CPU System, and if the connection is only to the active CPU Unit, then writing will become impossible when an operation switching error occurs and the active CPU Unit becomes...
Page 126 Section 2-7 Power Supply Units Personal Computer Connection Example In this example, communications between the CPU Unit and the personal computer are continued even after an operation switching error occurs. Active CPU Unit Standby CPU Unit Personal computer D P L01 R U N D P L S T A T U S R U N...
Page 127 Section 2-7 Power Supply Units current consumption under the condition of one Power Supply Unit. If two dif- ferent kinds of Power Supply Units are to be used, calculate the current con- sumption using the output of the smaller-capacity Power Supply Unit. 2-7-2 CS1D Power Supply Unit Models Power supply...
Page 128 Section 2-7 Power Supply Units Ground to a resistance of 100 Ω or less to avoid electric shock. RUN Output An internal contact turns ON when the CPU Unit is operating in RUN or MON- ITOR mode. Any of the RUN outputs at the CPU Rack, an Expansion Rack, or a Long-distance Rack can be used.
Page 129 Section 2-8 Backplanes Backplanes 2-8-1 CPU Backplanes Model Model Number of slots Application Weight CS1D-BC042D 3 to 5 Duplex CPU, Dual I/O 1,600 g max. Expansion Systems CS1D-BC052 Duplex CPU, Single I/O 1,600 g max. Expansion Systems CS1D-BC082S Single CPU Systems 1,600 g max.
Page 130 Section 2-8 Backplanes CPU Backplane for Single CPU Systems: CS1D-BC082S 6.25 Slots for mounting Backplane mounting screws CS-series Units Power Supply Unit connectors (two) Connecting Cable connector CS-series Unit connectors CPU Unit for Single CPU Systems connectors Note To protect unused connectors, always cover them with CV500-COV01 I/O Unit Connector Covers (sold separately) or mount the CS1W-SP001 Spacer Unit (sold separately).
Page 131 Section 2-8 Backplanes Dimensions CPU Backplane for Duplex CPU, Dual I/O Expansion Systems: CS1D-BC042D 505.1 6.25 17.1 CPU Backplane for Duplex CPU, Single I/O Expansion Systems: CS1D-BC052 6.25 17.1 505.1 26.8 CPU Backplane for Single CPU Systems: CS1D-BC082S 505.1 6.25 17.1 26.8 2-8-2...
Page 132 Section 2-8 Backplanes Nomenclature Backplane for Duplex CPU, Dual I/O Expansion Systems: CS1D-BI082D Slots for mounting Units Backplane mounting screws (Four M4 screws) Unit connectors Power Supply Unit Slot for Expansion Slot for either Expansion Unit connectors (two) Unit only or I/O Unit CPU Backplane for Duplex CPU, Single I/O Expansion Systems or Single CPU Systems: CS1D-BI092 Backplane mounting screws...
Page 133 Section 2-9 Units for Duplex CPU, Dual I/O Expansion Systems When using only one Power Supply Unit, cover the unused Power Supply Unit connector with a C500-COV01 Power Supply Unit Connector Covers (sold separately). Name Model I/O Unit Connector Cover CV500-COV01 I/O Unit Spacer Unit CS1W-SP001...
Page 134 Section 2-9 Units for Duplex CPU, Dual I/O Expansion Systems Nomenclature and Functions LED Indicators Connector to CS1D I/O Interface Unit's IN Connector LED Indicators Indicator Status Meaning RDY (Green) ON (lit) Operating normally. OFF (not lit) • PLC error •...
Page 135 Section 2-9 Units for Duplex CPU, Dual I/O Expansion Systems CS1D-IC102D I/O Control Units Slot 0 Slot 1 CS1D CPU Rack CS1W-CN@@3 CS-series Connecting Cables Note: Use cables of the same length. Duplex Connecting Cables connect to next Rack. Note 1.
Page 136 Section 2-9 Units for Duplex CPU, Dual I/O Expansion Systems If mounted here, a CS-series Basic I/O Unit, Special I/O Unit, or CPU Bus Unit will not operate. CS1D-IC102D I/O Control Unit Slot 0 Slot 1 CS1D CPU Rack Single Connecting Cable connects to next Rack.
Page 137 Section 2-9 Units for Duplex CPU, Dual I/O Expansion Systems Dimensions (mm) 12.5 100.5 25.6 34.5 Connecting the Units Mount the CS1D I/O Interface Unit in either slot 0 or slot 1 (or mount Units in both slots) of the CS1D-BI082D Expansion Backplane. If CS1D I/O Interface Units are mounted in slot 0 and slot 1, the Connecting Cables can be duplexed.
Page 138 Section 2-10 Units on CS1D Long-distance Expansion Racks If a CS1D I/O Interface Unit is mounted in slot 0 only, a Basic I/O Unit, Special I/O Unit, or CPU Bus Unit can be used in slot 1. Single Connecting Cable connects to previous Rack.
Page 139 Section 2-10 Units on CS1D Long-distance Expansion Racks Part Names and Functions IC102 Indicators TERM ERR OUT A OUT B Connector to Backplane Connector to I/O Interface Connector to I/O Interface Unit of series A Unit of series B Indicators Indicator Status Meaning...
Page 140 Section 2-10 Units on CS1D Long-distance Expansion Racks When Mounting to CPU Rack Connect the Backplane connector to the I/O expansion connector. IC102 TER ERR LEFT CPU RIGHT CPU Connect to I/O CPU Rack DPL SW cable connector. INIT. DUPLEX Series A Series B Note An I/O Control Unit cannot be mounted on an Expansion Backplane.
Page 141 Section 2-10 Units on CS1D Long-distance Expansion Racks Dimensions and Weight II102 236.5 34.5 Backplane Weight: 300 max. (including connector to Backplane) Connection Method Connect the I/O Interface Unit to the input I/O cable connector on the Back- plane (left side). Always connect a Terminator (CV500-TER01) to the connec- tor for the next Rack when it is not used (i.e., on the last Long-distance Expansion Rack in the series).
Page 142 Section 2-11 Basic I/O Units Model number Length CV500-CN222 CV500-CN322 CV500-CN522 CV500-CN132 10 m CV500-CN232 20 m CV500-CN332 30 m CV500-CN432 40 m CV500-CN532 50 m 2-11 Basic I/O Units 2-11-1 CS-series Basic I/O Units with Terminal Blocks Name Specifications Model Page Basic Input Units...
Page 143 Section 2-11 Basic I/O Units Components and Switch Settings CS-series Basic Input Units (20-pin Terminal Block) Unit mounting hooks Hooked onto Back- plane to mount Unit. I/O indicator Model label Terminal block connector (20-pin) 20-pin terminal block 16-point Unit CS1W-ID211 16-point Units CS1W-OD212 CS1W-INT01...
Page 144 Section 2-11 Basic I/O Units 2-11-2 Interrupt Input Units An Interrupt Input Unit can be used to input interrupts for a Single CPU Sys- tem. With a Duplex CPU System, however, interrupt inputs cannot be used, i.e., the Interrupt Input Unit will function only as a standard 16-point Input Unit. Model Model Specifications...
Page 145 Section 2-11 Basic I/O Units Input Signal Width High-speed input signals must meet the following conditions for the ON time. ON OFF Model ON time CS1W-IDP01 0.1 ms min. Dimensions The High-speed Input Unit has the same dimensions as the Units with a 20- terminal block.
Page 146 Section 2-11 Basic I/O Units Unit mounting hooks Model label Hooked onto Back- plane to mount Unit. I/O indicators Display Switch for 64-point I/O Units 56-pin I/O wiring connectors × 2 DISPLAY Display switch 0, 1 2, 3 Area 1 Area 2 Unit lock notch (Attach Unit to Back-...
Page 147 Section 2-11 Basic I/O Units Dimensions Units with One 40-pin connector (a) CS1W-ID231 CS1W-OD231 CS1W-OD232 Units with Two 40-pin connectors (b) CS1W-ID261 CS1W-OD261 CS1W-OD262 CS1W-MD261 CS1W-MD262 Units with 56-pin connectors (c) CS1W-ID291 CS1W-OD291 CS1W-OD292 CS1W-MD291 CS1W-MD292 Using Soldered or Crimped Connector Approx.
Page 148 Section 2-12 Unit Current Consumption Using Pressure-welded Connector Connecting Cables: XW2Z-R@@@C-@@@-@@@ XW2Z-@@@ 2-12 Unit Current Consumption There are fixed amounts of current and power that can be provided to the Units on the Rack. Even when using only one Power Supply Unit, design the system so that the total current consumption of Units on the Rack does not exceed the values for the maximum Power Supply Unit current and the maxi- mum total power.
Page 149 Section 2-12 Unit Current Consumption Note 1. When duplexing by combining the CS1D-PA207R and CS1D-PD024, de- sign the total current consumption for all Units on the Rack to be within the power supply capacity of the CS1D-PD024. 2. When duplexing by combining the CS1D-PA207R and CS1D-PD025, de- sign the total current consumption for all Units on the Rack to be within the power supply capacity for the CS1D-PA207R.
Page 150 Section 2-12 Unit Current Consumption 2-12-3 Current Consumption Tables Note For the current consumption of Units not shown in these tables, refer to the individual user manuals for those Units. 5-V Voltage Group Name Model Current consumption CPU Backplane for Single CPU Systems CS1D-BC082S 0.17 CPU Backplane for Duplex CPU, Dual I/O...
Page 151 Section 2-12 Unit Current Consumption Basic I/O Units Name Model Current consumption (A) DC Input Units CS1W-ID211 0.10 CS1W-ID231 0.15 CS1W-ID261 0.15 CS1W-ID291 0.20 AC Input Unit CS1W-IA111 0.11 CS1W-IA211 0.11 B7A Input Unit CS1W-B7A12 0.09 Interrupt Input Unit CS1W-INT01 0.10 High-speed Input Unit CS1W-IDP01...
Page 152 Section 2-12 Unit Current Consumption Name Model Current consumption (A) Isolated DC Input Unit CS1W-PDC01 0.15 CS1W-PDC11 0.12 CS1W-PDC55 0.18 Isolated Control Output Unit CS1W-PMV01 0.15 (Analog Output Unit) CS1W-PMV02 0.12 Power Transducer Input Unit CS1W-PTR01 0.15 DC Input Unit (100 mV) CS1W-PTR02 0.15 Isolated Pulse Input Unit...
Page 153 Section 2-13 CPU Bus Unit Setting Area Capacity Name Model Current consumption (A) MECHATROLINK-II Position CS1W-NC271 0.36 Control Units CS1W-NC471 0.36 CS1W-NCF71 0.36 SYSMAC SPU Units (High- CS1W-SPU01-V2 0.56 speed Data Storage Units) CS1W-SPU02-V2 0.70 Note NT-AL001 Link Adapters consume an additional 0.15 A each when used. Add 0.04 A for each CJ1W-CIF11 RS-422A Adapter that is used.
Page 154 Section 2-14 I/O Table Settings There is a limit to the capacity of the CPU Bus Unit Setting Area of 10,752 bytes (10 Kbytes). The system must be designed so that the number of words used in the CPU Bus Unit Setting Area by all of the CPU Bus Units and the Inner Board does not exceed this capacity.
Page 155 Section 2-14 I/O Table Settings 2-14-1 Basic I/O Units Name Model Unit type AC Input Unit CS1W-IA111 16-point Input Unit CS1W-IA211 16-point Input Unit DC Input Unit CS1W-ID211 16-point Input Unit CS1W-ID231 32-point Input Unit CS1W-ID261 64-point Input Unit CS1W-ID291 96-point Input Unit TTL I/O Unit CS1W-MD561...
Page 156 Section 2-14 I/O Table Settings 2-14-2 CS-series Special I/O Units Name Model Unit type Number of unit Allocated words numbers Inputs Outputs Analog I/O Unit CS1W-MAD44 Other Special I/O Units Analog Input Units CS1W-AD041/081(-V1) Other Special I/O Units Analog Output Units CS1W-DA041/08V/08C Other Special I/O Units Isolated Thermocouple CS1W-PTS01-V1/11...
Page 157 Section 2-14 I/O Table Settings 2-14-3 CS-series CPU Bus Units Name Model Unit type Controller Link Units CS1W-CLK11 Controller Link Unit CS1W-CLK21/12/52-V1 Serial Communications Unit CS1W-SCU21-V1 Serial Communications Unit Ethernet Units CS1W-ETN21 Ethernet Unit CS1D Ethernet Unit CS1D-ETN21D CS1D Ethernet Unit (See note.) NX Service Units CS1W-NXS01/11...
Page 158 Section 2-14 I/O Table Settings...
Page 159 SECTION 3 Duplex Functions This section describes the basic operation of a Duplex System. Duplex CPU Units..........3-1-1 Duplex CPU Systems .
Page 160 Section 3-1 Duplex CPU Units Duplex CPU Units 3-1-1 Duplex CPU Systems A Duplex CPU System consists of two CPU Units for Duplex CPU Systems and one Duplex Unit mounted to a CS1D Backplane for Duplex CPU Sys- tems. Note 1.
Page 161 Section 3-1 Duplex CPU Units • The present mode status is displayed by the DPL STATUS indicator on the Duplex Unit (green flashing: Duplex Mode; OFF: Simplex Mode). It can also be checked by means of A32808 in the Auxiliary Area (ON: Duplex Mode, OFF: Simplex Mode).
Page 162 Section 3-1 Duplex CPU Units Cyclic Operations Active CPU Unit Standby CPU Unit Startup processing Startup processing Duplex initialization Duplex initialization Common cyclic Common cyclic processing processing User program User program execution execution Synchronized processing Synchronized Synchronized instructions (See note.) instructions (See note.) Beginning of duplex synchronization Transfer processing...
Page 163 Section 3-1 Duplex CPU Units Processing Duplex-related processing User program execu- The same user program is executed. tion Synchronized instructions (see note) are executed simulta- neously for both the active and standby CPU Units. Note These instructions include IORF(097) (I/O REFRESH), DLINK(226) (CPU BUS UNIT I/O REFRESH), IORD(222) (INTELLIGENT I/O READ), IOWR(223) (INTELLIGENT I/O WRITE), PID(190) (PID),...
Page 164 Section 3-1 Duplex CPU Units • Fatal Inner Board error: Fatal Inner Board Error Flag (A40112) turns ON. (This is a fatal error for Single CPU Systems or the CS1-H.) (Process- control CPU Units only) • FALS error: FALS Error Flag (A40106) turns ON. (Previously this was a fatal error.) •...
Page 165 Section 3-1 Duplex CPU Units Time when Switching Occurred Words Description A024 to A026 The time at which the mode was switched from Duplex Mode to Simplex Mode is stored as follows: A02400 to A02407: Second (00 to 59) A02408 to A02415: Minute (00 to 59) A02500 to A02507: Hour (00 to 23) A02508 to A02515: Day (01 to 31) A02600 to A02607: Month (01 to 12)
Page 166 Section 3-1 Duplex CPU Units Duplex Mode Standby Active (Duplex error) Simplex Mode Remains in Remains standby in active status status (cannot be switched) 3-1-4 Automatic Recovery to Duplex Operation by Self-diagnosis After the mode has been switched from Duplex Mode to Simplex Mode due to an operation switching error or a duplex error, an automatic attempt is made to return to Duplex Mode if this function has been enabled in the PLC Setup.
Page 167 Section 3-1 Duplex CPU Units reason the standby CPU Unit previously failed (i.e., the reason for switch- ing to Simplex Operation) or the time the switch was made, use A019 (rea- sons for switching) and A020 to A022 (time of switching). 3-1-5 Duplex Initialization In Duplex Mode, duplex initialization is executed automatically at certain times...
Page 168 Section 3-1 Duplex CPU Units Maximum cycle time = Normal cycle time + α α (Maximum time beyond normal cycle time) CS1D CPU Unit model CS1D-CPU67HA 520 ms CS1D-CPU68HA 900 ms CS1D-CPU65H 190 ms + A CS1D-CPU67H 520 ms + A A is the time added when duplex Inner Boards are mounted.
Page 169 Section 3-1 Duplex CPU Units • When using new functions is specified If duplex operation is prevented by a Duplex Verification Error, duplex opera- tion can be recovered by stopping functions on the active CPU Unit that are not supported by the standby CPU Unit. When a CPU Unit Version Verifica- tion Error has occurred, the flags in A804 can be checked to identify the func- tions that are not supported in the standby CPU Unit.
Page 170 Section 3-1 Duplex CPU Units contents are different, write processing to the Memory Cards may not be completely correctly. • Duplex operation is possible for EM file memory. Operational • Interrupts (including scheduled interrupt tasks, external interrupt tasks, Restrictions and power OFF interrupt tasks) cannot be used. •...
Page 171 Section 3-1 Duplex CPU Units • Execution of the following instructions (called “synchronized instructions”) is synchronized between the two CPU Units, so their instruction execution times are longer than for the CS1-H. (For details on processing time, refer to 9-5 Instruction Execution Times and Number of Steps. Synchronized instructions: IORF(097) (I/O REFRESH), DLINK(226) (CPU BUS UNIT I/O REFRESH), IORD(222) (INTELLIGENT I/O READ), IOWR(223) (INTEL-...
Page 172 Section 3-1 Duplex CPU Units Note 1. When a duplex verification error or duplex bus error occurs when the pow- er is turned ON, the CPU Unit goes into “CPU standby” status. 2. The cause of the “CPU standby” is stored in A322 in the Auxiliary Area. Conditions for Mode Switching in a Duplex System (Reference) Condition System...
Page 173 Section 3-1 Duplex CPU Units 3-1-8 Duplex CPU Compatible Setting The Duplex CPU Compatible Setting on the CS1D-CPU67HA enables the CPU Unit duplexity with the CS1D-CPU65H or CS1D-CPU67H. ■ °Method of enabling the Duplex CPU Compatible Setting Make the changes with the DIP switches (Pin 4, 5, and 6) on the front panel of the CS1D-CPU67HA.
Page 174 Section 3-1 Duplex CPU Units ■ °Replacement Method When performing Duplex with CS1D-CPU65H or CPU67H, refer to 11-3 Replacing a CPU Unit for details on the procedure of replacing with the CS1D-CPU67HA. ■ Change the Setting To change the Duplex CPU Compatible Setting, perform Memory All Clear using the Programming Device and then turn OFF the power supply to the CPU Unit.
Page 175 Section 3-1 Duplex CPU Units ■ List of related AR Address Name Description Setting Held/Cleared Timing Related Words Bits When When area setting changing power is to RUN turned mode A317 A31707 CPU Unit 1 (ON) when the Matched Cleared Cleared When A316...
Page 176 Section 3-2 Duplex Power Supply Units Duplex Power Supply Units A CS1D Duplex System can be configured with Duplex Power Supply Units to prevent the system from going down due to a Power Supply Unit error. Be sure to use CS1D-PA/PD@@@ Power Supply Units. No other Power Sup- ply Units can be used in a CS1D System.
Page 177 Section 3-3 Duplex Communications Units Two Communications Units are connected to the same communications line. One of them operates in Active Mode, the other one in Standby Mode. The same unit number and node address are set for both of the Units. The active (ACT) Communications Unit performs communications with the nodes on the network.
Page 178 Section 3-3 Duplex Communications Units Normal Operation The primary Communications Unit communicates with other nodes through the primary network. Primary network Secondary network Operation for Errors The secondary Communications Unit communicates with nodes If the primary Communications with which the primary Unit fails, the secondary Communications Unit cannot Communications Unit performs...
Page 179 Section 3-4 Duplex Connecting Cables Number of pairs of Communications Allowable number of Units using primary/secondary other CPU Bus Units. communications Communication Unit settings must be made for both the primary and second- ary Communications Unit. Refer to the operation manual for the Communica- tions Units for information on the settings that are required.
Page 180 Section 3-4 Duplex Connecting Cables Note If there are problems in both Connecting Cables, the system will stop. Unit CPU Rack The system will stop if there are problems in both Connecting Cables. Expansion Rack Units Expansion Rack...
Page 181 SECTION 4 Operating Procedures This section outlines the steps required to assemble and operate a CS1D PLC system. Introduction ........... Basic Procedures .
Page 182 Section 4-1 Introduction Introduction The following procedure outlines the recommended steps to follow when pre- paring a Duplex CPU or Single CPU System for operation. 1. Installation 1,2,3... Set the DIP switches on the front of each Unit as required. Mount the two CPU Units (see note), Duplex Unit (see note), two Power Supply Units, and other Units to the Backplane.
Page 183 Section 4-1 Introduction Refer to SECTION 6 PLC Setup for details. 7. Registering the I/O Tables Check the Units to verify that they are installed in the right slots. With the PLC in PROGRAM mode, register the I/O tables from the Programming Device (CX-Programmer or Programming Console).
Page 184 Section 4-1 Introduction 13. Running the Program Switch the PLC to RUN mode to run the program.
Page 185 Section 4-2 Basic Procedures Basic Procedures 1. Installation 1. As necessary, set the DIP switches on the fronts of the Units. 1,2,3... 2. Mount the two Duplex CPU Units, Duplex Unit, two Power Supply Units, and other Units to the Backplane. Use the same model of CPU Unit for both CPU Units.
Page 186 Section 4-2 Basic Procedures 3. Initial Hardware Settings Settings for Duplex CPU Systems 1. Duplex Unit Settings 1,2,3... DPL02D DPL STATUS ACTIVE Left CPU USE/NO USE Switch CPU STATUS When mounting or removing the ACTIVE CPU STATUS left CPU Unit, set this switch to LEFT CPU NO USE to turn OFF the power supply to the CPU Unit.
Page 187 Section 4-2 Basic Procedures d) Set the communications switch on the Duplex Unit. When connecting a Programming Console to the peripheral port, set the PRPHL switch to OFF. When connecting the CX-Programmer to the RS-232C port, set the COMM switch to ON. Note When connecting anything other than a Programming Console to the peripheral port, set the PRPHL switch to ON.
Page 188 Section 4-2 Basic Procedures • Turn OFF pin 4 on the DIP switch when connecting a Programming Device to the peripheral port. Turn pin 4 ON when connecting any other device. • Turn ON pin 5 on the DIP switch when connected a Programming Device other than a Programming Console to the RS-232C port.
Page 189 Section 4-2 Basic Procedures 6. PLC Setup Settings These settings are the CPU Unit’s software configuration. Refer to SECTION 6 PLC Setup for details on the settings. Note The PLC Setup settings are arranged by word addresses when a Program- ming Console is used to make PLC Setup settings.
Page 190 Section 4-2 Basic Procedures Using a Programming Console PRO27 PROGRAMMING CONSOLE OGRAMMING CONSOLE MONITOR PROGRAM Procedure 000000 CT00 PC SETUP VRFY 0:MODE1:PC SETUP PC SETUP +000 0000 Specifying a word address in the PLC Setup. (Example: 209) PC SETUP +209 PC SETUP ↓...
Page 191 Section 4-2 Basic Procedures Note The I/O tables, user program, and PLC Setup data in CS1D CPU Units is backed up in the built-in flash memory. The BKUP indicator will light on the front of the CPU Unit when the backup operation is in progress. Do not turn OFF the power supply to the CPU Unit when the BKUP indicator is lit.
Page 192 Section 4-2 Basic Procedures Using the CX-Programmer Offline Use the following procedure to create the I/O tables offline with the CX-Pro- grammer and later transfer the I/O tables to the CPU Unit. 1. Set the device type in the CX-Programmer as shown in the following table. 1,2,3...
Page 193 Section 4-2 Basic Procedures 000000 I/O TBL WRIT ???? 000000 I/O TBL WRIT ???? Password (9713) 000000CPU BU ST? WRITE 0:CLR 1:KEEP 000000 I/O TBL Specify holding or clearing WRIT OK CPU Bus Unit information. 000000 CT00 Note If an error occurs when creating the I/O tales, detailed I/O table error informa- tion is stored in A261 whenever the I/O tables.
Page 194 Section 4-2 Basic Procedures 2. With Duplex CPU Systems, confirm that the DPL STATUS indicator on the Duplex Unit flashes green after the data has been transferred to the active CPU Unit. This indicates that the duplex system is being initialized, e.g., the data that was transferred to the active CPU Unit is also being trans- ferred to the standby CPU Unit.
Page 195 Section 4-2 Basic Procedures Retained memor y Operating mode changed IOM Hold Bit Status at Startup When the IOM Hold Bit has been turned ON and the PLC Setup is set to pro- tect the status of the IOM Hold Bit at startup (PLC Setup address 80 bit 15 turned ON), the contents of I/O memory that would otherwise be cleared will be retained when the PLC is turned ON.
Page 196 Section 4-2 Basic Procedures Trial Operation Use the Programming Console or Programming Device (CX-Programmer) to switch the CPU Unit to MONITOR mode. Using a Programming Console Turn the Mode Switch to MONITOR for the trial operation. (Turn the switch to RUN for full-scale PLC operation.) Trial Operation MONITOR...
Page 197 Section 4-2 Basic Procedures Differentiation Monitor The differentiation monitor operation can be used to monitor the up or down differentiation of particular bits. When a Programming Console is being used, monitor the bit with Bit/Word Monitor. Press the SHIFT+Up Arrow Keys to specify up differentiation or press the SHIFT+Down Arrow Keys to specify down differentiation.
Page 198 Section 4-2 Basic Procedures...
Page 199 SECTION 5 Installation and Wiring This section describes how to install a PLC System, including mounting the various Units and wiring the System. Be sure to follow the instructions carefully. Improper installation can cause the PLC to malfunction, resulting in very dangerous situations.
Page 200 Section 5-1 Fail-safe Circuits Fail-safe Circuits Be sure to set up safety circuits outside of the PLC to prevent dangerous con- ditions in the event of errors in the PLC or external power supply. Order of Supplying Power If the PLC’s power supply is turned ON after the controlled system’s power supply, outputs in Units such as DC Output Units may malfunction momen- tarily.
Page 201 Section 5-2 Installation MCB1 Power supply MCB2 Controlled system Transformer or noise filter CS1D PLC in Duplex Mode Twisted-pair wires DC voltage input/output regulator − PLC RUN output Surge suppressor Note Do not latch the RUN output and use it in a circuit to stop a controlled object. Chattering of the relay contacts used in the output may cause incorrect opera- tion.
Page 202 Section 5-2 Installation • Locations subject to ambient temperatures lower than 0°C or higher than 55°C. • Locations subject to drastic temperature changes or condensation. • Locations subject to ambient humidity lower than 10% or higher than 90%. • Locations subject to corrosive or flammable gases. •...
Page 203 Section 5-2 Installation Improving Noise Resistance • Do not mount the PLC in a control panel containing high-voltage equip- ment. • Install the PLC at least 200 mm (6.5 feet) from power lines. Power lines 200 mm min. 200 mm min. •...
Page 204 Section 5-2 Installation 5-2-2 Installation in a Control Panel • A typical installation is a CPU Rack mounted above an Expansion Rack on a mounting plate in the control panel. • The spacing between the CPU Rack and Expansion Rack (or between two Expansion Racks) should be sufficient to allow space for a wiring duct, wiring, air circulation, and replacement of Units in the Racks.
Page 205 Section 5-2 Installation • The Backplanes are mounted to the plate(s) with four M4 screws each. • Whenever possible, route I/O wiring through wiring ducts or raceways. Install the duct so that it is easy to fish wire from the I/O Units through the duct.
Page 206 Section 5-2 Installation Input duct Output duct Power duct 200 mm min. CPU Rack Breakers, fuses Expansion Rack Power equipment such as transformers and magnetic relays Fuses, relays, timers, etc. (NOT heat-generating equip- Terminal Terminal blocks for ment, power equipment, etc.) blocks or PLC power equipment 5-2-3...
Page 207 Section 5-2 Installation 5-2-4 Backplane Mounting Dimensions 491±0.3 Four, M4 118±0.3 131.9 CS1D-BC052/BC082S CPU Backplane 505.1 84 to 491±0.3 CS1D-BI092 Expansion Backplane 118±0.3 131.9 505.1 Four, M4 5-2-5 Mounting Units to the Backplane The following table shows the mounting method. Installation method Removal method Hook the top of the Unit into the...
Page 208 Section 5-2 Installation Duct 20 mm min. Unit Backplane 20 mm min. Duct Phillips screwdriver 4. To remove a Unit, use a phillips-head screwdriver to loosen the screw at the bottom of the Unit, rotate the Unit upward, and remove it. 5-2-6 I/O Connecting Cables I/O Connecting Cables are used to connect the CPU Rack and Expansion...
Page 209 Section 5-2 Installation Note Not all CS1W-CN313/CN713 Cables can be used. Refer to CS-series Con- necting Cables on page 45 for details. Long-distance Expansion Rack I/O Connecting Cables Model number Cable length CV500-CN312 0.3 m CV500-CN612 0.6 m CV500-CN122 CV500-CN222 CV500-CN322 CV500-CN522 CV500-CN132...
Page 210 Section 5-2 Installation Example 2: Long-distance Expansion Rack I/O Connecting Cables CPU Rack IC102 TER ERR LEFT CPU RIGHT CPU DPL SW INIT. DUPLEX Long-distance Expansion Rack IC102 IC102 TER ERR Long- TER ERR Total cable length: distance Expansion 50 m max. Rack Total cable IC102...
Page 211 Section 5-2 Installation CPU Rack or Expansion Rack Expansion Rack Simple locking connectors The connectors can be inserted only one way; they cannot be inserted upside down. Be sure that the connectors fit properly as they are inserted. The connecting port for each CS-series I/O Connecting Cable depends on the system configuration and the Rack being connected, as shown in the follow- ing diagrams.
Page 212 Section 5-2 Installation IC102 TER ERR CPU Rack CV-series Long-distance I/O Connecting Cables I/O Control Unit Long-distance Long-distance Expansion Rack IC1 02 TER ERR Expansion Rack IC1 02 TER ERR Series B I/O Interface Unit Series A I/O Interface Unit The connecting port for each CV-series Long-distance I/O Connecting Cable depends on the system configuration and the Rack being connected, as shown in the following diagrams.
Page 213 Section 5-2 Installation 4. A 75-mm hole will be required if the I/O Connecting Cable must pass through a hole when connecting a Long-distance Expansion Rack and a 63-mm hole will be required for Cables connecting other Racks. 5. I/O Connecting Cables cannot be cut or rejoined. Be sure to use I/O Con- necting Cables of the proper length, particularly when wiring inside panels or wiring ducts.
Page 214 Section 5-2 Installation into the CS1D-CPU@@PProcess-control CPU Units. The CS1D-CPU@@P Process-control CPU Units are sold as a single product and the Board cannot be removed. Note 1. Duplex operation that includes Inner Boards can be used with CPU Units from lot number 030422 onwards (i.e., CPU Units manufactured from April 22, 2003 onwards).
Page 215 Section 5-3 Power Supply Wiring COMM 1 COMM 2 Power Supply Wiring The power supply systems are divided as follows: Power section, control cir- cuits, CS1D Racks, and DC I/O. Wire each of these separately. When using a duplex CS1D System, use a separate power source for each of the two Duplex Power Supply Units.
Page 216 Section 5-3 Power Supply Wiring Wiring Examples: Expansion Racks AC power supply 1 (A1) CS1D CPU Rack PA207R PA207R POWER POWER L2/N L2/N AC power supply 2 (A2) AC100V-120V/ AC100V-120V/ AC2100-240V/ AC2100-240V/ INPUT INPUT 100-120 100-120 CLOSE CLOSE 200-240 200-240 OPEN OPEN OUTPUT...
Page 217 Section 5-4 Wiring Methods Wiring Methods 5-4-1 Wiring Power Supply Units AC Power Supply Models Note When 220 V AC power (200 to 240 V AC) is being supplied, be sure to remove the jumper bar that shorts the voltage selector terminals. The Unit will be damaged if 220 V AC is supplied with the jumper bar connected.
Page 218 Section 5-4 Wiring Methods AC Power Source • Supply 100 to 120 V AC or 200 to 240 V AC. • Keep voltage fluctuations within the specified range: Supply voltage Allowable voltage fluctuations 100 to 120 V AC 85 to 132 V AC 200 to 240 V AC 170 to 264 V AC •...
Page 219 Section 5-4 Wiring Methods Wiring Example: RUN Output PA207R PA207R POWER POWER L2/N L2/N AC100V-120V/ AC100V-120V/ AC2100-240V/ AC2100-240V/ INPUT INPUT 100-120 100-120 CLOSE CLOSE 200-240 200-240 OPEN OPEN Power supply OUT450V OUTPUT Control circuits DC24V AC240V 2A RESISTIVE DC24V 2A RESISTIVE in controlled system Emergency stop circuit...
Page 220 Section 5-4 Wiring Methods !Caution Tighten the AC power supply terminal block screws to the torque of 0.8 N⋅m. Loose screws may result in short-circuit, malfunction, or fire. Note 1. Be sure to check the setting of the voltage selector before supplying pow- 2.
Page 221 Section 5-4 Wiring Methods Recommended crimp terminals 7 mm max. 7 mm max. Manufacturer Models Shape Applicable wire range (stranded wire) JST Mfg. V1.25-YS3A Y-shaped termi- 0.25 to 1.65 mm (AWG nal with sleeve 22 to 16) V1.25-M3(RAV1.25- Round terminal 3.5) with sleeve V2-YS3A...
Page 222 Section 5-4 Wiring Methods Other equipment CS1D PLC Ground Ground (100 Ω or less) (100 Ω or less) Other equipment CS1D PLC Ground Ground (100 Ω or less) (100 Ω or less) • Do not share the PLC’s ground with other equipment or ground the PLC to the metal structure of a building.
Page 223 Section 5-4 Wiring Methods Recommended Wiring IC101 I102 1:1 Isolating 1:1 Isolating transformer transformer Match to the I/O Expansion Rack CPU Rack Expansion Cable. I/O Expansion Cable Control panel Control panel Wiring Susceptible to Noise IC101 I102 Noise source Expansion Rack CPU Rack I/O Expansion Cable Grounded to building...
Page 224 Section 5-4 Wiring Methods Wiring Terminal screws M3.5 self-rising screws Recommended wire size AWG 14 min. (2 mm min.) Recommended tightening 0.8 N·m torque Recommended crimp terminals 7 mm max. 7 mm max. Manufacturer Models Shape Applicable wire range (stranded wire) JST Mfg.
Page 225 Section 5-4 Wiring Methods 2. Do not connect bare stranded wires directly to terminals. • Confirm that the Units have been mounted properly. • Cover the Unit while wiring to prevent wire clippings from entering the Unit. If there is a dustproof label on the top of the Unit, do not remote it before you wire the Unit.
Page 226 This section describes wiring CS-series Basic I/O Units with Connectors (32-, 64-, and 96-point Units). The user can combine a special connector with cable or use a preassembled OMRON cable to connect a High-density I/O Unit to a terminal block or I/O Terminal.
Page 227 Wiring Methods CS-series 96-point I/O The following connectors are recommended for attachment to CS-series 96- Units point I/O Units. Connection Pins OMRON set Fujitsu/Otax parts Solder-type CS1W-CE561 Socket: Fujitsu FCN-361J056-AU (included with Unit) Connector bar: Fujitsu FCN-360C056-J3 Otax N360C056J3 Crimp-type...
Page 228 Section 5-4 Wiring Methods Solder-type connector included with Unit. Heat-shrink tubing Wire (0.2 to 0.13 mm Note Double-check to make sure that the Output Unit’s power supply leads haven’t been reversed. If the leads are reversed, the Unit’s internal fuse will blow and the Unit will not operate.
Page 229 Connector lock screws Tighten the connector-attaching screws to a torque of 0.2 N⋅m. The following examples show applications for preassembled OMRON Cables. Contact your OMRON dealer for more details. Connecting to a Terminal Two sets of the following Cables and Conversion Units are required.
Page 230 Section 5-4 Wiring Methods CS1 Basic I/O Unit CS1 Basic I/O Unit CS1W-ID291 (96 input points) CS1W-ID291 (96 input points) CS1W-OD291 (96 output points) CS1W-OD291 (96 output points) CS1W-OD292 (96 output points) CS1W-OD292 (96 output points) CS1W-MD291 (48 inputs, 48 outputs) CS1W-MD291 (48 inputs, 48 outputs) CS1W-MD292 (48 inputs, 48 outputs) CS1W-MD292 (48 inputs, 48 outputs)
Page 231 Section 5-4 Wiring Methods Connecting to a Relay Two sets of the following Cables and Relay Terminals are required. Terminal CS1 Basic I/O Unit CS1 Basic I/O Unit CS1W-ID231 CS1W-ID291 (96 input points) CS1W-ID261 CS1W-OD291 (96 output points) CS1W-MD261 (inputs) CS1W-OD292 (96 output points) CS1W-OD231 CS1W-MD291 (48 inputs, 48 outputs)
Page 232 Section 5-4 Wiring Methods • NPN open-collector output Sensor Power Supply Output DC Input Unit 7 mA • NPN current output Current regulator Output DC Input Unit 7 mA Sensor Power Supply • PNP current output Sensor Power Supply Output AC/DC Input Unit 7 mA •...
Page 233 Section 5-4 Wiring Methods AC Input Units • Contact output AC Input Unit • AC switching Proximity switch AC Input Unit main circuit Note When using a reed switch as the input contact for an AC Input Unit, use a switch with an allowable current of 1 A or greater.
Page 234 Example In this example, the sensor’s power supply voltage is used as the input to CIO 000000 and a 100-ms timer delay (the time required for an OMRON Proximity Sensor to stabilize) is created in the program. After the Comple- tion Flag for the timer turns ON, the sensor input on CIO 000001 will cause output bit CIO 000100 to turn ON.
Page 235 Section 5-4 Wiring Methods Use the following formula to determine the resistance and rating for the bleeder resistor. : ON voltage of the load (V) R < I: Leakage current (mA) R: Bleeder resistance (KΩ) Output Surge Current When connecting a transistor or triac output to an output device having a high surge current (such as an incandescent lamp), steps must be taken to avoid damage to the transistor or triac.
Page 236 Section 5-4 Wiring Methods Diode Relay output DC input or triac output Surge suppressor Relay output or transistor output Diode Note Use surge suppressors and diodes with the following specifications. 50 Ω Resistance: 0.47 µF Capacitor: Voltage: 200 V Breakdown voltage: 3 times load voltage min.
Page 237 SECTION 6 PLC Setup This section describes the settings in the PLC Setup and how they are used to control CPU Unit operation. Overview of PLC Setup ......... 6-1-1 Duplex System Settings .
Page 238 Section 6-1 Overview of PLC Setup Overview of PLC Setup The PLC Setup contains basic CPU Unit software settings that the user can change to customize PLC operation. These settings can be changed from a Programming Console or other Programming Device. The various settings for the CPU Unit are made in the PLC Setup.
Page 239 Section 6-1 Overview of PLC Setup 5. This function is supported only by Duplex CPU Units with Unit Ver. 1.3 or later. 6. Can be set in CX-Programmer Ver. 8.0 or later. The settings will be added to CX-Programmer version 7.0 when its functions are expanded by auto- update.
Page 240 Section 6-1 Overview of PLC Setup Cases when settings must be changed Setting(s) to be changed The peripheral port will not be used with the Programming Console or CX- Peripheral Port Settings Programmer (peripheral bus) communications speed auto-detection and will not used the default host link communications settings such as 9,600 bps.
Page 241 Section 6-2 Specific PLC Setup Settings 6-1-3 Tab Pages for Duplex Settings in the PLC Setup The location of duplex settings and the tab labels in CX-Programmer are dif- ferent between version 3.@ and version 4.0 or higher. Settings CX-Programmer Ver. 3.@ CX-Programmer Ver.
Page 242 Section 6-2 Specific PLC Setup Settings IOM Hold Bit Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0: Cleared This setting determines whether or not the A50012 (IOM At startup 1: Retained status of the IOM Hold Bit (A50012) is Hold Bit) retained at startup.
Page 243 Section 6-2 Specific PLC Setup Settings Enable Setting in Word 83 for Inner Boards (Single CPU Systems Only) Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0: Wait for Boards. To start the CPU Unit in MONITOR or PRO- At startup GRAM mode even if there is one or more of 1: Don’t wait.
Page 244 Section 6-2 Specific PLC Setup Settings Detect Interrupt Task Error (Single CPU Systems Only) Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0: Detect This setting determines whether interrupt A40213 Takes effect task errors are detected.
Page 245 Section 6-2 Specific PLC Setup Settings Memory Allocation Settings EM File Setting Enabled Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0: None This setting determines whether part of the After initial- EM Area will be used for file memory.
Page 246 (internal logical execution. ports) Note This setting cannot be used with Duplex CPU Systems. FB Communications Instruction Settings (CS1D-CPU@@HA/SA only) The following PLC Setup settings are used only when using the OMRON FB Library. Number of Resends ■ Programming Settings...
Page 247 OMRON FB Library to execute FINS messages or DeviceNet explicit messages communications. The values set in this PLC Setup for OMRON FB Library will be automatically stored in the related Auxiliary Area words A580 to A582 and used by the function blocks from the OMRON FB Library.
Page 248 Section 6-2 Specific PLC Setup Settings Cycle Time (Minimum Cycle Time Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0 to 15 0001 to 7D00 hex: 1 Set to 0001 to 7D00 to specify a minimum At the start of to 32,000 ms cycle time (in parallel processing mode, the...
Page 249 Section 6-2 Specific PLC Setup Settings Power OFF Interrupt Disable (Single CPU Systems Only) Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0: Disabled When this setting is set to 1, the power OFF Takes effect 1: Enabled interrupt task will be executed when power...
Page 250 Section 6-2 Specific PLC Setup Settings 6-2-5 Unit Settings Tab Page Basic I/O Unit Input (Rack) Response Times Item Address in Settings Function Related New set- Programming flags and ting’s Console words effective- ness Word Bit(s) Rack 0, Slot 0 0 to 7 00 hex: 8 ms Sets the input response time...
Page 251 Section 6-2 Specific PLC Setup Settings 6-2-6 Host Link Port Tab Page With a Duplex CPU System, these settings are valid when the COMM pin on the DIP switch on the Duplex Unit is turned OFF. With a Single CPU System, these settings are valid when the pin 5 on the DIP switch on the CPU Unit is turned OFF.
Page 252 Section 6-2 Specific PLC Setup Settings Format: Data Bits Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 7 bits These settings are valid only when the com- A61902 Takes effect 8 bits munications mode is set to host link or no- (RS-232C the next...
Page 253 Section 6-2 Specific PLC Setup Settings Unit Number (for CPU Unit in Host Link Mode) Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0 to 7 00 to 1F hex: This setting determines the CPU Unit’s unit A61902 Takes effect (0 to 31)
Page 254 Section 6-2 Specific PLC Setup Settings Peripheral Bus Settings Communications Settings Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0: Default (stan- *The default settings are for a baud rate of A61902 Takes effect dard)*...
Page 255 Section 6-2 Specific PLC Setup Settings Start Code/End Code Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 8 to 15 00 to FF hex Start code: Set this start code only when the A61902 Takes effect start code is enabled (1) in bits 12 of 165.
Page 256 Section 6-2 Specific PLC Setup Settings Host Link Settings Communications Settings Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0: Default (stan- *The default settings are for 1 start bit, 7 A61901 Takes effect dard)*...
Page 257 Section 6-2 Specific PLC Setup Settings Format: Parity Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0 and 1 00: Even These setting is valid only when the commu- A61901 Takes effect 01: Odd nications mode is set to Host link.
Page 258 Section 6-2 Specific PLC Setup Settings Baud Rate (bps) Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0 to 7 00 hex: Standard * Set to 115,200 when setting this value A61901 Takes effect 0A hex: High-speed...
Page 259 Section 6-2 Specific PLC Setup Settings Baud Rate (bps) Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0 to 7 00 hex: 9,600 The following settings are valid for the A61901 Takes effect 06 hex: 9,600 peripheral bus mode: 00 and 06 to 0A hex.
Page 260 Section 6-2 Specific PLC Setup Settings Set Time to All Events (Fixed Peripheral Servicing Time) Enable Fixed Servicing Time Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0: Default* Set to 1 to enable the fixed peripheral ser- Takes effect 1: Bits 0 to 7 vicing time in bits 0 to 7.
Page 261 Section 6-2 Specific PLC Setup Settings Target Units (Units/Boards for Priority Servicing Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 08 to 15 Up to five Units and/or Boards can be speci- Takes effect 10 to 1F fied for priority servicing.
Page 262 Section 6-2 Specific PLC Setup Settings Nodes Excluded from Write Protection (Protection Releasing Addresses) Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) Set the nodes and networks from which FINS write operations will be enabled. The total number of nodes set to be excluded from write protection will be automatically set.
Page 263 Section 6-2 Specific PLC Setup Settings Active-Standby Settings (Check Boxes for Communications Units 0 to 15) Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0 to 15 0: Disable duplex These settings (individual bits) enable or At startup settings for Commu- disable duplex settings for individual Com-...
Page 264 Section 6-2 Specific PLC Setup Settings 6-2-11 CPU Duplex Tab Page Duplex Settings Operation Settings, Run under Duplex Initial Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0: Do not run during This setting determines where operation is At startup initialization (start...
Page 265 Section 6-2 Specific PLC Setup Settings When an operation switching error occurs in the Active CPU Unit, the Standby CPU Unit will become the Active CPU Unit and start operating. Address in Settings Function Related New set- Programming flags and ting’s effec- Console words...
Page 266 Section 6-2 Specific PLC Setup Settings Memory Card Duplex Settings Enable Memory Card Duplex Setting Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0: Disable duplex When data is written to Memory Cards, this Every cycle operation for Mem- setting determines whether it is written to...
Page 267 Section 6-2 Specific PLC Setup Settings CPU Unit Duplex Transfer Settings EM Division Transmission, Division Size Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0 to 7 00 hex: 4,906 words This setting determines the number of At startup words to transfer each cycle in units of 512...
Page 268 Section 6-2 Specific PLC Setup Settings Transfer Variable Area of Inner Board Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 0: Transfer Inner This setting determines if the variable area At startup Board Variable Area is transferred between Duplex Inner Boards.
Page 269 Section 6-2 Specific PLC Setup Settings Enabling Unit Removal/Addition of Units without a Programming Device Address in Settings Function Related New set- Programming flags and ting’s effec- Console words tiveness Word Bit(s) 8 to 15 Value other than AA This setting determines if Units can be A09911 Every cycle hex: Online replace-...
Page 270 Section 6-2 Specific PLC Setup Settings Turning ON Error Unit Number Flag when Removing a Special I/O Unit Error or CPU Bus Unit (When removing any special unit, turn ON the error unit flag in the CX-Programmer) Address in Settings Function Related New set-...
Page 271 SECTION 7 I/O Allocations This section describes I/O allocations to Basic I/O Units, Special I/O Units, and CPU Bus Units, and data exchange with CPU Bus Units. I/O Allocations ..........7-1-1 Unit Types.
Page 272 Section 7-1 I/O Allocations I/O Allocations In CS1D PLCs, memory must be allocated to the Units mounted in the PLC. I/O tables containing the models and locations of all Units and the allocations made to each must be created and these I/O tables must be registered in the CPU Unit.
Page 273 Section 7-1 I/O Allocations The following table shows the maximum number of Units that can be mounted in each type of system. System Max. number of Units Duplex CPU, Dual I/O Duplex Connecting Cables Expansion System Single Connecting Cable Duplex CPU, Single I/O Expansion System Single CPU System Special I/O Units Special I/O Units...
Page 274 Section 7-1 I/O Allocations Creating I/O Tables Based on Mounted Units Connect a Programming Console or the CX-Programmer to a CPU Unit in a PLC with all the Units mounted and create the I/O tables. In the I/O table cre- ation operation, information on the Unit models and mounting locations are registered in the parameter area of the CPU Unit as the registered I/O tables for all Units mounted to the basic PLC system.
Page 275 Section 7-1 I/O Allocations I/O Table Creation with a Programming Console Use the following procedure to register the I/O table with a Programming Con- sole. 000000 CT00 000000 I/O TBL ? SHIFT Note If the Rack first words have already been set from the CX-Program- mer, “Rack 1st Word En”...
Page 276 Section 7-1 I/O Allocations be mounted are set for each Rack, the CX-Programmer will automatically allo- cate words according to Rack and slot positions starting from CIO 0000. 1. Double-click IO Table in the project tree in the main window. The I/O Table 1,2,3...
Page 277 Section 7-1 I/O Allocations Setting the First Words for Specific Slots A word is set for slot 00 on the CPU Rack for group 00. A word is set for slot 02 on the CPU Rack for group 01. Rack 0 Rack 1 A word is set for slot 02 on Rack 1 for group 02.
Page 278 Section 7-2 I/O Allocation Methods I/O Allocation Methods 7-2-1 I/O Allocations to Basic I/O Units Basic I/O Units include the following Units: • CS-series Basic I/O Units These Units are allocated words in the I/O Area (CIO 0000 to CIO 0319) and can be mounted to the CPU Rack, and CS-series Expansion Racks.
Page 279 Section 7-2 I/O Allocation Methods Example 2 The following example shows the I/O allocations to 5 Basic I/O Units in the CPU Rack. Two slots are filled with Dummy Units to reserve I/O words for those slots. Example for Single CPU System, CPU Rack served served CIO CIO CIO CIO CIO CIO...
Page 280 Section 7-2 I/O Allocation Methods Example for Single CPU System The following example shows the I/O allocation to Basic I/O Units in the CPU Rack and two CS-series Expansion Racks. Single CPU System served CPU Rack CIO CIO CIO CIO CIO CIO CIO 0000 0001...
Page 281 Section 7-2 I/O Allocation Methods I/O Table Editing Operation Double-click IO Table in the project tree in the main window. The I/O Table Window will be displayed. • CX-Programmer Ver. 5.0 or Earlier Right-click the slot for which a word is to be reserved and select the Dummy item from under the Basic I/O Unit with the correct number of I/O points.
Page 282 Section 7-2 I/O Allocation Methods The following Select Unit Dialog Box will be displayed. Click the expansion button (+) to the left of Basic I/O, select one of the Dummy Units (CS_Dummy_016/032/048/064/096/128), and click the OK Button. Note Do not execute the I/O table creation operation after completing the above editing operation.
Page 283 Section 7-2 I/O Allocation Methods 7-2-2 I/O Allocations to Special I/O Units Special I/O Units include the following Units: • CS-series Special I/O Units Each of these Units is allocated ten words in the Special I/O Unit Area (CIO 2000 to CIO 2959) according the unit number set on the Unit. Special I/O Units can be mounted to the CPU Rack, CS-series Expansion Racks (see note).
Page 284 Section 7-3 Allocating First Words to Racks 7-2-3 I/O Allocations to CPU Bus Units Each CPU Bus Unit is allocated 25 words in the CPU Bus Unit Area (CIO 1500 to CIO 1899) according the unit number set on the Unit. CPU Bus Units can be mounted to the CPU Rack or CS-series Expansion Racks.
Page 285 Section 7-3 Allocating First Words to Racks Word Allocations For Racks in which the first word address has been set, words are allocated to Units in the order that the Units are mounted (from left to right) beginning with the specified first word. Words are not allocated to empty slots. For Racks in which the first word address has not been set, words are allo- cated in rack-number order (lowest to highest) continuing from the last word allocated to the previous rack and starting with CIO 0000 on the first Rack for...
Page 286 Section 7-3 Allocating First Words to Racks the specified first words. The non-shaded Racks are allocated in order from left to right and in order of Rack starting from CIO 0000. Setting First Rack Words from the CX-Programmer The first word allocated on each Rack can be set from the CX-Programmer. These settings are not possible from a Programming Console.
Page 287 Section 7-4 Allocating First Words to Slots (Single CPU Systems Only) 000000I/O TBL ? SHIFT Rack 1st Word En If nothing is displayed, then a first word has not been set. 2. Press the CHG Key, enter the password (9713), and then press the WRITE Key to continue creating the I/O tables, or press the CLR Key to cancel the operation and return to the initial display.
Page 288 Section 7-4 Allocating First Words to Slots (Single CPU Systems Only) Example: Setting the First Words for Racks In this example, a first slot word has been set in the middle of each Rack. For simplicity, only 16-bit Units have been used. Group 00 set for first Group 01 set for first slot word of CIO 0000...
Page 289 Section 7-4 Allocating First Words to Slots (Single CPU Systems Only) 2. Select the Slot Start Addresses Settings Option and click the OK Button. 3. In the dialog box that will appear, set the first word for slot 00 on the CPU Rack.
Page 290 Section 7-5 Detailed Information on I/O Table Creation Errors Precautions in Setting First Slot Words When the I/O tables are edited, the CX-Programmer checks for any duplica- tions in word allocations caused by first word settings. It is conceivable, how- ever, that duplications in word allocations could occur after the I/O tables have been registered, e.g., as the result of replacing a 1-word Unit with a 2- word Unit.
Page 291 Section 7-6 Data Exchange with CPU Bus Units Data Exchange with CPU Bus Units This section describes how data can be exchanged between Special I/O Units or CS-series CPU Bus Units, and the CPU Unit. 7-6-1 Special I/O Units Special I/O Units include C200H Special I/O Units and CS-series Special I/O Units.
Page 292 Section 7-6 Data Exchange with CPU Bus Units Special I/O Unit CPU Unit Transferred when power is turned DM Area for Special I/O Units on or the Unit is restarted. 100 words/Unit Transferred each cycle and when necessary. FINS Commands The CMND(490) instruction can be added to the ladder program to issue a FINS command to the Special I/O Unit.
Page 293 Section 7-6 Data Exchange with CPU Bus Units can be extended by setting a minimum cycle time in the PLC Setup or cyclic I/O refreshing with the Special I/O Unit can be disabled. When cyclic refresh- ing has been disabled, the Special I/O Unit’s data can be refreshed during program execution with IORF(097).
Page 294 Section 7-6 Data Exchange with CPU Bus Units Some models transfer data in both directions, from the DM Area to the Unit and from the Unit to the DM Area. See the Unit’s Operation Manual for details on data transfers. These 100 words are generally used to hold initial settings for the CPU Bus Unit.
Page 295 Section 7-7 Online Addition of Units and Backplanes Online Addition of Units and Backplanes This function allows previously unregistered Units to be added and controlled during operation. Both Units and Expansion Racks can be added during oper- ation. Note 1. A Duplex CPU Unit with unit version 1.3 or later is required to add Units online.
Page 296 Section 7-7 Online Addition of Units and Backplanes • Creating the I/O Table by setting the Starting Word for each Rack Units cannot be added to the shaded slots because the word Starting rack word addresses would be duplicated. is set to CIO 20. Units can be added in these slots with word addresses CIO 13 to CIO 19.
Page 297 Section 7-7 Online Addition of Units and Backplanes A Unit cannot be added to the shaded slots because the word address would be duplicated. When the Connecting Cables are duplexed, all of the cables must be connected properly before adding a Rack. Units can be added in these slots starting from CIO 9.
Page 298 Section 7-7 Online Addition of Units and Backplanes Online Addition of Units 1. Mount the additional Unit in an empty slot. 1,2,3... Add a CS1W-AD0041 (unit number 0) in Rack 1 slot 6. Note: Always tighten the new Unit's screws and verify that it is secure.
Page 299 Section 7-7 Online Addition of Units and Backplanes Select the Select Unit Window from Rack 01, Slot 06 and add a CS1W-AD041. 6. Select Options - Online Add Unit - reflection. The Unit addition will be completed if the Unit selected in the CX-Programmer matches the Unit that was actually added.
Page 300 Section 7-7 Online Addition of Units and Backplanes When the Connecting Cables are duplexed, all of the cables must be connected properly before adding a Rack. Verify that the Becomes slot 2. END RACK indicator is lit. Note: When adding a Unit and Backplane, always tighten the screws and verify that the Unit is secure.
Page 301 SECTION 8 Memory Areas This section describes the structure and functions of the I/O Memory Areas and Parameter Areas. Introduction ........... I/O Memory Areas .
Page 302 Section 8-1 Introduction Introduction The CPU Unit’s memory (RAM with battery back-up) can be divided into three parts: the User Program Memory, I/O Memory Area, and Parameter Area. This section describes the I/O Memory Area and Parameter Area. I/O Memory Area This region of memory contains the data areas which can be accessed by instruction operands.
Page 303 Section 8-2 I/O Memory Areas I/O Memory Areas 8-2-1 I/O Memory Area Structure The following table shows the basic structure of the I/O Memory Area. Area Size Range Exter- Word Access Change Status at Forcing nal I/O access access from startup bit sta- Read...
Page 304 Section 8-2 I/O Memory Areas Area Size Range Exter- Word Access Change Status at Forcing nal I/O access access from startup bit sta- Read Write alloca- Pro- or mode tion gram- change ming Device DM Area 32,768 D00000 to No (See Main- words D32767...
Page 305 Section 8-2 I/O Memory Areas Word CIO 0000 I/O Area CIO 0319 (CIO 0320) (Not used, but see note 1.) (CIO 0999) CIO 1000 Data Link Area CIO 1199 CIO 1200 Internal I/O Area CIO 1499 CIO 1500 CPU Bus Unit Area (25 words/Unit) CIO 1899 CIO 1900...
Page 306 Section 8-2 I/O Memory Areas Link Area Words in the Link Area are used for data links when LR is set as the data link area for automatic allocation for Controller Link Networks. It is also used for PLC Links. Words in the Link Area can be used in the program when LR is not set as the data link area for Controller Link Networks and PLC Links are not used.
Page 307 Section 8-2 I/O Memory Areas Word H511 Auxiliary Area (AR) The Auxiliary Area contains flags and control bits used to monitor and control PLC operation. This area is divided into two parts: A000 to A447 are read- only and A448 to A959 can be read or written. Refer to 8-11 Auxiliary Area for details on the Auxiliary Area.
Page 308 Section 8-2 I/O Memory Areas Word D00000 D20000 Special I/O Unit Area (100 words/Unit) D29599 D30000 CPU Bus Unit Area (100 words/Unit) D31599 D32000 Inner Board Area D32767 Extended Data Memory The EM Area is a multi-purpose data area that can be accessed in word-units Area (EM) only (16-bit words).
Page 309 Section 8-2 I/O Memory Areas Counter Completion Flags These flags are read as bits. A Completion Flag is turned ON by the system when the corresponding counter counts out (the set value is reached). Counter PVs The PVs are read and written as words (16 bits). The PVs count up or down as the counter operates.
Page 310 Section 8-3 I/O Area Area External allocation Fatal Error Generated Forced Set/ Forced Reset Execution of FALS(007) Other Fatal Error Functions IOM Hold IOM Hold IOM Hold IOM Hold Usable? Bit OFF Bit ON Bit OFF Bit ON Work Area (W) None Retained Retained...
Page 311 Section 8-3 I/O Area the first Rack word with any Programming Device other than a Programming Console. The maximum number of bits that can be allocated for external I/O will still be 5,120 (320 words) even if the I/O Area is expanded. Note The maximum number of external I/O points depends upon the CPU Unit being used.
Page 312 Section 8-3 I/O Area In the following example, CIO 000101 is allocated to switch 1, an external switch connected to the input terminal of an Input Unit. The ON/OFF status of switch 1 is reflected in CIO 000101 once each cycle. Ladder symbol Mnemonic 000101...
Page 313 Section 8-3 I/O Area Ladder symbol Mnemonic 000101 !LD 000101 Input Unit CPU Unit CIO 000101 Switch 0 Switch 1 Switch 7 Read just be- fore instruc- tion execu- tion. IORF(097) Refreshing When IORF(097) (I/O REFRESH) is executed, the input bits in the specified range of words are refreshed.
Page 314 Section 8-3 I/O Area The default value for input response times is 8 ms and the setting range is 0 to 32 ms. Note If the time is set to 0 ms, there will still be an ON delay time of 20 µs max. and an OFF delay time of 300 µs due to delays caused by internal elements.
Page 315 Section 8-3 I/O Area 2. Word Operand Just after the instruction is executed, the ON/OFF status of the 16 I/O points allocated to the specified word will be output to the output device(s). In the following example, CIO 000201 is allocated to an actuator, an external device connected to the output terminal of an Output Unit.
Page 316 Section 8-4 CS-series DeviceNet Area 00002 00000 00000 An output bit can be used in only one Output instruction that controls its sta- tus. If an output bit is used in two or more Output instructions, only the last instruction will be effective. CIO 000000 is controlled by CIO 000010.
Page 317 Section 8-5 Data Link Area • With user-set allocations, the user can allocate words to Slaves from the following words. CIO 0000 to CIO 0235, CIO 0300 to CIO 0511, CIO 1000 to CIO 1063 W000 to W511 H000 to H511 D00000 to D32767 E00000 to E32767 (banks 0 to C) For details on word allocations, refer to the CS/CJ Series DeviceNet Unit...
Page 318 Section 8-6 CPU Bus Unit Area A data link automatically (independently of the program) shares data with Link Areas in other CPU Units in the network through a Controller Link Unit mounted to the PLC’s CPU Rack. Data links can be generated automatically (using the same number of words for each node) or manually.
Page 319 Section 8-6 CPU Bus Unit Area Data is exchanged with CPU Bus Units once each cycle during I/O refreshing, which occurs after program execution. (Words in this data area cannot be refreshed with IORF(097).) CPU Bus Unit CPU Unit CPU Bus Unit Area (25 words/Unit) I/O re- fresh-...
Page 320 Section 8-7 Inner Board Area If the IOM Hold BIt (A50012) is ON, the contents of the CPU Bus Unit Area won’t be cleared when a fatal error occurs or the operating mode is changed from PROGRAM mode to RUN/MONITOR mode or vice-versa. If the IOM Hold BIt (A50012) is ON and the PLC Setup’s “IOM Hold Bit Status at Startup”...
Page 321 Section 8-8 Special I/O Unit Area If the IOM Hold BIt (A50012) is ON and the PLC Setup’s “IOM Hold Bit Status at Startup” setting is set to protect the IOM Hold Bit, the contents of the Inner Board Area won’t be cleared when the PLC’s power supply is cycled. Special I/O Unit Area The Special I/O Unit Area contains 960 words with addresses ranging from CIO 2000 to CIO 2959.
Page 322 Section 8-9 Work Area Bits in the Special I/O Unit Area can be force-set and force-reset. Special I/O Unit Area The contents of the Special I/O Unit Area will be cleared in the following cases: Initialization 1. The operating mode is changed from PROGRAM mode to RUN/MONITOR 1,2,3...
Page 323 Section 8-10 Holding Area 8-10 Holding Area The Holding Area contains 512 words with addresses ranging from H000 to H511 (bits H00000 to H51115). These words can be used only in the pro- gram. Holding Area bits can be used in any order in the program and can be used as normally open or normally closed conditions as often as necessary.
Page 324 Section 8-11 Auxiliary Area Set input Input Unit Reset input There are no restrictions in the order of using bit address or in the number of N.C. or N.O. conditions that can be programmed. 8-11 Auxiliary Area The Auxiliary Area contains 960 words with addresses ranging from A000 to A959).
Page 325 Section 8-11 Auxiliary Area Switching from Duplex to Simplex Operation (Duplex CPU Systems Only) Cause of Switching ■ Name Address Description Access Duplex Verification Error A02300 ON: A duplex verification error caused a switch from duplex Read-only Switch Flag to simplex operation. Only operation is switched and the active CPU Unit will not be switched.
Page 326 Section 8-11 Auxiliary Area Time of Switching ■ Name Address Description Access Time of Switch from Duplex to A024 to The time when operation was switched from duplex to sim- Read-only Simplex Operation A026 plex operation is stored. The time is cleared when duplex operation is restored. A02400 to A02407: Seconds (00 to 59) A02408 to A02415: Minutes (00 to 59) A02500 to A02507: Hours (00 to 23)
Page 327 Section 8-11 Auxiliary Area Non-fatal Duplex Errors Name Address Description Reference Non-fatal Duplex Error Flag A40214 ON: One of the following errors occurred: Duplex Duplex Verifications verification error, duplex bus error, duplex power Errors supply unit error, or duplex communications error Duplex Power Supply (See note.) Errors...
Page 328 Section 8-11 Auxiliary Area Name Address Description Access Unit Removal without a Pro- A80401 ON: The unit version of the standby CPU Unit is earlier than Read-only gramming Device Function the unit version of the active CPU Unit and the active CPU Setting Flag Unit uses a PLC Setup setting (Unit Removal without a Pro- gramming Device Function Setting) that is not supported by...
Page 329 Section 8-11 Auxiliary Area Duplex Communications Unit Information for I/O Table Generation ■ Name Address Description Access Duplex Communications Unit A26111 ON: Duplex Units are not mounted for a unit number speci- Read-only Missing or Non-Duplex Com- fied for Duplex Communications Units (i.e., one Unit is miss- munications Unit Flag ing or the mounted Units do not support duplex operation).
Page 330 Section 8-11 Auxiliary Area Name Address Description Access Duplex Communications A43600 to Active/Standby Communications Units Read-only Switched Flags (non-fatal A43615 ON: An error was detected in self-diagnosis in the active Com- communications error) munications Unit and operation was switched to the standby Communications Unit.
Page 331 Section 8-11 Auxiliary Area Duplex System Status Name Address Description Access Duplex/Simplex Mode Flag A32808 Indicates the current mode as follows: Read-only (Duplex CPU Systems only) 1: Duplex Mode 0: Simplex Mode A32808 is turned OFF in duplex initialization and thus can- not be used alone to detect errors causing a switch to Sim- plex Mode.
Page 332 Section 8-11 Auxiliary Area Name Address Description Access I/O Unconfirmed Error Flag A26109 ON: I/O detection has not been completed. Read-only Turns OFF when I/O tables are generated normally. Online Replacement Flag A26110 ON: An online replacement operation is being performed (It Read-only is treated as an I/O table creation error.) This flag will be turned OFF automatically when the online replacement...
Page 333 Section 8-11 Auxiliary Area Name Address Description Access CPU Bus Unit Error, Unit A41700 to When an error occurs in a data exchange between the CPU Read-only Number Flags A41715 Unit and a CPU Bus Unit, the CPU Bus Unit Error Flag (A40207) and the corresponding flag in A417 are turned ON.
Page 334 Section 8-11 Auxiliary Area Note 1. Do not turn ON the Maintenance Start Bit continuously from the ladder pro- gram or other source. As long as the Maintenance Start Bit is ON, errors will not be generated even if there are Unit malfunctions, so the system may be adversely affected.
Page 335 Section 8-11 Auxiliary Area Operation Start/Stop Times (CPU Unit Ver. 1.1 or Later Only) ■ Name Address Description Access Operation Start Time A515 to The time that operation started as a result of changing the Read/write A517 operating mode to RUN or MONITOR mode is stored here in BCD.
Page 336 Section 8-11 Auxiliary Area Power Supply Information ■ Name Address Description Access Startup Time A510 and These words contain the time (in BCD) at which the power Read/write A511 was turned ON. The contents are updated every time that the power is turned ON. A51000 to A51007: Seconds (00 to 59) A51008 to A51015: Minutes (00 to 59) A51100 to A51107: Hour (00 to 23)
Page 337 Section 8-11 Auxiliary Area Name Address Description Access Power ON Clock Data 2 (see A723 to These words contain the startup time/date for the second-to- Read/write note 1, 2) A725 last time that power was turned ON. The data is BCD and the storage format is the same as words A720 to A722.
Page 338 Section 8-11 Auxiliary Area File Memory Information File Memory Information for Active CPU Unit or CPU Unit in Single CPU System ■ The following words and bits provide file memory status for Single CPU Sys- tems or for the active CPU Unit in a Duplex CPU Systems. For a Only the Memory Card in the active CPU Unit is accessed.
Page 339 Section 8-11 Auxiliary Area Name Address Description Access Memory Card Format Error A34107 ON when the Memory Card is not formatted or a formatting Read-only Flag error has occurred in the left CPU Unit. File Transfer Error Flag A34108 ON when an error occurred while writing data to file memory Read-only in the left CPU Unit.
Page 340 Section 8-11 Auxiliary Area Name Address Description Access Accessing File Data Flag A34214 ON while file data is being accessed in the right CPU Unit. Read-only Memory Card Detected Flag A34215 ON when a Memory Card has been detected in the right Read-only CPU Unit.
Page 341 Section 8-11 Auxiliary Area Name Address Description Access Program Replacement End A65000 to Normal End (i.e., when A65014 is OFF) Read-only Code A65007 01 hex: Program file (.OBJ) replaced. Error End (i.e., when A65014 is ON) 00 hex: Fatal error 01 hex: Memory error 11 hex: Write-protected 12 hex: Program replacement password error...
Page 342 Section 8-11 Auxiliary Area CPU Unit/Duplex Unit Setting Name Address Description Access DIP Switch Setting Flag A39512 Shows the ON/OFF status of the following switches depend- Read-only ing on the system. Duplex CPU Systems: Status of the “A39512” switch on the DIP switch on the front of the Duplex Unit.
Page 343 Section 8-11 Auxiliary Area Program Creation Flags Name Address Description Access First Cycle Flag A20011 This flag is turned ON for one cycle when program execution Read-only starts (the operating mode is switched from PROGRAM to RUN/MONITOR). Initial Task Execution Flag A20015 When a task switches from INI to RUN status for the first Read-only...
Page 344 Section 8-11 Auxiliary Area Cycle Time Information Maximum Cycle Time A262 to These words contain the maximum cycle time in units of Read-only A263 0.1 ms. The time is updated every cycle and is recorded in 32-bit binary (0 to FFFF FFFF, or 0 to 429,496,729.5 ms). (A263 is the leftmost word.) (See note.) Present Cycle Time A264 to...
Page 345 Section 8-11 Auxiliary Area Differentiate Monitor ■ Name Address Description Access Differentiate Monitor Com- A50809 ON when the differentiate monitor condition has been estab- Read/write pleted Flag lished during execution of differentiation monitoring. Data Tracing ■ Name Address Description Access Sampling Start Bit A50815 When a data trace is started by turning this bit from OFF to...
Page 346 Section 8-11 Auxiliary Area Name Address Description Access Instruction Processing Error A29508 This flag and the Error Flag (ER) will be turned ON when an Read-only Flag instruction processing error has occurred and the PLC Setup has been set to stop operation for an instruction error. Indirect DM/EM BCD Error A29509 This flag and the Access Error Flag (AER) will be turned ON...
Page 347 Section 8-11 Auxiliary Area FAL/FALS Error Information ■ Name Address Description Access FAL Error Flag A40215 ON when a non-fatal error is generated by executing Read-only (Non-fatal error) FAL(006). Executed FAL Number Flags A360 to The flag corresponding to the specified FAL number will be Read-only A391 turned ON when FAL(006) is executed.
Page 348 Section 8-11 Auxiliary Area PLC Setup Error Information ■ Name Address Description Access PLC Setup Error Flag A40210 ON when there is a setting error in the PLC Setup. Read-only (Non-fatal error) PLC Setup Error Location A406 When there is a setting error in the PLC Setup, the location Read-only of that error is written to A406 in 4-digit hexadecimal.
Page 349 Section 8-11 Auxiliary Area Name Address Description Access Too Many I/O Points, Details A40700 to The 2 possible causes of the Too Many I/O Points Error are Read-only A40712 listed below. The 3-digit binary value in A40713 to A40715 indicates the cause of the error. (The causes corresponding to values 0 to 5 are listed below.) •...
Page 350 Section 8-11 Auxiliary Area Special I/O Unit Information ■ Name Address Description Access Special I/O Unit Number A41100 to The Duplication Error Flag (A40113) and the corresponding Read-only Duplication Flags A41615 flag in A411 through A416 will be turned ON when a Special I/O Unit’s unit number has been duplicated.
Page 351 Section 8-11 Auxiliary Area Other PLC Operating Information ■ Name Address Description Access Cycle Time Overrun Flag A40108 ON if the cycle time exceeds the maximum cycle time set in Read-only (Operation switched) the PLC Setup. (Watch Cycle Time) With a Single CPU Sys- tem in Parallel Processing Mode, this will be the cycle time for instruction execution.
Page 352 Section 8-11 Auxiliary Area Flash Memory Backup Information Name Address Description Access User Program Date A090 to These words contain in BCD the date and time that the user Read-only A093 program was last overwritten. A09000 to A09007: Seconds (00 to 59) A09008 to A09015: Minutes (00 to 59) A09100 to A09107: Hour (00 to 23) A09108 to A09115: Day of month (01 to 31)
Page 353 Section 8-11 Auxiliary Area Communications Network Communications Information ■ Name Address Description Access Communications Port Enabled A20200 to ON when a network instruction (SEND, RECV, CMND, or Read-only Flags A20207 PMCR) or background processing (see note) can be exe- cuted with the corresponding port number. Bits 00 to 07 cor- respond to communications ports 0 to 7.
Page 354 Section 8-11 Auxiliary Area Information on Communications Instruction Execution with Automatic Allocation of Communications Ports ■ Name Address Description Access Network Communications A20215 ON when a communications instruction can be executed Read-only Port Allocation Enabled Flag with automatic port allocation and there is a communications port available for automatic allocation.
Page 355 Section 8-11 Auxiliary Area Information on Explicit Message Instructions (Single CPU Systems Only) ■ Name Address Description Access Explicit Communications Error A21300 to Turn ON when an error occurs in executing an Explicit Mes- Read-only Flag A21307 sage Instruction (EXPLT, EGATR, ESATR, ECHRD, or ECHWR).
Page 356 Section 8-11 Auxiliary Area RS-232C Port Communications Information ■ Name Address Description Access RS-232C Port Communica- A39204 ON when a communications error has occurred at the RS- Read-only tions Error Flag 232C port. RS-232C Port Restart Bit A52600 Turn this bit ON to restart the RS-232C port. Read/write RS-232C Port Settings A61902...
Page 357 OMRON FB Library to execute FINS messages or DeviceNet explicit messages communications. The values set in the Set- tings for OMRON FB Library in the PLC Setup will be automatically stored in the related Auxiliary Area words A580 to A582 and used by the function...
Page 358 Section 8-12 TR (Temporary Relay) Area Duplex CPU Compatible Setting Information (CS1D-CPU67HA only) Name Address Description Access CPU Unit Model Verification A31707 1 (ON) when the model of the two CPU Units does not Read-only Error Flag match in the Duplex mode, or when the combination of the Duplex CPU compatible setting and CPU model is wrong.
Page 359 Section 8-13 Timer Area Instruction Operand 000000 TR 0 000001 000002 000003 TR 0 000003 Note A TR bit is not required when there are no execution conditions after the branch point or there is an execution condition only in the last line of the instruction block.
Page 360 Section 8-13 Timer Area The following table shows when timer PVs and Completion Flags will be reset. Instruction name Effect on PV and Completion Flag Operation in Jumps and Interlocks CNR(545) or Jumps Interlocks Mode change PLC start-up CNRX(547) (JMP-JME) or (IL-ILC) Tasks on standby PV →...
Page 361 Section 8-14 Counter Area Accuracy when Switching from Duplex to Simplex Operation The accuracy of timers may be longer in the first cycle after switching from duplex to simplex operation. The following table shows the timer accuracy in the first cycle after switching. Timer Accuracy −20 ms to Cycle time...
Page 362 Section 8-15 Data Memory (DM) Area The following table shows when counter PVs and Completion Flags will be reset. Instruction name Effect on PV and Completion Flag Reset Mode PLC startup Reset Input CNR(545) or Interlocks change CNRX(548) (IL-ILC) PV → 0000 COUNTER: CNT or Maintained Maintained...
Page 363 Section 8-15 Data Memory (DM) Area DM Area Allocation to Parts of the DM Area are allocated to Special I/O Units, CPU Bus Units, and Inner Boards for functions such as initial Unit settings. The timing for data Special Units Inner Board transfers is different for these Units, but may occur at any of the three follow- ing times.
Page 364 Section 8-16 Extended Data Memory (E18) Area Inner Board (D32000 to D32099) The Inner Board is allocated 100 words. Refer to the Board’s Operation Man- ual for details on the function of these words. CPU Unit DM Area for Inner Board (100 words) Note Inner Boards are supported for Single CPU Systems and Process-control CPU Units only.
Page 365 Section 8-17 Index Registers 0000 to 7FFF and words in the next EM bank (E00000 to E32767) can be addressed with hexadecimal values 8000 to FFFF. @E1_00100 0200 E1_00512 Address actually used. (When the current @E00100 0200 E0_00512 bank is bank 0.) Address actually used.
Page 366 Section 8-17 Index Registers Register, not the Index Register itself. Basically, the Index Registers are I/O memory pointers. • All addresses in I/O memory (except Index Registers, Data Registers, and Condition Flags) can be specified seamlessly with PLC memory addresses. It isn’t necessary to specify the data area. •...
Page 367 Section 8-17 Index Registers Example This example shows how to store the PLC memory address of a word (CIO 0002) in an Index Register (IR0), use the Index Register in an instruc- tion, and use the auto-increment variation. MOVR(560) 0002 Stores the PLC memory address of CIO 0002 in IR0.
Page 368 Section 8-17 Index Registers When the operand is treated as a word, the contents of the Index Register are used “as is” as the PLC memory address of a word. In this example MOVR(560) sets the PLC memory address of CIO 0002 in IR2 and the MOV(021) instruction copies the contents of D00000 to CIO 0002.
Page 369 Section 8-17 Index Registers The Index Registers cannot be directly addressed in any other instructions, although they can usually be used for indirect addressing. Instruction group Instruction name Mnemonic Data Movement MOVE TO REGISTER MOVR(560) Instructions MOVE TIMER/COUNTER PV TO REGISTER MOVRW(561) DOUBLE MOVE MOVL(498)
Page 370 Section 8-17 Index Registers read Index Register values from the storage words (e.g., DM area) at the beginning of each task. The values stored for each task in other areas (e.g., DM area) can then be edited using the Programming Devices, Host Link com- mands, or FINS commands.
Page 371 Section 8-18 Data Registers Sharing Index Registers This setting can be made from the CX-Programmer. To share Index Registers among tasks, remove the check from (deselect) the Use IRs/DRs independently per task Option. 8-18 Data Registers The sixteen Data Registers (DR0 to DR15) are used to offset the PLC mem- ory addresses in Index Registers when addressing words indirectly.
Page 372 Section 8-19 Task Flags 2. The PLC’s power supply is cycled and the IOM Hold Bit is OFF or not pro- tected in the PLC Setup. IOM Hold Bit Operation By default, data registers are cleared when power is interrupted or the CPU Unit is restarted.
Page 373 Section 8-20 Condition Flags Task Flag Initialization The Task Flags will be cleared in the following cases, regardless of the status of the IOM Hold Bit. 1. The operating mode is changed from PROGRAM mode to RUN/MONI- 1,2,3... TOR mode or vice-versa. 2.
Page 374 Section 8-20 Condition Flags Refer to the description of the instruction for complete details on the operation of the Condition Flags for a particular instruction. Name Symbol Label Function Error Flag P_ER Turned ON when the operand data in an instruction is incorrect (an instruction processing error) to indicate that an instruction ended because of an error.
Page 375 Section 8-20 Condition Flags !Caution Condition Flags can be tricky to use. They are manipulated by essentially all instructions and if they are not used with the proper timing, the wrong status may be read, leading to unexpected operation. Program Condition Flags with caution.
Page 376 Section 8-21 Clock Pulses 8-21 Clock Pulses The Clock Pulses are flags that are turned ON and OFF at regular intervals by the system. Name Label Symbol Operation 0.02 s Clock Pulse 0.02s P_0_02_s ON for 0.01 s 0.01 s OFF for 0.01 s 0.01 s 0.1 s Clock Pulse...
Page 377 Section 8-22 Parameter Areas Clock Pulse Accuracy The accuracy of the clock pulses is different for Duplex CPU Systems than for Single CPU Systems or CS1-H CPU Units. Accuracy in Normal Operation The following table shows the clock pulse accuracy in normal operation. Timer Accuracy ±(10 ms + cycle time)
Page 378 Section 8-22 Parameter Areas tered I/O Tables. Refer to the Programming Device’s Operation Manual for details on registering the I/O Tables. Programming Device CPU Unit Commu- Analog Output 16 nications Regis- Output 12 Input 16 tered Tables The I/O Verification Error Flag (A40209) will be turned ON if the models and locations of the Units actually mounted to the PLC (CPU Rack and Expansion I/O Racks) do not match the information in the Registered I/O Tables.
Page 379 Section 8-22 Parameter Areas Relay Network Table This table lists the network address and node number of the first relay node to contact in order to reach the destination network. The destination network is reached through these relay nodes. Local Network Table This table lists the network address and unit number of the Communications Unit connected to the local PLC.
Page 380 Section 8-22 Parameter Areas...
Page 381 SECTION 9 CPU Unit Operation and the Cycle Time This section describes the internal operation of the CPU Unit and the cycle used to perform internal processing. CPU Unit Operation ..........9-1-1 General Flow for Duplex CPU Systems .
Page 382 9-5-16 Data Control Instructions ....... . . 9-5-17 Subroutine Instructions ........9-5-18 Interrupt Control Instructions .
Page 383 Section 9-1 CPU Unit Operation CPU Unit Operation 9-1-1 General Flow for Duplex CPU Systems The following flowchart shows the overall operation of the CPU Units in a Duplex CPU System. CPU Unit Operation Flow This section describes the internal operation of the CPU Unit and the cycle used to perform internal processing.
Page 384 Section 9-1 CPU Unit Operation 9-1-2 General Flow for Single CPU Systems The following flowchart shows the overall operation of the CPU Unit. Note The CPU Unit’s processing mode is set to Normal Mode, Parallel Processing with Synchronous Memory Access, or Parallel Processing with Asynchronous Memory Access in the PLC Setup (Programming Console address 219, bits 08 to 15).
Page 385 Section 9-1 CPU Unit Operation Parallel Processing (Single CPU Systems Only) The following two types of processing are performed in parallel in either of the Parallel Processing Modes. 1. Program execution: Includes user program execution and I/O refreshing. 1,2,3... It is this cycle time that is monitored from a Programming Device. 2.
Page 386 Section 9-1 CPU Unit Operation 9-1-3 I/O Refreshing and Peripheral Servicing I/O Refreshing I/O refreshing involves cyclically transferring data with external devices using preset words in memory. I/O refreshing includes the following: • Refreshing the CIO Area for Basic I/O Units •...
Page 387 Section 9-1 CPU Unit Operation and executed every cycle. If all servicing cannot be completed within the allo- cated time, the remaining servicing is performed the next cycle. Units Servicing Event servicing for Non-scheduled servicing for FINS commands from Special I/O Special I/O Units Units, CPU Bus Units, and Inner Boards Non-scheduled servicing for FINS commands from the CPU...
Page 388 Section 9-1 CPU Unit Operation • Autoboot using the autotransfer files in the Memory Card if one is inserted. • Perform self-diagnosis (user memory check). • Restore the user program (See note 3.) Note 1. The I/O memory is held or cleared according to the status of the IOM Host Bit and the setting for IOM Hold Bit Status at Startup in the PLC Setup (read only when power is turned ON).
Page 389 Section 9-1 CPU Unit Operation 9-1-5 Duplex Initialization (Duplex CPU Systems Only) The Duplex System is initialized when the power supply is turned ON, when operation is started, when the user program or PLC Setup is transferred, etc. It involves transferring data from the active CPU Unit to the standby CPU Unit and verifying that both CPU Units contain the same data.
Page 390 Section 9-2 CPU Unit Operating Modes Duplex operating status does not exist during duplex initialization (i.e., duplex initialization is performed in simplex operating status). This means that the active CPU Unit will not be switched. Because of this, operation will not con- tinue if an error that would cause the CPU Unit to be switched occurs during duplex initialization, including CPU errors, memory errors, fatal Inner Board errors, program errors, exceeding the cycle time limit, and execution of FALS...
Page 391 Section 9-2 CPU Unit Operating Modes Mode Modify Force- Changing timer/ Changing timer/ Changing I/O Unit online Setup program set/reset counter SV counter PV memory PV replacement PROGRAM MONITOR Note The following table shows the relationship of operating modes to tasks. Mode Cyclic task status Interrupt task...
Page 392 Section 9-3 Power OFF Operation 2. The cycle time will increase by approximately 10 ms when the operating mode is changed from MONITOR to RUN mode. This will not, however, cause an error for exceeding the maximum cycle time limit. I/O Memory I/O Memory Output bits allocated to Output Units...
Page 393 Section 9-3 Power OFF Operation 85% of the rated voltage or less 10 ms 25 ms 0 to 10 ms Momentary power interruption not detected and operation continues. Power supply voltage 10 to 25 ms Power supply voltage Operation will continue or stop Over 25 ms depending on whether or not a Power supply...
Page 394 Section 9-3 Power OFF Operation 2. If the Power OFF Detection Delay Time is set (0 to 10 ms in 1-ms incre- ments) in the PLC Setup, the CPU reset signal will turn ON while the inter- nal power supply is maintained and the CPU Unit will be reset. Note a) Power OFF interrupt tasks cannot be used in Duplex CPU Sys- tems.
Page 395 Section 9-3 Power OFF Operation must be set to maintain the setting of the IOM Hold Bit at Startup, or the following type of instruction must be included at the beginning of the program to set A530 to A5A5 hex. Set A530 to A5A5 Hex at the A20011 beginning of the program to enable...
Page 396 Section 9-4 Computing the Cycle Time Computing the Cycle Time 9-4-1 CPU Unit Operation Flowchart The CS1D CPU Units process data in repeating cycles from the overseeing processing up to peripheral servicing as shown in the following diagram. Normal Processing Mode Power ON Checks Unit connection status.
Page 397 Section 9-4 Computing the Cycle Time Parallel Processing Mode Power ON Checks Unit connection status Program Execution Peripheral Cycle Servicing Cycle Check hardware, Check user program etc. memory, etc. Check OK? Check OK? Set error flags. Flashing: Non-fatal Services Execute user ERR/ALM error peripherals.
Page 398 Section 9-4 Computing the Cycle Time 9-4-2 Cycle Time Overview Normal Processing Mode The cycle time depends on the following conditions. • Type and number of instructions in the user program (in all cyclic tasks that are executed during a cycle, including additional cyclic tasks). •...
Page 399 Section 9-4 Computing the Cycle Time 4: I/O Refreshing Details Processing time and fluctuation cause Basic I/O Units Basic I/O Units are refreshed. Out- I/O refresh time for each Unit puts from the CPU Unit to the I/O multiplied by the number of Unit are refreshed first for each Units used Unit, and then inputs.
Page 400 Section 9-4 Computing the Cycle Time Details Processing time and fluctuation cause Services Inner Board events (Single CPU If a uniform peripheral servicing time Systems or Process-control CPU Units hasn’t been set in the PLC Setup for this only) servicing, 4% of the previous cycle’s cycle time (calculated in step (3)) will be allowed for peripheral servicing.
Page 401 Section 9-4 Computing the Cycle Time • Socket services for specific control bits for Ethernet Units and the number of send/receive words • Fixed cycle time setting in the PLC Setup • File access in file memory, and the amount of data transferred to/from file memory •...
Page 402 Section 9-4 Computing the Cycle Time Parallel Processing with Synchronous Memory Access (Single CPU Systems Only) Program Execution Cycle The program execution cycle time depends on the same conditions as the Normal Mode. Partial peripheral servicing ((5) below), however, is restricted to servicing for file and I/O memory access.
Page 403 Section 9-4 Computing the Cycle Time Note 1. The cycle time display on a Programming Device is the Program Execution Cycle Time. 2. The peripheral service cycle time varies with the event load and number of Units that are mounted. In a Parallel Processing Mode, however, this vari- ation will not affect the program execution cycle time.
Page 404 Section 9-4 Computing the Cycle Time Note Longer I/O refresh times will be required according to the distance from the CPU Rack to the Unit when these Units are mounted to Long-distance Expan- sion Racks. Multiply the values given in the table by the factors on line *1 in the following graph.
Page 405 Section 9-4 Computing the Cycle Time Unit Name Model I/O refresh time per Unit Normal Mounted on Long- distance Expansion Rack (See note.) 0.2 ms × *2 CS-series Special I/ Analog I/O Unit CS1W-MAD44 0.12 ms O Units 0.2 ms × *2 Analog Input Unit CS1W-AD041/081 0.12 ms...
Page 406 Section 9-4 Computing the Cycle Time Increase in Cycle Time Caused by CPU Bus Units Unit Name Model Increase Remarks CPU Bus Units Controller Link CS1W-CLK11 0.1 ms There will be an increase of 0.1 ms + 0.7 µs x number of data link Unit CS1W-CLK21-V1 With Long-dis-...
Page 407 Section 9-4 Computing the Cycle Time Increase in Cycle Time Caused by Inner Board Name Model Increase Remarks Serial Com- CS1W- 0.22 ms There will be an increase of up to the munications SCB21- following time when a protocol macro is Board V1/41-V1 executed:...
Page 408 Section 9-4 Computing the Cycle Time 9-4-5 Online Editing Cycle Time Extension When online editing is executed from a Programming Device (such as Pro- gramming Console or CX-Programmer) while the CPU Unit is operating in MONITOR mode to change the program, the CPU Unit will momentarily sus- pend operation while the program is being changed.
Page 409 Section 9-4 Computing the Cycle Time 9-4-7 Duplex Processing Cycle Time Extension (Duplex CPU Systems Only) The cycle time for a Duplex CPU System can be extended at various times as described below. Enter actual system operation only after verifying that the system operates correctly for the maximum possible cycle time.
Page 410 Section 9-4 Computing the Cycle Time The following table list the time by which the cycle time will be extended depending on the error that caused operation to be switched. Error switching Cycle time Remarks operation extension Switch with CPU 11.5 ms Time required to detect switch setting: 11 ms Unit switch setting...
Page 411 Section 9-4 Computing the Cycle Time Maximum I/O Response The I/O response time is longest when data is retrieved immediately after I/O Time refresh of the Input Unit. The maximum I/O response time is the total of the Input ON delay, (the cycle time ×...
Page 412 Section 9-4 Computing the Cycle Time The interrupt response time of I/O interrupt tasks is the sum of the Input ON delay (0.2 ms max.) and the software interrupt response time (1 ms max.). Input Input ON delay (Interrupt Input Unit retrieval) Software interrupt response time Interrupt task execution I/O interrupt task inter-...
Page 413 Note 1. Program capacity for CS-series PLCs is measured in steps, whereas pro- gram capacity for previous OMRON PLCs, such as the C-series and CV- series PLCs, was measured in words. Basically speaking, 1 step is equiv- alent to 1 word. The amount of memory required for each instruction, how-...
Page 414 Section 9-5 Instruction Execution Times and Number of Steps 9-5-1 Sequence Input Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) LOAD 0.02 0.02...
Page 415 Section 9-5 Instruction Execution Times and Number of Steps 9-5-2 Sequence Output Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) OUTPUT 0.02 0.02...
Page 416 Section 9-5 Instruction Execution Times and Number of Steps 9-5-3 Sequence Control Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) NO OPERA- 0.02 0.02...
Page 417 Section 9-5 Instruction Execution Times and Number of Steps 9-5-4 Timer and Counter Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) TIMER 0.72...
Page 418 Section 9-5 Instruction Execution Times and Number of Steps 9-5-5 Comparison Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) Input Com- LD, AND, 0.10 0.10...
Page 419 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) Time Com- LD, AND, 23.0 25.1 36.4...
Page 420 Section 9-5 Instruction Execution Times and Number of Steps 9-5-6 Data Movement Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) MOVE 0.20 0.18...
Page 421 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) REVERS- SFTR Shifting 1 word IBLE SHIFT 481.6 615.3...
Page 422 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) SHIFT N-BIT NSFL Shifting 1 bit DATA LEFT 37.5 40.3...
Page 423 Section 9-5 Instruction Execution Times and Number of Steps 9-5-9 Symbol Math Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) SIGNED 0.20 0.18...
Page 424 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) −BL DOUBLE 11.4 12.8 11.4 12.8 14.0...
Page 425 Section 9-5 Instruction Execution Times and Number of Steps 9-5-10 Conversion Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) BCD-TO- 0.26 0.22 0.22...
Page 426 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) SIGNED BINS Data format set- BCD-TO- ting No.
Page 427 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) ASCII-TO-4- NUM4 11.4 11.3 DIGIT NUM- (See note 3.) (See...
Page 428 Section 9-5 Instruction Execution Times and Number of Steps 9-5-12 Special Math Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) BINARY ROTB 41.2...
Page 429 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) TANGENT 16.3 16.3 16.3 16.3 16.6 ARC SINE...
Page 430 Section 9-5 Instruction Execution Times and Number of Steps 9-5-14 Double-precision Floating-point Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) DOUBLE LD, AND, 10.3...
Page 431 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) DOUBLE COSD 32.9 43.0 32.6 43.0 43.4...
Page 432 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) SETR RECORD LOCATION GETR RECORD NUMBER DATA...
Page 433 Section 9-5 Instruction Execution Times and Number of Steps 9-5-16 Data Control Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) PID CON- 416.0 436.2...
Page 434 Section 9-5 Instruction Execution Times and Number of Steps 9-5-17 Subroutine Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) SUBROU- 5.40 1.26 5.40...
Page 435 Section 9-5 Instruction Execution Times and Number of Steps 9-5-19 Step Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) STEP STEP 12.6 17.4...
Page 436 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) MATRIX 17.0 47.8 68.1 Data input value: INPUT (See note 2.)
Page 437 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) Serial Com- TXDU 139.0 munications (See note 2.) (See note 2.)
Page 438 Section 9-5 Instruction Execution Times and Number of Steps 9-5-23 File Memory Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) READ DATA FREAD 328.0...
Page 439 Section 9-5 Instruction Execution Times and Number of Steps 9-5-25 Clock Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) CALENDAR CADD 94.1 38.3...
Page 440 Section 9-5 Instruction Execution Times and Number of Steps 9-5-27 Failure Diagnosis Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) FAILURE 244.4 15.4...
Page 441 Section 9-5 Instruction Execution Times and Number of Steps 9-5-28 Other Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) SET CARRY STC 0.06 0.06 0.06...
Page 442 Section 9-5 Instruction Execution Times and Number of Steps 9-5-29 Block Programming Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) BLOCK BPRG 12.1...
Page 443 Section 9-5 Instruction Execution Times and Number of Steps Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) COUNTER CNTW 18.0 17.9 18.0 17.9 22.6...
Page 444 Section 9-5 Instruction Execution Times and Number of Steps 9-5-30 Text String Processing Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) MOV$ 43.6...
Page 445 Section 9-5 Instruction Execution Times and Number of Steps 9-5-31 Task Control Instructions Instruction Mnemonic Code Length Execution time (µs) Conditions (steps) CPU6@HA CPU6@H CPU@@SA CPU6@S CPU4@S (See (Duplex CPU) (Duplex CPU) (Single (Single (Single note 1.) CPU) CPU) CPU) TASK ON TKON 15.7...
Page 446 Guidelines on Converting Guidelines are provided in the following table for converting the program Program Capacities from capacity (unit: words) of previous OMRON PLCs (SYSMAC C200HX/HG/HE, Previous OMRON PLCs CVM1, or CV-series PLCs) to the program capacity (unit: steps) of the CS- series PLCs.
Page 447 Section 9-5 Instruction Execution Times and Number of Steps CS-series steps = “a” (words) of previous PLC + n Instructions Variations Value of n when Value of n when converting from converting from C200HX/HG/HE to CV-series PLC or CS Series CVM1 to CS Series Special None...
Page 448 Section 9-5 Instruction Execution Times and Number of Steps...
Page 449 SECTION 10 Troubleshooting This section provides information on hardware and software errors that occur during PLC operation. 10-1 Error Log........... . . 10-2 Error Processing .
Page 450 Section 10-1 Error Log 10-1 Error Log Each time that an error occurs, the CPU Unit stores error information in the Error Log Area. The error information includes the error code (stored in A400), error contents, and time that the error occurred. Up to 20 records can be stored in the Error Log.
Page 451 Section 10-2 Error Processing 10-2 Error Processing 10-2-1 Error Categories Error are classified as shown in the following table for CS1D Duplex Systems. Error status Duplex CPU Systems Single CPU Systems Duplex Mode Simplex Mode Operation switching errors Operation continues Operation stops.
Page 452 Section 10-2 Error Processing 10-2-2 Error Information There are basically five sources of information on errors that have occurred: • The indicators on the CPU Units • The indicators on the Duplex Unit (Duplex CPU Systems only) • The Auxiliary Area Error Flags •...
Page 453 Section 10-2 Error Processing Indicator Status and Error Classifications for Duplex CPU Systems Simplex Mode Fatal errors Non-fatal errors Duplex initializa- standby switch Duplex Mode Operation switched Operation Operation continues tion settings and operation stops error continues Indicator Fatal Fatal Duplex Non-fatal Communications...
Page 454 Section 10-2 Error Processing 10-2-3 Troubleshooting Flowcharts The following flowchart shows troubleshooting using a Programming Console. Determine the error according to the mode and take appropriate measures. Duplex CPU Systems in Duplex Mode Error during operation POWER Not lit. indicator Go to 10-2-7 Power Supply Check .
Page 455 Section 10-2 Error Processing Duplex Mode, Continued Operation switching error (The CPU Unit that was Connect Programming the active CPU Unit.) Console to standby CPU Unit. --------------------------- CPU error (WDT) Memory error MEMORY ERR FATAL INNER ERR Fatal Inner Board error PROGRAM ERR Program error CYCLE TIME ERR...
Page 456 Section 10-2 Error Processing Duplex CPU Systems in Simplex Mode or Single CPU Systems Error during operation Not lit. POWER Go to 10-2-7 Power Supply Check . indicator lit? indicator on CPU Unit lit? Not lit. Not lit. ERR/ALM Go to 10-2-13 Environmental indicator Conditions Check.
Page 457 Section 10-2 Error Processing 10-2-4 Errors and Troubleshooting The following tables show error messages for errors which can occur in CS1D PLCs and indicate the likely cause of the errors. CPU Standby Errors When the following indicator status appears during operation in RUN or MON- and Expansion Rack ITOR Mode, a CPU standby error or Expansion Rack power interruption has Power Interruptions...
Page 458 Section 10-2 Error Processing Operation Switching In a Duplex CPU System, the standby CPU Unit will become the active CPU Errors (Operation Unit and continue operation (assuming the standby CPU Unit is normal) in Stops in Simplex RUN or MONITOR mode and in Simplex Mode whenever an error causing operation to switch occurs.
Page 459 Section 10-2 Error Processing Troubleshooting Table For all of the following errors, operation will be switched to the standby and operation will continue in a Duplex CPU System in Duplex Mode. If the error occurs in a Single CPU System or in a Duplex CPU System in Simplex Mode, operation will stop.
Page 460 Section 10-2 Error Processing Error Program- Error Error Flags Probable cause Possible remedy ming flags in code (in Console Auxiliary A400) word display Area data Program PRO- A40109: 80F0 A294 to The program is incorrect. See If the error has occurred in both the active error GRAM Program...
Page 461 Section 10-2 Error Processing Error Program- Error Error Flags Probable cause Possible remedy ming flags in code (in Console Auxiliary A400) word display Area data Program PRO- A40109: A294 to A29514: Illegal instruction If the error has occurred in both the active 80F0 error and standby CPU Units, retransfer the pro-...
Page 462 Section 10-2 Error Processing Fatal Errors For the following errors, operation will stop for a Duplex CPU System in Duplex Mode or in Simplex Mode, or for a Single CPU System. Connect the CX-Programmer or a Programming Console to display the error message (in the PLC Error Window on the CX-Programmer).
Page 463 Section 10-2 Error Processing Troubleshooting Table For the following errors, operation will stop for a Duplex CPU System in Duplex Mode or in Simplex Mode, or for a Single CPU System. Error Program- Error Error Flags Probable cause Possible remedy ming flags in code (in...
Page 464 Section 10-2 Error Processing Non-fatal Errors Operation will continue for any of the following errors for a Duplex CPU Sys- tem in Duplex Mode or in Simplex Mode, or for a Single CPU System. For some of these errors, operation for a Duplex CPU System will switch from Duplex Mode to Simplex Mode and for other errors, operation will remain in Duplex Mode.
Page 465 Section 10-2 Error Processing Errors for which Duplex If any of the following errors occurs for a Duplex CPU System in Duplex Mode, Mode Continues operation will continue in Duplex Mode and in RUN or MONITOR mode. Oper- ation will also continue if any of these errors occurs in Simplex Mode or in a Single CPU System.
Page 466 Section 10-2 Error Processing Error Program- Error Error Flags Probable cause Possible remedy ming Con- flags in code (in sole Auxiliary A400) word display Area data CS-series CPU BU A40207: 0200 to A417: An error occurred in a data exchange Check the Unit indicated in A417.
Page 467 Section 10-2 Error Processing Other Errors Error Error Flags Error Probable cause Possible remedy flags in code Auxiliary word Area A400) data ---- ---- ---- Peripheral A communica- Check the PRPHL set- Power Supply Unit Lit green. POWER Port Com- tions error has ting on the Duplex Unit Lit green.
Page 468 Section 10-2 Error Processing Rank Error Programming Error flag Code Console display stored in A400 I/O setting error I/O SET ERR A40110 80E0 I/O Setting Error Flag Program error PROGRAM ERR A40109 80F0 Program Error Flag Cycle time CYCLE TIME ERR A40108 809F overrun error...
Page 469 Section 10-2 Error Processing 10-2-6 Duplex Check Errors Causing Operation to Switch to Standby CPU CPU STATUS indicator for active Unit (Duplex CPU Systems CPU Unit lights. Only) Operation switched to Simplex Mode. Take countermeasures for CPU Unit where the error occurred. Error eliminated? Switch the switch for the CPU...
Page 470 Section 10-2 Error Processing Duplication Verification Errors (Duplex CPU Systems Only) The DPL STATUS indicators are flashing red. DLP verification error (to Simplex Mode) Check the following bit in A317 channel of the standby CPU using the peripheral tool. 14: Active CPU missing bit The active CPU Unit is not mounted, or the use active CPU setting switch is set to...
Page 471 Section 10-2 Error Processing Duplex Bus Errors (Duplex CPU Systems DPL STATUS indicator lit red. Only) Duplex bus error (to Simplex Mode) Turn power supply OFF and then ON. STATUS indicator still flashing red? Replace the Duplex Unit. Operation should restart in Duplex Mode. Duplex Power Supply Errors Duplex Power Supply Error Flag...
Page 472 Section 10-2 Error Processing 10-2-7 Power Supply Check Power supply voltage Allowable voltage range Power Supply Unit CS1D-PA207R 100 to 120 V AC 85 to 132 V AC Power indicator not lit. 200 to 240 V AC 170 to 264 V AC CS1D-PD024 24 V DC 19.2 to 28.8 V DC...
Page 473 Section 10-2 Error Processing 10-2-8 Memory Error Check Memory error occurred. Conditions have not been met for A40309 automatic transfer at startup. Confirm (autotransfer at that the required files are on the startup error) Memory Card and the pin 2 on the DIP switch is OFF.
Page 474 Section 10-2 Error Processing 10-2-9 Program Error Check Program error occurred. Make sure that a power OFF interrupt Power OFF interrupt A29512 (Task Error Flag) ON? task enabled in PLC task has been created. setup? Not applicable The specified task does not exist. What is the value #FFFF of Task Number when Program...
Page 475 Section 10-2 Error Processing 10-2-12 Battery Error Check Battery error occurred. Set the PLC Setup so that battery errors are not detected. (DM Area contents may be unstable when this Battery-free operation setting is used.) required? Refer to the CS/CJ Programming Manual for details.
Page 476 Section 10-2 Error Processing 10-2-14 I/O Check The I/O check flowchart is based on the following ladder diagram section assuming that SOL1 does not turn ON. (LS1) (LS1) 000002 000003 000500 SOL1 000500 Start Indicator of 000500 normal? Monitor ON/OFF status of Check terminal voltage Replace terminal block Correct wiring...
Page 477 Section 10-3 Troubleshooting Racks and Units 10-3 Troubleshooting Racks and Units CPU Racks and Standard Expansion Racks Symptom Cause Remedy POWER indicator is not lit on Power PCB short-circuited or damaged. Replace Power Supply Unit or Back- Supply Unit. plane. RUN indicator is not lit on CPU Unit (1) Error in program.
Page 478 Section 10-3 Troubleshooting Racks and Units Symptom Cause Remedy Cycle time is too long. (1) A CPU Bus Unit that is allocated many Move the CPU Bus Unit to the CPU Rack. words (e.g., Controller Link Unit) is mounted to a Long-distance Expansion Rack.
Page 479 Section 10-3 Troubleshooting Racks and Units Output Units Symptom Cause Remedy Not all outputs turn ON. (1) Load is not supplied with power. Supply power (2) Load voltage is low. Adjust voltage to within rated range. (3) Terminal block screws are loose. Tighten screws.
Page 480 Section 10-4 Troubleshooting Errors in Duplex Connecting Cables 10-4 Troubleshooting Errors in Duplex Connecting Cables 10-4-1 Identifying and Correcting the Cause of the Error When a duplexed Connecting Cable is disconnected or damaged, the location of the error can be identified with Auxiliary Area flags (in A270 and A271), the CS1D I/O Control Unit LED indicators, and the CS1D I/O Interface Unit LED indicators.
Page 481 Section 10-4 Troubleshooting Errors in Duplex Connecting Cables Error Indications When an Expansion Unit is Removed ■ In this example, the Expansion Unit in Rack 1, slot 0 is removed, so the affected slot 0 flags in A270 (A27002, A27004, and A27006) are turned ON. The Duplex Communications Cable Status Flags are turned OFF for the all of the Racks (A27100 to A27102).
Page 482 Section 10-4 Troubleshooting Errors in Duplex Connecting Cables Cause Remedy Cable IN/OUT connections are Connect the Connecting Cables properly. reversed. If either cable is connected to the wrong side when the power supply is turned ON, an I/O bus error C will occur and the PLC will not operate. Note If the cable to the other slot is discon- nected, the PLC will stop.
Page 483 SECTION 11 Inspection and Maintenance This section provides inspection and maintenance information. 11-1 Inspections ........... 11-1-1 Inspection Points.
Page 484 Section 11-1 Inspections 11-1 Inspections Daily or periodic inspections are required in order to maintain the CS1D’s functions in peak operating condition. 11-1-1 Inspection Points The major electronic components in CS1D PLCs are semiconductor compo- nents, which although have an extremely long life time, can deteriorate under improper environmental conditions.
Page 485 Section 11-1 Inspections Item Inspection Criteria Action Installation and Check that each Unit is No looseness Tighten loose screws with a Phil- wiring installed securely. lips-head screwdriver. Check that cable connectors No looseness Correct any improperly installed are fully inserted and locked. connectors.
Page 486 • If a faulty Unit is being returned for repair, describe the problem in as much detail as possible, enclose this description with the Unit, and return the Unit to your OMRON representative. • For poor contact, take a clean cotton cloth, soak the cloth in industrial alcohol, and carefully wipe the contacts clean.
Page 487 Section 11-2 Replacing User-serviceable Parts The time that CPU power is ON shown in the following table (power supply rate) is calculated as follows: Power supply rate = Total time power is ON/(total time power is ON + total time power is OFF) The following table shows minimum lifetimes and typical lifetimes for the backup battery.
Page 488 Section 11-2 Replacing User-serviceable Parts ERR/ALM BKUP PRPHL COMM When the ERR/ALM indicator flashes, connect the CX-Programmer to the peripheral port and read the error message. If the message “BATT LOW” appears on the Programming Console* and the Battery Error Flag (A40204) is ON*, first check whether the battery is properly connected to the CPU Unit.
Page 489 Section 11-2 Replacing User-serviceable Parts Type Unit version Number of Replacement Replacement method battery time (see note) connectors CPU Duplex System No unit version 3 min. Refer to Replacement Procedure for CPU Units with One Battery Unit Ver. 1.1 Connector. Unit Ver.
Page 490 Section 11-2 Replacing User-serviceable Parts 3. Remove the old battery from the compartment, but leave its connector con- nected. Old battery Leave connected. Old battery 4. Insert the new battery into the battery compartment with the cable and connector facing outward. Battery compartment New battery New battery...
Page 491 Section 11-2 Replacing User-serviceable Parts New battery Old battery Old battery 6. Remove the old battery’s connector. Old battery 7. Push the new battery’s wire into the battery compartment and close the cover. 8. Connect a Programming Device and verify that the Battery Error has been cleared.
Page 492 Section 11-2 Replacing User-serviceable Parts !Caution Do not short the battery terminals or charge, disassemble, heat, or incinerate the battery. Do not subject the battery to strong shocks. Doing any of these may result in leakage, rupture, heat generation, or ignition of the battery. !Caution Dispose of any battery that has been dropped on the floor or otherwise sub- jected to excessive shock.
Page 493 Section 11-3 Replacing a CPU Unit 11-3 Replacing a CPU Unit If the active CPU Unit fails during operation in a Duplex CPU System, the standby CPU Unit will switch to become the active CPU Unit and operation will continue. Use the following procedure to replace the faulty CPU Unit and restore duplex operation.
Page 494 Section 11-3 Replacing a CPU Unit 11-3-2 CPU Unit Replacement Procedure 1. Change the USE/NO USE switch for the CPU Unit to be replaced to NO 1,2,3... USE. When the switch is changed to NO USE, the power supply to the CPU Unit will turn OFF.
Page 495 Section 11-3 Replacing a CPU Unit Duplex CPU compatibility setting is set with DIP switches (Pin 4, 5, and 6). Set DIP switches (Pins 4, 5, and 6) of the CPU67HA according to the model of the CPU Unit to be replaced. Note When changing the Duplex CPU Compatible Setting using the DIP switches (Pins 4, 5, and 6), do so after performing Memory All Clear...
Page 496 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units 6. Use the following procedure if the PLC Setup has not been changed to en- able automatic recovery to Duplex Mode. a) Confirm that the switch is set for duplex operation. DPL SW Turn OFF for Duplex operation.
Page 497 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units !Caution If an Output Unit is replaced and ON status is held in memory for that Unit, the corresponding output will turn ON as soon as the online replacement opera- tion has been completed.
Page 498 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units To exit online replacement, go to step 7. To start online replacement, con- tinue to step 4. 4. Specify the number of the Rack and the slot where the Unit is to be re- placed.
Page 499 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Replace End ↓ 5-8=I32 Canceling Online Use the following procedure to return to the initial display after starting the Replacement online replacement procedure. • Instead of the Rack and slot numbers, press the following keys to enter Online Replacement Mode.
Page 500 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Word Bits Description A040 00 to 08 Used to confirm when online replacement is in progress for a slot on Rack 6. A bit will be ON when online replacement is in progress for the corresponding slot.
Page 501 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units 11-4-2 Replacing More than One Unit at a Time The PLC Setup can be set to enable online replacement of more than one Unit at a time. This operation is possible only from the Programming Console.
Page 502 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Replace End ↓ 3-2=M96 When the online replacement procedure for the last Unit has been ended, the display will not change even if the INS Key is pressed. If the INS Key is pressed without pressing the Down Key, the Units for which online replace- ment procedures have been started can be displayed without ending the pro- cedures.
Page 503 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Replace End? ~5-8=I32 Replace End? ~5-8=I32 ***** 11-4-4 Online Replacement Precautions for Special I/O and CPU Bus Units Special I/O Units and CPU Bus Units have hardware switches, software switches, and parameters, all of which help to control Unit operation.
Page 504 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Unit Settings and Replacement Precautions Special I/O Units Name and model Settings Precautions number Hardware Settings Settings stored settings stored in in Special I/O on Special CPU Unit Unit I/O Unit...
Page 505 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Name and model Settings Precautions number Hardware Settings Settings stored settings stored in in Special I/O on Special CPU Unit Unit I/O Unit GP-IB Interface Unit num- Settings in None Refer to the GP-IB Unit operation manual for replacement proce-...
Page 506 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units CPU Bus Units Name and model Settings Precautions number Hardware Settings stored Settings stored settings on in CPU Unit in CPU Bus CPU Bus Unit Unit Optical-ring Control- Unit number In CPU Bus...
Page 507 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Name and model Settings Precautions number Hardware Settings stored Settings stored settings on in CPU Unit in CPU Bus CPU Bus Unit Unit Ethernet Units Unit number In CPU Bus None Refer to the Ethernet Unit operation manual for replacement...
Page 508 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Name and model Settings Precautions number Hardware Settings stored Settings stored settings on in CPU Unit in CPU Bus CPU Bus Unit Unit DeviceNet Unit Unit number In CPU Bus In non-volatile Refer to the DeviceNet Unit operation manual for replace-...
Page 509 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Note 1. Refer to the Programming Manual (W339), 5-2-6 Simple Backup Opera- tion for details on the simple backup function. If the Memory Card is insert- ed in the new Unit, the data on the Memory Card will be automatically transferred to the Unit when the online replacement operation is complet- 2.
Page 510 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units will operate according to the “Unit Removal without a Programming Device function.” A Programming Device can be used for online replacement even if one of these functions is enabled. Two or more Units can be removed at one time with this setting.
Page 511 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Note A Unit error may occur if the Unit is removed slowly. Steps required before Starting Online Replacement without a Programming Device The following steps must be performed in advance before replacing a Unit online without a PLC Programming Device.
Page 512 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units This bit can be turned ON externally (just like the Online Replacement Com- pleted Bit) by allocating the bit to an external switch on an Input Unit and inputting the signal or turning ON the bit from a PT.
Page 513 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Note Do not turn ON the Online Replacement Completed Bit (A80215) continu- ously from the ladder program or other source. If the Unit is mounted while the Online Replacement Completed Bit is ON, the PLC (CPU Unit) may stop operating.
Page 514 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units Ladder Programming for the Online Replacement Bit and Maintenance Start Bit Example Input from external switch Turn bit ON with the corresponding switch. (for Online Replacement Completed Bit) A80215 Online Replacement...
Page 515 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units 1. Confirm that the Unit Removal without a Programming Device or the Re- 1,2,3... moval/Addition of Units without a Programming Device function is enabled in the PLC Setup. !Caution Do not touch any of the terminals or terminal blocks while the power is being supplied.
Page 516 Section 11-4 Online Replacement of I/O Units, Special I/O Units, and CPU Bus Units 2. Remove the Unit that is being replaced. When the Unit Removal without a Programming Device function is select- ed, one of the following non-fatal errors will be generated at this point, de- pending on the type of Unit that was removed.
Page 517 Section 11-5 Replacing Power Supply Unit 11-5 Replacing Power Supply Unit Use the following procedure to replace a Power Supply Unit when ever it is necessary to replace it, e.g., when an error is detected in the Power Supply Unit or for periodic maintenance. 1.
Page 518 Section 11-6 Replacement of Expansion Units 1. Disconnect the Connecting Cables from the Unit being replaced. 1,2,3... Remove cables from Unit being replaced. Replace Note Before replacing an Expansion Unit, verify that the other Expansion Unit in the Rack is operating normally by checking the Duplex Com- munications Cable Error Flags in A270 as well as the LED Indica- tors on each Expansion Unit.
Page 519 Section 11-6 Replacement of Expansion Units 3. Tighten the screws on the Expansion Unit, and once the Unit is secured, verify that the ERR indicator on the Expansion Unit is lit. Then connect the disconnected Expansion Cable to the new Expansion Unit. In this case, connect the Expansion Cable in its original condition.
Page 520 Section 11-7 Replacing the Duplex Unit 11-7 Replacing the Duplex Unit With a Duplex CPU Dual I/O Expansion System, the Duplex Unit can be replaced when an error occurs in the Unit or during periodic maintenance. Use the following procedure to replace an Duplex Unit. Note The only Duplex Unit that can be replaced is the CS1D-DPL02D Duplex Unit, which is used in a Duplex CPU Dual I/O Expansion System.
Page 521 Section 11-7 Replacing the Duplex Unit 2. Remove the Duplex Unit. Verify that the new Duplex Unit’s DPL Switch is set to NO USE and mount the new Duplex Unit. Standby CPU Active CPU Verify that the new Duplex Unit's DPL Switch is set to NO USE before mounting the Unit.
Page 522 Section 11-7 Replacing the Duplex Unit...
Page 523 Appendix A Specifications of Basic I/O Units and High-density I/O Units List of Basic I/O Units Input Units Category Name Specifications Model Page CS-series Basic AC Input Units 100 to 120 V AC/V DC, 16 inputs, 50/60 Hz CS1W-IA111 Input Units with Ter- 200 to 240 V AC, 16 inputs, 50/60 Hz CS1W-IA211 minal Blocks...
Page 524 Appendix A Specifications of Basic I/O Units and High-density I/O Units Mixed I/O Units Category Name Specifications Model Page CS-series Basic I/O DC Input/Transistor 24 V DC inputs; CS1W-MD261 Units with Connec- Output Units 12 to 24 V DC, 0.3-A, sinking outputs; tors 32 inputs, 32 outputs 24 V DC inputs;...
Page 525 Appendix A Specifications of Basic I/O Units and High-density I/O Units Basic I/O Units Basic Input Units CS1W-IA111 100 V AC Input Unit (16 points) Rated Input Voltage 100 to 120 V AC, 50/60 Hz, 100 to 120 V DC Allowable Input Voltage 85 to 132 V AC (50/60 Hz), 85 to 132 V DC Range...
Page 526 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-IA211 200-V AC Input Unit (16 points) Rated Input Voltage 200 to 240 V AC, 50/60 Hz Allowable Input Voltage 170 to 264 V AC (50/60 Hz) Range Input Impedance 21 kΩ...
Page 527 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-ID211 24-V DC Input Unit (16 Points) Rated Input Voltage 24 V DC Allowable Input Voltage 20.4 to 26.4 V DC Range Input Impedance 3.3 kΩ Input Current 7 mA typical (at 24 V DC) ON Voltage/ON Current 14.4 V DC min./3 mA min.
Page 528 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-INT01 Interrupt Input Unit (16 Points) Rated Input Voltage 24 V DC Allowable Input Voltage 20.4 to 26.4 V DC Range Input Impedance 3.3 kΩ Input Current 7 mA typical (at 24 V DC) ON Voltage/ON Current 14.4 V DC min./3 mA min.
Page 529 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-IDP01 High-speed Input Unit (16 Points) Rated Input Voltage 24 V DC Allowable Input Voltage 20.4 to 26.4 V DC Range Input Impedance 3.3 kΩ Input Current 7 mA typical (at 24 V DC) ON Voltage/ON Current 14.4 V DC min./3 mA min.
Page 530 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-ID231 DC Input Unit (32 Points) Rated Input Voltage 24 V DC Allowable Input Voltage Range 20.4 to 26.4 V DC Input Impedance 3.9 kΩ Input Current 6 mA typical (at 24 V DC) ON Voltage/ON Current 15.4 V DC min./3 mA min.
Page 531 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-ID261 DC Input Unit (64 Points) Rated Input Voltage 24 V DC Allowable Input Voltage 20.4 to 26.4 V DC Range Input Impedance 3.9 kΩ Input Current 6 mA typical (at 24 V DC) ON Voltage/ON Current 15.4 V DC min./3 mA min.
Page 532 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-ID291 DC Input Unit (96 Points) Rated Input Voltage 24 V DC Allowable Input Voltage 20.4 to 26.4 V DC Range Input Impedance 4.7 kΩ Input Current Approx. 5 mA (at 24 V DC) ON Voltage/ON Current 17 V DC min./3 mA min.
Page 533 Appendix A Specifications of Basic I/O Units and High-density I/O Units Terminal Connections The polarity of the input power supply can be in either direction, as indicated by the dotted lines. COM2 COM3 COM1 COM4 COM0 COM5 Figure 1 Terminal Connections: CS1W-ID291 24-V DC 96-point Input Unit...
Page 534 Appendix A Specifications of Basic I/O Units and High-density I/O Units Basic Output Units CS1W-OC211 Contact Output Unit (16 points) Max. Switching Capacity 2 A 250 V AC (cosφ = 1), 2 A 24 V DC (8 A/common, 16 A/Unit), 0.1 A 120 V DC Min.
Page 535 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-OC201 Contact Output Unit (8 points) Max. Switching Capacity 2 A 250 V AC (cosφ = 1), 2 A 24 V DC (16 A/Unit), 0.1 A 120 V DC Min.
Page 536 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-OA211 Triac Output Unit (16 Points) Max. Switching Capacity 0.5 A 250 V AC, 50/60 Hz (2 A/common, 4 A/Unit) Max. Inrush Current 15 A (pulse width: 10 ms) Min.
Page 537 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-OA201 Triac Output Unit (8 Points) Max. Switching Capacity 1.2 A 250 V AC, 50/60 Hz (4.8 A/Unit) Max. Inrush Current 10 A (pulse width: 100 ms), 20 A (pulse width: 10 ms) Min.
Page 538 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-OD211 Transistor Output Unit (16 Points, Sinking) Rated Voltage 12 to 24 V DC Operating Load Voltage 10.2 to 26.4 V DC Range Maximum Load Current 0.5 A/point, 4.0 A/common, 8.0 A/Unit Maximum Inrush Current 4.0 A/point, 10 ms max.
Page 539 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-OD231 Transistor Output Unit (32 Points, Sinking) Rated Voltage 12 to 24 V DC Operating Load Voltage Range 10.2 to 26.4 V DC Maximum Load Current 0.5 A/point, 2.5 A/common, 5.0 A/Unit (See note.) Maximum Inrush Current 4.0 A/point, 10 ms max.
Page 540 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-OD261 Transistor Output Unit (64 Points, Sinking) Rated Voltage 12 to 24 V DC Operating Load Voltage 10.2 to 26.4 V DC Range Maximum Load Current 0.3 A/point, 1.6 A/common, 6.4 A/Unit Maximum Inrush Current 3.0 A/point, 10 ms max.
Page 541 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-OD291 Transistor Output Unit (96 Points, Sinking) Rated Voltage 12 to 24 V DC Operating Load Voltage 10.2 to 26.4 V DC Maximum Load Current 0.1 A/point, 1.2 A/common, 7.2 A/Unit (See note.) Maximum Inrush Current 1.0 A/point, 10 ms max.
Page 542 Appendix A Specifications of Basic I/O Units and High-density I/O Units 12 to 24 VDC COM2 12 to 24 VDC COM3 COM1 12 to 24 VDC 12 to 24 VDC COM4 COM0 12 to 24 VDC COM5 12 to 24 VDC Figure 2 Terminal Connections: CS1W-OD291 24-V DC 96-point Transistor Output Unit (Sinking Outputs)
Page 543 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-OD212 Transistor Output Unit (16 Points, Sourcing) Rated Voltage 24 V DC Operating Load Voltage 20.4 to 26.4 V DC Range Maximum Load Current 0.5 A/point, 2.5 A/common, 5.0 A/Unit Leakage Current 0.1 mA max.
Page 544 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-OD232 Transistor Output Unit (32 Points, Sourcing) Rated Voltage 24 V DC Operating Load Voltage 20.4 to 26.4 V DC Range Maximum Load Current 0.5 A/point, 2.5 A/common, 5.0 A/Unit (See note.) Leakage Current 0.1 mA max.
Page 545 Appendix A Specifications of Basic I/O Units and High-density I/O Units Circuit Configuration COM0 (+V) COM0 (+V) OUT00 OUT15 Output indicator COM1 (+V) COM1 (+V) OUT00 OUT15 ERR indicator When the output current of any output exceeds the detection current, the output for that point will turn OFF.
Page 546 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-OD262 Transistor Output Unit (64 Points, Sourcing) Rated Voltage 24 V DC Operating Load Voltage 20.4 to 26.4 V DC Range Maximum Load Current 0.3 A/point, 1.6 A/common, 6.4 A/Unit Leakage Current 0.1 mA max.
Page 547 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-OD292 Transistor Output Unit (96 Points, Sourcing) Rated Voltage 12 to 24 V DC Operating Load Voltage 10.2 to 26.4 V DC Range Maximum Load Current 0.1 A/point, 1.2 A/common, 7.2 A/Unit (See note.) Maximum Inrush Current 1.0 A/point, 10 ms max.
Page 548 Appendix A Specifications of Basic I/O Units and High-density I/O Units 12 to 24 VDC COM2 12 to 24 VDC COM3 COM1 12 to 24 VDC 12 to 24 VDC COM4 COM0 12 to 24 VDC COM5 12 to 24 VDC Figure 3 Terminal Connections: CS1W-OD292 24-V DC 96-point Transistor Output Unit (Sourcing Outputs)
Page 549 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-MD261 24-V DC Input/Transistor Output Unit (32/32 Points, Sinking) Output section (CN1) Input section (CN2) Rated Voltage 12 to 24 V DC Rated Input Voltage 24 V DC Operating Load Voltage 10.2 to 26.4 V DC Allowable Input Voltage 20.4 to 26.4 V DC...
Page 550 Appendix A Specifications of Basic I/O Units and High-density I/O Units Circuit Configuration Number of Simultaneously ON Points vs. Ambient OUT00 Temperature Characteristic OUT15 COM0 16 points at 34°C 16 points at 40°C COM0 (Outputs) Input voltage: 24 VDC OUT00 Input voltage: 26.4 VDC OUT15 I/O indicator...
Page 551 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-MD291 DC Input/Transistor Output Unit (48/48 Points, Sinking) Outputs (CN1) Inputs (CN2) Rated Voltage 12 to 24 V DC Rated Input Voltage 24 V DC Operating Load Voltage 10.2 to 26.4 V DC Allowable Input Voltage 20.4 to 26.4 V DC Range...
Page 552 Appendix A Specifications of Basic I/O Units and High-density I/O Units Note 1. The input ON and OFF response times for Basic I/O Units can be set to 0 ms, 0.5 ms, 1 ms, 2 ms, 4 ms, 8 ms, 16 ms, or 32 ms in the PLC Setup. The ON response time will be 120 µs maximum and OFF response time will be 300 µs maximum even if the response times are set to 0 ms due to internal element delays.
Page 553 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-MD262 24-V DC Input/Transistor Output Unit (32/32 Points, Sourcing) Output section (CN1) Input section (CN2) Rated Voltage 24 V DC Rated Input Voltage 24 V DC Operating Load Voltage 20.4 to 26.4 V DC Allowable Input Voltage 20.4 to 26.4 V DC...
Page 554 Appendix A Specifications of Basic I/O Units and High-density I/O Units Circuit Configuration Number of Simultaneously COM0 (+V) ON Points vs. Ambient COM0 (+V) Temperature Characteristic OUT00 OUT15 (Outputs) 32 points at 34°C 32 points at 40°C COM1 (+V) COM1 (+V) Input voltage: 24 VDC OUT00 OUT15...
Page 555 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-MD292 24-V DC Input/Transistor Output Unit (48/48 Points, Sourcing) Outputs (CN1) Inputs (CN2) Rated Voltage 12 to 24 V DC Rated Input Voltage 24 V DC Operating Load Voltage 10.2 to 26.4 V DC Allowable Input Voltage 20.4 to 26.4 V DC...
Page 556 Appendix A Specifications of Basic I/O Units and High-density I/O Units Note 1. The input ON and OFF response times for Basic I/O Units can be set to 0 ms, 0.5 ms, 1 ms, 2 ms, 4 ms, 8 ms, 16 ms, or 32 ms in the PLC Setup. The ON response time will be 120 µs maximum and OFF response time will be 300 µs maximum even if the response times are set to 0 ms due to internal element delays 2.
Page 557 Appendix A Specifications of Basic I/O Units and High-density I/O Units CS1W-MD561 TTL I/O Unit (32 Inputs, 32 Outputs) Outputs (CN1) Inputs (CN2) 5 V DC ±10% 5 V DC ±10% Rated Voltage Rated Input Volt- Operating Load Voltage 4.5 to 5.5 V DC Input Impedance 1.1 kΩ...
Page 558 Appendix A Specifications of Basic I/O Units and High-density I/O Units Note 1. The ON response time will be 120 µs maximum and OFF response time will be 300 µs maximum even if the response times are set to 0 ms due to internal element delays 2.
Page 559 Appendix A Specifications of Basic I/O Units and High-density I/O Units About Contact Output Units When used in the ways shown below, there may be differences in the life expectancies of the relays. • When using in excess of rated values •...
Page 560 Appendix A Specifications of Basic I/O Units and High-density I/O Units Arc killer circuit examples are listed in the following table. Circuit Current Characteristic Required element AC DC Using a CR Yes Yes If the load is a relay or solenoid, The capacitance of the capacitor must be 1 to 0.5 µF per contact cur- there is a time lag between the...
Page 561 Appendix A Specifications of Basic I/O Units and High-density I/O Units Load Short-circuit Protection CS1W-OD212/OD232/OD262/MD262 As shown below, normally when the output bit turns ON (OUT), the transistor will turn ON and then output cur- rent (Iout) will flow. If the output (Iout) is overloaded or short-circuited exceeding the detection current (Ilim), the output current (Iout) will be limited as shown in Figure 2 below.
Page 562 Appendix A Specifications of Basic I/O Units and High-density I/O Units Output bit 0 to 7 8 to 15 0 to 15 0 to 15 0 to 15 CS1W-OD232 Mounted in even slot Mounted in odd slot CS1W-OD262 Mounted in even slot Mounted in odd slot CS1W-MD262 Mounted in even slot...
Page 563 Appendix B Auxiliary Area Allocations The tables list the functions of Auxiliary Area words and bits in order of their addresses. For a list of Auxiliary Area words and bit by function, refer to SECTION 8 Memory Areas. The Auxiliary Area consists of read-only words A000 to A447 and read/write words A448 to A959. Read-only Words The following words and bits are written by the system to provide information on PLC operation.
Page 564 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status Timing Related after flags, Words Bits mode startup settings change A019 Previous Cause of Switching to Simplex Operation (Duplex CPU Systems only) A01900 Duplex ON: A duplex verification error caused the ON: Switched to Held Held...
Page 565 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status Timing Related after flags, Words Bits mode startup settings change A020 to Previous Cause of Switching to Simplex Operation (Duplex CPU Systems only) A022 Time of The time of the previous switch from Held Held Data from...
Page 566 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status Timing Related after flags, Words Bits mode startup settings change A023 A02308 Cycle ON: Exceeding the cycle time caused a ON: Switched to Held Held When A40108 Time switch from duplex to simplex operation. simplex opera- operation in CPU...
Page 567 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status Timing Related after flags, Words Bits mode startup settings change A034 A03400 Online ON: Online replacement is being per- ON: Online Held Cleared When A26110 Replace- formed for the slot that corresponds to the replacement online A03415...
Page 568 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status Timing Related after flags, Words Bits mode startup settings change A042 A04200 Duplex Duplex Communications Switch Cause Refer to the Held Cleared When A43600 Communi- Flag for Communication Unit with unit Operation Man- duplex A04207...
Page 569 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A050 A05000 Basic I/O A bit will turn ON to indicate when a ON: Fuse blown Every Unit Infor- fuse has blows.
Page 570 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A099 A09900 UM Read Indicates whether the entire user 0: UM not read- Retained Retained When pro- Protection program in the PLC is read-pro- protected.
Page 571 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A100 to Error Log When an error has occurred, the Error code Held Held When A50014 A199 Area error code, error contents, and Error contents: error...
Page 572 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A202 A20200 Communi- ON when a network instruction ON: Network Cleared cations (SEND, RECV, CMND, or PMCR) instruction is not A20207 Port can be executed with the corre-...
Page 573 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A214 A21400 First Cycle When a communications instruction ON for the first Held Cleared Flags after is executed with automatic port allo- cycle after com- A21407 Network...
Page 574 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A220 to A22000 Basic I/O These words contain the actual 0 to 17 hexadec- Held See func- A259 Unit Input input response times for CS-series imal...
Page 575 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A262 Maximum These words contain the maximum 0 to FFFFFFFF: Cycle cycle time since the start of PLC 0 to A263 Time...
Page 576 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change OFF → ON: A272 A27215 Online ON: An error occurred that pre- Cleared Cleared Each Addition vented a Backplane and Unit from cycle An error pre- Failed Flag...
Page 577 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A295 A29510 Illegal This flag and the Access Error Flag ON: Illegal Cleared Cleared A294, Access (AER) will be turned ON when an access occurred A298/ Error Flag...
Page 578 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A298 Program These words contain the 8-digit Right 4 digits of Cleared Cleared A294 Address binary program address of the the program Where instruction where program execution...
Page 579 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A310 Rightmost These words contain the production Held Held When Digits of lot number in 6 binary digits. power is Produc- turned ON...
Page 580 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A317 Duplex Verification Errors (Duplex CPU Systems only) (When A31600 turns ON, the cause of the error will be indicated here.) A31706 Other CPU ON: A duplex error occurred in the...
Page 581 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A319 Error Power Supply Unit Location When an error in a Power Supply Unit results in an error in the 5-V/26-V output, one of the following bits will turn ON to show the location of the Power Supply Unit with the error.
Page 582 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A322 CPU Standby Information A32203 CPU Bus/ ON: The CPU Unit is on standby ON: Standby Held Cleared When Special I/O waiting for CPU Bus or Special I/O...
Page 583 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A328 A32808 Duplex/ Indicates the current mode. ON: Duplex Held When Simplex OFF: Simplex power is A32808 is turned OFF in duplex ini- Mode Flag turned ON tialization and thus cannot be used...
Page 584 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A341 File Memory Information for Left CPU Unit (Duplex CPU Systems only) A34100 Memory Indicates the type of Memory Card, 0 hex: None Held When...
Page 585 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A342 File Memory Information for Right CPU Unit (Duplex CPU Systems only) A34200 Memory Indicates the type of Memory Card, 0 hex: None Held When...
Page 586 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A343 A34300 File Mem- Memory Card Type Flash A343 Held When ory Status The type of Memory power is A34302 Card mounted in the turned ON...
Page 587 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A343 A34309 File Mem- Cannot Write File Flag 1: Write not pos- Held Cleared When ory Status ON when data cannot be when sible writing a...
Page 588 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A343 A34313 File Mem- File Memory Operation ON: Instruction Held Cleared When file ory Status Flag when being executed. memory ON while any of the follow- A341...
Page 589 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A344 EM File Contains the starting bank number 0000 to 0018 Held Held When EM Memory of EM file memory (bank number of file for- Setup Starting...
Page 590 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A351 to Calendar/ These words contain the CPU Unit’s Held Held Written A354 Clock Area internal clock data in BCD. The clock every can be set from a Programming cycle...
Page 591 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A392 A39204 RS-232C ON when an error has occurred at ON: Error Held Cleared When A528 Port Error the RS-232C port.
Page 592 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A395 A39506 File ON when the system deleted the ON: File deleted Cleared Cleared When Deleted remainder of a Memory Card file OFF: No files system Flags...
Page 593 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A401 A40106 FALS ON when a non-fatal error is gener- ON: FALS(006) Cleared Cleared When A400 Error Flag ated by the FALS(006) instruction.
Page 594 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A401 A40111 Too Many ON when the number of I/O points ON: Error Cleared Cleared A407 I/O Points being used in Basic I/O Units OFF: No error Flag...
Page 595 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A402 A40202 Special I/O ON when an installed Special I/O ON: Setting error Cleared Cleared A428 to Unit Set- Unit does not match the Special I/O detected A433...
Page 596 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A402 A40208 Inner ON when an error occurs in a data ON: Error Cleared Cleared A424 Board exchange between the CPU Unit OFF: No error Error Flag and the Inner Board (including an...
Page 597 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A402 A40215 FAL Error ON when a non-fatal error is gener- ON: FALS(006) Cleared Cleared When A360 to Flag ated by executing FAL(006).
Page 598 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A405 A40515 Peripheral Turns ON when the peripheral ser- 1: Too long (Par- Cleared Cleared Written A268 Servicing vicing time in a Parallel Processing allel processing when...
Page 599 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A410 A41000 CPU Bus The Duplication Error Flag (A40113) ON: Duplication Cleared Cleared A40113 Unit Num- and the corresponding flag in A410 detected A41015 ber Dupli-...
Page 600 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A424 A42400 Inner When an error occurs in a data Cleared Cleared Board exchange between the CPU Unit A42415 Error Infor- and the Inner Board, the Inner Board...
Page 601 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A436 A43600 Duplex Active/Standby Communications ON: Duplex Held Cleared When A40214 Communi- Units Communica- communi- A31603 A43615 cations ON: An error was detected in self- tions Units cations...
Page 602 Appendix B Auxiliary Area Allocations Address Name Function Settings Status Status at Timing Related after startup flags, Words Bits mode settings change A441 Interrupt Contains the task number of the 8000 to 80FF Cleared Cleared See Func- Task With interrupt task with the maximum pro- tion col- hexadecimal Max.
Page 603 Appendix B Auxiliary Area Allocations Addresses Name Function Settings Status Status at Timing Related after startup Flags, Word mode Settings change A502 to A50200 Special I/ Turn these bits ON to restart (initialize) OFF to ON: Held Cleared A33000 to A507 O Unit the Special I/O Unit with the corre-...
Page 604 Appendix B Auxiliary Area Allocations Addresses Name Function Settings Status Status at Timing Related after startup Flags, Word mode Settings change A512 to A51200 Power These words contain the time at which See Function Held Held Written at A513 Interrup- the power was interrupted.
Page 605 Appendix B Auxiliary Area Allocations Addresses Name Function Settings Status Status at Timing Related after startup Flags, Word mode Settings change A526 A52600 RS-232C Turn this bit ON to restart the RS-232C OFF to ON: Held Cleared Port port. (Do not use this bit when the port Restart Restart is operating in peripheral bus mode.)
Page 606 OMRON FB Library to execute FINS messages or DeviceNet explicit messages communications. The values set in the Settings for OMRON FB Library in the PLC Setup will be automatically stored in the related Auxiliary Area words A580 to A582 and used by the...
Page 607 Appendix B Auxiliary Area Allocations Addresses Name Function Settings Status Status at Timing Related after startup Flags, Word mode Settings change A598 A59800 Turn this bit ON to set the monitoring ON: Teach Cleared Cleared Teaching time automatically with the teaching monitoring time function.
Page 608 Appendix B Auxiliary Area Allocations Addresses Name Function Settings Status Status at Timing Related after startup Flags, Word mode Settings change A620 A62001 Communi- The corresponding flag will be ON ON: Changing Held Cleared cations when the settings for that port are being OFF: Not Unit 0, changed.
Page 609 Appendix B Auxiliary Area Allocations Addresses Name Function Settings Status Status at Timing Related after startup Flags, Word mode Settings change A650 A65000 Program • Normal End (i.e., when A65014 is Retained Cleared Replace- OFF) A65007 ment End 01 hex: Program file (.OBJ) replaced. Code •...
Page 610 Appendix B Auxiliary Area Allocations Addresses Name Function Settings Status Status at Timing Related after startup Flags, Word mode Settings change A654 to Program When program replacement starts, the Held Cleared A657 File Name program file name will be stored in ASCII.
Page 611 Appendix B Auxiliary Area Allocations Addresses Name Function Settings Status Status at Timing Related after startup Flags, Word mode Settings change A732 to Power ON This is the history data at Startup Time. See at left Held Held When A734 Clock power is Data 5...
Page 612 Appendix B Auxiliary Area Allocations Addresses Name Function Settings Status Status at Timing Related after startup Flags, Word mode Settings change A747 to Power ON For the CPU@@SA, this is the history See at left Held Held When A749 Clock data at Startup Time.
Page 613 Appendix B Auxiliary Area Allocations Addresses Name Function Settings Status Status at Timing Related after startup Flags, Word mode Settings change A804 Details on The corresponding bit is turned ON ON: Mismatch Held Cleared When A31600, duplex when a duplex verification error duplex A317 OFF: Match...
Page 614 Appendix B Auxiliary Area Allocations Details on Auxiliary Area Operation A100 to A199: Error Log Area Error code A100 A101 Error flag contents Error A102 record A103 A104 A195 Error code A196 Error flag contents Error A197 record A198 A199 The following data would be generated in an error record if a memory error (error code 80F1) occurred on 1 April 2002 at 17:10:30 with the error located in the PLC Setup (0010 hex).
Page 615 Appendix B Auxiliary Area Allocations Error Codes and Error Flags Classification Error code Meaning Error flags System-defined fatal errors 80F1 Memory error (See note 1.) A403 80F0 Program error (See note 1.) A294 to 299 (See note 5.) 809F Cycle time overrun error (See note 1.) 82F0 Fatal Inner Board error (See notes 1 and A424...
Page 616 Appendix B Auxiliary Area Allocations Bit 06 to 07: Reserved Bit 08 to 15: rack number (BIN data): 0 to 7 A20011: First Cycle Flag Execution started. Time One cycle A20015: Initial Task Flag A20015 will turn ON during the first time a task is executed after it has reached executable status. It will be ON only while the task is being executed and will not turn ON if following cycles.
Page 617 Appendix B Auxiliary Area Allocations A300: Error Record Pointer 00 to 14 hex Error record 1 Points to the next record to be used. Example Stored Stored Stored Error record 20 next A20110: Online Editing Wait Flag Wait Online edit processing A20110 A50100 to A50115: CPU Bus Unit Restart Bits Automatically turned OFF by system...
Page 618 Appendix B Auxiliary Area Allocations A40109: Program Error Error Address UM Overflow Error Flag A29515 Illegal Instruction Flag A29514 Distribution Overflow Error Flag A29513 Task Error Flag A25912 No END(001) Error Flag A29511 Illegal Area Access Error Flag A29510 Indirect DM/EM Addressing Error Flag A29509...
Page 619 Appendix C Memory Map of PLC Memory Addresses PLC Memory Addresses PLC memory addresses are set in Index Registers (IR00 to IR15) to indirectly address I/O memory. Normally, use the MOVE TO REGISTER (MOVR(560)) and MOVE TIMER/COUNTER PV TO REGISTER (MOVRW(561)) instructions to set PLC memory addresses into the Index Registers.
Page 620 Appendix C Memory Map of PLC Memory Addresses Memory Map Do not access words that are reserved by the system. Classification PLC memory User addresses Area addresses (hex) Parameter 00000 to 0B0FF PLC Setup Area areas Registered I/O Table Area Routing Table Area CPU Bus Unit Setup Area Real I/O Table Area...
Page 621 Appendix D PLC Setup Coding Sheets for Programming Console Use the following coding sheets when setting the PLC Setup from a Programming Console. 10@@@@ Value (hex) Rack 0, Slot 0 I/O Response Time 8 ms No filter 0.5 ms 1 ms 2 ms 4 ms 8 ms...
Page 622 Appendix D PLC Setup Coding Sheets for Programming Console 11@@@@ Value (hex) Rack 0, Slot 2 I/O Response Time 8 ms No filter 0.5 ms 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms Value (hex) Rack 0, Slot 3 I/O Response Time 8 ms No filter 0.5 ms...
Page 623 Appendix D PLC Setup Coding Sheets for Programming Console 84@@@@ Value (hex) Inner Board Setting 8000 Don’t wait. 0000 Wait for all Boards. 95@@@@ Value (hex) Primary/Secondary Duplex Communications Unit Settings 0000 Not duplex for unit numbers 0 to 15. Bits 00 to 14 correspond to unit numbers 0 to 14.
Page 624 Appendix D PLC Setup Coding Sheets for Programming Console (Duplex CPU Systems only) 123@@@@ Value (hex) Operation during Duplex Automatic Recovery to Initialization Duplex Operation 0000 Don’t run during initialization. Don’t recover automatically. 4000 Run during initialization. Don’t recover automatically. 8000 Don’t run during initialization.
Page 625 Appendix D PLC Setup Coding Sheets for Programming Console 130@@@@ Value (hex) Memory Card Duplex Setting Disabled. Enable duplex check for Memory Card. (Duplex CPU Systems only) 131@@@@ Value (hex) Enabling Unit Removal without a Programming Device Any value Disabled. except 5AA5 5AA5 Enabled.
Page 626 Appendix D PLC Setup Coding Sheets for Programming Console 144@@@@ Peripheral Port Value (hex) Data bits Stop bits Parity 7 bits 2 bits Even 7 bits 2 bits 7 bits 2 bits None 7 bits 1 bit Even 7 bits 1 bit 7 bits 1 bit...
Page 627 Appendix D PLC Setup Coding Sheets for Programming Console @@@@ Peripheral Port Value (hex) Host link Unit No. 0000 No. 0 0001 No. 1 0002 No. 2 001F No. 31 150@@@@ Peripheral Port Value (hex) NT Link Mode Maximum Unit No. 0000 No.
Page 628 Appendix D PLC Setup Coding Sheets for Programming Console 161@@@@ RS-232C Port Value (hex) Baud rate 0000 9,600 bps 0001 300 bps 0002 600 bps 0003 1,200 bps 0004 2,400 bps 0005 4,800 bps 0006 9,600 bps 0007 19,200 bps 0008 38,400 bps 0009...
Page 629 Appendix D PLC Setup Coding Sheets for Programming Console 164@@@@ Value (hex) No-protocol Mode End Code Value (hex) No-protocol Mode Start Code 165@@@@ RS-232C Port Value (hex) No-protocol Mode reception data volume Value (hex) No-protocol Mode end code setting None (Specify the amount of data being received) Yes (Specify the end code) End code is set to CF+LF Value (hex)
Page 630 Appendix D PLC Setup Coding Sheets for Programming Console 197@@@@ Value (hex) Instruction Error Operation 0000 Continue operation 8000 Stop operation 198@@@@ Background Processing Settings (Single CPU Systems Only) Value (hex) Communications Port for Background Processing 0 to 7 Communications port 0 to 7 Value (hex) Background Processing 0 to E...
Page 631 Appendix D PLC Setup Coding Sheets for Programming Console 219@@@@ Value (hex) Time Slice Peripheral Servicing Time (See note.) Do not use Peripheral Servicing Priority Mode. 01 to FF Time Slice Peripheral Servicing Time (0.1 to 25.5 ms in 0.1-ms increments) Value (hex) Time Slice Instruction Execution Time (See note.) Do not use Peripheral Servicing Priority Mode.
Page 632 Appendix D PLC Setup Coding Sheets for Programming Console 221@@@@ Special Peripheral Servicing Unit Numbers (See note.) Value (hex) Special Peripheral Servicing Unit Number No special servicing 10 to 1F CPU Bus Units 0 to 15 (unit number + 10 hex) 20 to 7F Special I/O Units 0 to 95 (unit number + 20 hex) RS-232C port...
Page 633 Appendix D PLC Setup Coding Sheets for Programming Console 226@@@@ Value Special I/O Unit Cyclic Refreshing 0: Yes 1: No (hex) Unit number 0000 0001 0002 0003 0004 0005 FFFF Addresses 227 through 231 are the same as 226. 448@@@@ Use FINS Write Protection and Number of Node Excluded from Write Protection Value (hex)
Page 634 Appendix D PLC Setup Coding Sheets for Programming Console...
Page 635 Appendix E Precautions in Replacing CS1-H PLCs with CS1D PLCs Observe the following precautions when replacing a CS1-H system (see note) with a CS1D system, and make sure the new system is suitable for the application conditions. Note The information in the following table is based on CS1-H CPU Unit Ver. 4.1. Refer to the CS Series PLC Operation Manual (W339) for differences between unit versions.
Page 636 Appendix E Precautions in Replacing CS1-H PLCs with CS1D PLCs Item Duplex CPU Systems Single CPU Systems CS1-H (See note.) Perfor- System overhead 1.9 ms 0.5 ms (normal mode) 0.3 ms (normal mance time 0.4 ms (Parallel Processing Mode) mode on CS1-H) 0.2 ms (Parallel Processing Mode on the CS1-H)
Page 637 Appendix E Precautions in Replacing CS1-H PLCs with CS1D PLCs Item Duplex CPU Systems Single CPU Systems CS1-H (See note.) I/O pro- Number of slots for • Duplex CPU, Dual I/O 71 slots, 8 on CPU Rack and 9 each 80 slots, 10 on CPU cessing 1 CPU Rack and 7...
Page 638 Appendix E Precautions in Replacing CS1-H PLCs with CS1D PLCs Item Duplex CPU Systems Single CPU Systems CS1-H (See note.) Instruc- ER Flag operation The ER Flag will turn ON if (No precautions in converting from tions the active and standby CPU the CS1-H.) Units cannot be synchronized tasks,...
Page 639 Appendix E Precautions in Replacing CS1-H PLCs with CS1D PLCs Item Duplex CPU Systems Single CPU Systems CS1-H (See note.) Instruc- Expansion data Not supported. No precautions in converting from Supported. tions comparison the CS1-H. instruction: tasks, BCMP2 contd Gray scale conver- Not supported.
Page 640 Appendix E Precautions in Replacing CS1-H PLCs with CS1D PLCs Item Duplex CPU Systems Single CPU Systems CS1-H (See note.) Pro- CX-Programmer Supported from CX-Program- Supported from CX-Programmer Supported from CX- gram- restrictions mer version 3.1. version 4.0. CX-Programmer Version Programmer ver- ming 3.@ or lower cannot be used.
Page 641 Appendix E Precautions in Replacing CS1-H PLCs with CS1D PLCs Item Duplex CPU Systems Single CPU Systems CS1-H (See note.) Serial Built-in RS-232C A DIP switch pin on the No precautions in converting from A DIP switch pin on commu- port Duplex Unit is used to switch the CS1-H.
Page 642 Appendix E Precautions in Replacing CS1-H PLCs with CS1D PLCs Item Duplex CPU Systems Single CPU Systems CS1-H (See note.) File Automatic transfer Must be performed on the No precautions in converting from mem- at startup active CPU Unit. The results the CS1-H.
Page 643 Appendix F Connecting to the RS-232C Port on the CPU Unit Connection Examples The wiring diagrams for connecting to the RS-232C port are provided in this appendix. In actual wiring, we rec- ommend the use of shielded twisted-pair cables and other methods to improve noise resistance. Refer to Rec- ommended Wiring Methods later in this appendix for recommended wiring methods.
Page 644 Appendix F Connecting to the RS-232C Port on the CPU Unit Duplex Connections to Standby and Active CPU Units for Continuous Communications when Switching to Simplex Operation with Duplex CPU Systems RS-232C RS-422A/485 CJ1W-CIF11 Adapters are connected to both CPU Units. NT-AL001 (See note 2.) terminating...
Page 645 Appendix F Connecting to the RS-232C Port on the CPU Unit 1:N Connections via RS-232C Port Connecting to One CPU Unit RS-232C RS-422A/485 NT-AL001 NT-AL001 terminating RS-232C RS-232C RS-232C resistance ON, 5-V power required RS-232C ports on active CPU Units. NT-AL001 Link Adapter NT-AL001 Link Adapter Personal Computer...
Page 646 Appendix F Connecting to the RS-232C Port on the CPU Unit • Wiring with XW2Z-@@0T-1 (10 Conductors) CPU Unit NT-AL001 Arrows indicate Signal Signal signal directions name name Returned Returned Shell Shell Shield Note 1. Do not use the 5-V power from pin 6 of the RS-232C port for anything but the NT-AL001/CJ1W-CIF11 Link Adapter, or NV3W-M@20L Programmable Terminal.
Page 647 Appendix F Connecting to the RS-232C Port on the CPU Unit Connection Example to Programmable Terminal (PT) Direct Connection from RS-232C to RS-232C Duplex Connections to Standby and Active CPU Units for Continuous Communications when Switching to Simplex Operation NS-series PT NS-AL002 RS-422A/485 CJ1W-CIF11 Adapters are...
Page 648 Appendix F Connecting to the RS-232C Port on the CPU Unit Recommended Wiring Methods We recommend the following wiring methods for RS-232C, especially in environment prone to noise. 1. Use shielded twisted-pair cable for communications cables. The following RS-232C cables are recommend- Model Manufacturer UL2464 AWG28×5P IFS-RVV-SB (UL approved)
Page 649 Appendix F Connecting to the RS-232C Port on the CPU Unit Wiring Connectors Use the following procedures to wire connectors. Preparing the Cable Lengths for steps in the procedure are provided in the diagrams. Connecting the Shield Line to the Hood (FG) 1.
Page 650 Appendix F Connecting to the RS-232C Port on the CPU Unit Electrician's tape Soldering 1. Place heat-shrinking tubes over all wires. 2. Pre-solder all wires and connector terminals. 3. Solder the wires. 1 mm Soldering iron Heat-shrinking tube (inner dia. 1.5, l = 10) 4.
Page 651 Appendix F Connecting to the RS-232C Port on the CPU Unit Connections to the CPU Unit Tighten the screws firmly. • Always turn OFF the power supply to the PLC before connecting or disconnecting communications cables. • Tighten the communications connector attachment screws to 0.4 N⋅m.
Page 652 Appendix F Connecting to the RS-232C Port on the CPU Unit...
Page 653 Appendix G CJ1W-CIF11 RS-422A Converter The CJ1W-CIF11 RS-422A Converter converts RS-232C to RS-422A/485. Specifications General Specifications Item Specifications 18.2 × 34.0 × 38.8 mm (W × H × D) Dimensions Weight 20 g max. Ambient operating temperature 0 to 55°C −29 to 75°C Ambient storage temperature Ambient operation humidity...
Page 654 Appendix G CJ1W-CIF11 RS-422A Converter RS-422A/485 Terminal Block Signal name RDA− RDB+ SDA− SDB+ DIP Switch Settings Function number Terminating resistance With (at both ends of the commu- Without nications path) Two-wire/four-wire method selec- Two-wire method Four-wire method tion (See note 1.) Two-wire/four-wire method selec- Two-wire method Four-wire method...
Page 655 Appendix G CJ1W-CIF11 RS-422A Converter Note Press the cover gently while removing it to prevent it from popping out suddenly. 2. Using a fine pair of tweezers or other tool with a fine point, change the settings of the DIP switch pins to match the desired communications conditions.
Page 656 Appendix G CJ1W-CIF11 RS-422A Converter 3. Strip the sheath off the signal wires to a length sufficient to attach crimp terminals. Apply vinyl tape or heat- shrinking tube to the sheathes and stripped parts of communications lines. 4. Attach ferrules to ends of the signal lines and crimp them using a crimp tool. •...
Page 657 Appendix G CJ1W-CIF11 RS-422A Converter Mounting to the Unit Mount the Converter to the RS-232C port (D-Sub, 9-pin) of the Unit to be connected in the following way. 1. Align the Converter’s connector with that of the Unit and push it into the Unit’s connector as far as possible. 2.
Page 658 Appendix G CJ1W-CIF11 RS-422A Converter Wiring for Two-wire Cable CS1D CPU Unit CS1D CPU Unit CS1D CPU Unit (slave 1) (master) (slave 0) DIP Switch Settings ON (with) ON (with) OFF (without) Terminating resistance ON (two-wire) ON (two-wire) ON (two-wire) Two-wire/four-wire ON (two-wire) ON (two-wire)
Page 659 Appendix H Method of Switching the Operation of a Duplex System by a Program Intentionally Creating Errors to Switch Operation With a Duplex CPU System, a hot standby method is used, which means that the standby CPU Unit executes the same program as the active CPU Unit. Thus, if FALS(007) is executed with the same conditions on both the CPU Units, FALS(007) will be executed at the same time in both CPU Units and operation will not switch to the standby, causing the CPU STATUS indicators on the Duplex Unit to flash red for both CPU Units.
Page 660 Appendix H Method of Switching the Operation of a Duplex System by a Program...
Page 661 Appendix I Method of specifing the EM Bank from the Program Console The procedure for specifying the EM Bank from the program console is as follows. • Specify from EM 0 to 9 (Hex) Bank No. Address EM_/EXT • Specify from EM A to F (Hex) Bank No.
Page 662 Appendix I Method of specifing the EM Bank from the Program Console...
Page 663 Index A39512 setting on DIP switch, 53 C200H Racks, 39 Access Error Flag, 334 C200H Units, 102 ACT RIGHT/ACT LEFT switch, 52 cables, 168 See also I/O Connecting Cables ACT. LEFT switch, 52 Carry Flag, 334 ACT. RIGHT switch, 52 CIO Area, 264 Active CPU Unit, 121 description, 270...
Page 664 Index settings, 339 data movement instructions execution times, 380 CPU operating switches, 51 Data Registers, 331 CPU Racks troubleshooting, 437 data registers sharing, 269, 304, 332 CPU standby error, 417 data tracing CPU STATUS indicator, 56, 57 related flags/bits, 305 CPU Unit debugging, 156 initialization, 347...
Page 665 Index specifications, 22 duplex operation, 414 startup processing, 122 error codes, 552, 575 status, 291 error log, 306, 574 systems, 120 error messages, 417 Unit replacement, 453 Expansion I/O Rack, 437 user program execution, 123 FAL/FALS flags, 307 flags, 334 Duplex Optical Controller Link Units, 123 flash memory, 307, 557 Duplex Power Supply Units, 123, 136...
Page 666 Index flowchart input bits and words, 272 environmental conditions check, 435 output bits and words, 274 I/O check, 436 index registers, 325 overall CPU operation, 343, 344 sharing, 269, 304 PLC cycle, 356 indirect addressing Forced Status Hold Bit, 562 DM Area, 322, 324 fuses EM Area, 324...
Page 667 Index interrupt tasks error information, 308 Negative Flag, 334 interrupts, 26, 104, 130 Power OFF Interrupt Task, 209 networks response time, 371, 372 related flags/bits, 313, 314, 315 IOM Hold Bit, 562 noise reducing electrical noise, 195 IORF(097) refreshing input bits and words, 273 Not Equal Flag, 334 output bits and words, 275 IR/DR Operation between Tasks, 304...
Page 668 Index peripheral port Program Error Flag, 553 related flags/bits, 315, 551 program errors, 578 peripheral servicing, 346 PROGRAM mode, 350 duplex operation, 123 Programmable Terminals setting, 220, 221, 222 RS-232C connection example, 607 Peripheral Servicing Priority Mode, 26 programming, 143, 153 Peripheral Servicing Too Long Flag, 311 error flag, 553 personal computer...
Page 669 Index recommended wiring methods, 608 related flags/bits, 316, 551 settings, 211 Task Error Flag, 537 RS-422A Converter, 613 Task Flags, 332 RSV setting on DIP switch, 53 Task Started Flag, 303 RUN mode, 350 tasks related flags/bits, 304 RUN output, 178 Task Flags, 332 terminal blocks, 186 Terminator, 101...
Page 670 Index...
Page 671 Revision History A manual revision code appears as a suffix to the catalog number on the front cover of the manual. Cat. No. W405-E1-16 Revision code The following table outlines the changes made to the manual during each revision. Page numbers refer to the previous version.
Page 672 Revision History Revision code Date Revised content June 2003 “CS1D-PA207R Power Supply Unit” was globally changed to “CS1D-PA/PD Power Supply Unit.” Page 7: CS1D-PD024 Power Supply Unit information added to table. Page 22: CS1D-PD024 Power Supply Unit information added to table. Page 23: CS1D-PD024 Power Supply Unit information added as Note number 4.
Page 673 Revision History Revision code Date Revised content January 2008 Page ix: Added references to notes in middle of table. Page x: Changed note 3 and added note 4. Page xi: Deleted Note 1 deleted. Page 7: Removed “L” from beginning of model number in bottom table. Page 18: Added model numbers and unit version in bottom middle cell of table.
Page 674 Revision History...
Page 676 Hoffman Estates, IL 60169 U.S.A. Tel: (31) 2356-81-300 Fax: (31) 2356-81-388 Tel: (1) 847-843-7900 Fax: (1) 847-843-7787 ©OMRON Corporation 2002-2024 All Rights Reserved. OMRON ASIA PACIFIC PTE. LTD. OMRON (CHINA) CO., LTD. In the interest of product improvement, 438B Alexandra Road, #08-01/02 Alexandra Room 2211, Bank of China Tower, specifications are subject to change without notice.

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