5.5.26 Gpmc_Ecc_Control; Gpmc_Ecc_Control Field Descriptions - Texas Instruments TMS320C6A816 Series Technical Reference Manual

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5.5.26 GPMC_ECC_CONTROL

31
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-9 Reserved
8 ECCCLEAR
7-4 Reserved
3-0 ECCPOINTER
SPRUGX9 – 15 April 2011
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Preliminary
Figure 5-76. GPMC_ECC_CONTROL
9 8
ECCCLEAR
R/W-0
Table 5-81. GPMC_ECC_CONTROL Field Descriptions
Value Description
0 Reserved
Clear all ECC result registers
R0 All reads return 0
W0 Ignored
W1 Clears all ECC result registers
0 Reserved
0-Fh Selects ECC result register (Reads to this field give the dynamic position of the ECC pointer -
Writes to this field select the ECC result register where the first ECC computation will be stored).
Writing values not listed disables the ECC engine (ECCEnable bit of GPMC_ECC_CONFIG cleared
to 0).
0 Writing 0 disables the ECC engine (ECCENABLE bit of GPMC_ECC_CONFIG cleared to 0)
1h ECC result register 1 selected
2h ECC result register 2 selected
3h ECC result register 3 selected
4h ECC result register 4 selected
5h ECC result register 5 selected
6h ECC result register 6 selected
7h ECC result register 7 selected
8h ECC result register 8 selected
9h ECC result register 9 selected
© 2011, Texas Instruments Incorporated
Reserved
R-0
7
Reserved
R-0
General-Purpose Memory Controller (GPMC)
Registers
4 3
ECCPOINTER
R/W-0
16
0
689