Port Descriptions - Xilinx LogiCORE IP AXI Product Manual

Table 2-2: Resource Utilization Summary
Configuration
Endpoint x1 Gen1
Endpoint x2 Gen1
Endpoint x4 Gen1
Endpoint x8 Gen1
Endpoint x1 Gen2
Endpoint x2 Gen2
Endpoint x4 Gen2
Root Port x1 Gen1
Root Port x2 Gen1
Root Port x4 Gen1
Root Port x8 Gen1
Root Port x1 Gen2
Root Port x2 Gen2
Root Port x4 Gen2

Port Descriptions

The interface signals for the AXI Bridge for PCI Express are described in
Table 2-3: Top-Level Interface Signals
Signal Name
refclk
axi_aresetn
axi_aclk_out
axi_ctl_aclk_out
mmcm_lock
interrupt_out
s_axi_awid[c_s_axi_id_width-1:0]
s_axi_awaddr[c_s_axi_addr_width-1:0]
s_axi_awregion[3:0]
s_axi_awlen[7:0]
s_axi_awsize[2:0]
AXI Bridge for PCI Express v2.4
PG055 June 4, 2014
Slice Registers Slice LUTs
8678 13054
8963 13300
9558 13666
11912 17355
8620 14041
8897 14362
10629 16477
10703 15909
10836 15537
11431 15924
13805 20128
10674 16734
11062 17137
12563 19325
I/O Description
Global Signals
I PCIe Reference Clock
I Global reset signal for AXI Interfaces
O PCIe derived clock output for axi_aclk
O PCIe derived clock output for axi_ctl_aclk
O axi_aclk_out from the axi_enhanced_pcie block is stable
O Interrupt signal
AXI Slave Interface
I Slave write address ID
I Slave address write
I Slave write region decode
I Slave write burst length
I Slave write burst size
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Chapter 2: Product Specification
Table 2-3.
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