Setting Example; Psvd Setting Example - Panasonic MN101L Series User Manual

6.3 Setting Example

6.3.1

PSVD Setting Example

Mode Transition Operation with PSVD
The following procedure shows that CPU transits from STOP to NORMAL mode when VDD30 exceeds 2.0 V.
Setup Procedure
(1) Disable all maskable interrupts.
PSW
bp6: MIE = 0
(2) Set the detection voltage
LVICTR0 (0x03F66)
bp4 to 0: LV4 to LV0 = 01100
(3) Enable power supply detection function
LVICTR1 (0x03F67)
bp0: LVION = 1
(4) Wait for power supply voltage detection
function activation
wait 1.5 ms
(5) Clear the interrupt request bit
PERI1DT (0x03FDF)
(6) Set the interrupt level
PERI1ICR (0x03FFE)
bp7 to 6: PERI1LV1 to 0
PSW
bp5 to 4: IM1 to IM0
(7) Enable interrupt
PERI1EN (0x03FDE)
bp0: PERI1EN0 = 1
(8) Enable all maskable interrupts
PSW
bp6: MIE = 1
(9) Check power supply voltage
LVICTR1 (0x03F76)
bp1: LVIOUT = 0?
(1) Clear the MIE bit of PSW to disable all maskable
interrupts. To change the interrupt control registers, this
step must be performed.
(2) Set the LV4 to 0 bits of LVICTR0 to "01100" to set the
level of power supply voltage detection to 2.0 V.
(3) Set the LVION bit of LVICTR1 to "1" to enable the power
supply voltage detection function.
(4) Wait for the power supply voltage function activation
time (1.5 ms) or more.
(5) Clear the interrupt request bits by reading PERI1DT and
writing the read value to PERI1DT.
Refer to [3.1.4 Group Interrupt Control Register Setup].
(6) Set the interrupt level by the PERI1LV1 to 0 bits of
PERI1ICR. If the interrupt mask level of PSW needs to
change, set the IM1 to IM0 bits of PSW.
(7) Set the PERI1EN0 bit of PERI1EN to enable interrupt.
(8) Set the MIE bit of PSW to enable maskable interrupts.
(9) Monitor the LVIOUT bit of LVICTR1 periodically.
Power Supply Voltage Detection
Description
Setting Example
Chapter 6
VI - 7