Panasonic MN101L Series User Manual page 437

Setting of Transfer Clock (SCnCLK)
SCIFn operates with SCnCLK which is generated based on BRTM output clock (BRTM_SCnCLK).
Regardless of the setting value of SCnMD1.SCnCKM, SCnCLK is as follows:
When SCnMD1.SCnDIV is "0", SCnCLK is generated by dividing BRTM_SCnCLK by 8.
When SCnMD1.SCnDIV is "1", SCnCLK is generated by dividing BRTM_SCnCLK by 16.
Generating Baud Rate Timer Output Clock (BRTM_SCnCLK)
This is a common feature with the Clock-Synchronous communication. For more information, refer to XIII-30.
Transmission Data Buffer (TXBUFn) and Transmission Buffer Empty Flag (SCnTEMP)
This is a common feature with the Clock-Synchronous communication. For more information, refer to XIII-35.
Write data to TXBUFn only when SCnSTR.SCnTEMP is "0".
If data is written to TXBUFn while SCnTEMP is "1", SCIFn does not work properly.
.. ..
As in the Clock-Synchronous communication, a wait time (T
to the first data transmission is the period of 3.5 transfer clocks.
(A start bit is transmitted after 2.5 transfer clocks after a data is written to TXBUFn.)
..
..
Reception Data Buffer (RXBUFn) and of Reception Buffer Empty Flag (SCnREMP)
This is a common feature with the Clock-Synchronous communication. For more information, refer to XIII-35.
Activation Source for Communication
Data write to TXBUFn is the trigger to start data transmission.
In data reception, a communication starts with a detection of start bit. "Low" level input time of 0.5 transfer clock
or more is required for a detection of start bit.
Interrupt
In data transmission, transmission complete interrupt (SCnTIRQ) occurs every 1-frame transmission completion.
In data reception, reception complete interrupt (SCnRIRQ) occurs every 1-frame reception completion.
) from a data write to TXBUFn
wait
Full-duplex UART Communication
Chapter 13
Serial Interface
XIII - 49