Panasonic MN101L Series User Manual page 549

MN101L SERIES INSTRUCTION SET
Group Mnemonic
→ Dm
NOT NOT Dn ~Dn
ASR ASR Dn Dn.msb
Dn >> 1 → Dn, temp → Dn.msb
LSR LSR Dn Dn.lsb
0 → Dn.msb
ROR ROR Dn Dn.lsb
CF → Dn.msb, temp → CF
Bit manipulation Instructions
BSET BSET (io8)bp mem8(IOTOP+io8) & bpdata...PSW
→ mem8(IOTOP+io8)bp
1
BSET (abs8)bp
mem8(abs8) & bpdata...PSW
→ mem8(abs8)bp
1
BSET (abs16)bp
mem8(abs16) & bpdata...PSW
→ mem8(abs16)bp
1
BCLR BCLR (io8)bp mem8(IOTOP+io8) & bpdata...PSW
→ mem8(IOTOP+io8)bp
0
BCLR (abs8)bp
mem8(abs8) & bpdata...PSW
→ mem8(abs8)bp
0
BCLR (abs16)bp
mem8(abs16) & bpdata...PSW
→ mem8(abs16)bp
0
BTST BTST imm8, Dm Dm & imm8...PSW
BTST (abs8)bp mem8(abs16) & bpdata...PSW
Branch Instructions
if(ZF=1), PC+3+d4(label)+H → PC
Bcc BEQ label
if(ZF=0), PC+3 → PC
if(ZF=1), PC+4+d7(label)+H → PC
BEQ label
if(ZF=0), PC+4 → PC
if(ZF=1), PC+5+d11(label)+H → PC
BEQ label
if(ZF=0), PC+5 → PC
if(ZF=0), PC+3+d4(label)+H → PC
BNE label
if(ZF=1), PC+3 → PC
if(ZF=0), PC+4+d7(label)+H → PC
BNE label
if(ZF=1), PC+4 → PC
if(ZF=0), PC+5+d11(label)+H → PC
BNE label
if(ZF=1), PC+5 → PC
if((VF^NF)=0), PC+4+d7(label)+H → PC
BGE label
if((VF^NF)=1), PC+4 → PC
if((VF^NF)=0), PC+5+d11(label)+H → PC
BGE label
if((VF^NF)=1), PC+5 → PC
if(CF=0), PC+4+d7(label)+H → PC
BCC label
if(CF=1), PC+4 → PC
if(CF=0), PC+5+d11(label)+H → PC
BCC label
if(CF=1), PC+5 → PC
if(CF=1), PC+4+d7(label)+H → PC
BCS label
if(CF=0), PC+4 → PC
if(CF=1), PC+5+d11(label)+H → PC
BCS label
if(CF=0), PC+5 → PC
if((VF^NF)=1), PC+4+d7(label)+H → PC
BLT label
if((VF^NF)=0), PC+4 → PC
if((VF^NF)=1), PC+5+d11(label)+H → PC
BLT label
if((VF^NF)=0), PC+5 → PC
BLE label
if((VF^NF) | ZF=1),
PC+4+d7(label)+H → PC
if((VF^NF) | ZF=0),
PC+4 → PC
BLE label
if((VF^NF) | ZF=1),
PC+5+d11(label)+H → PC
if((VF^NF) | ZF=0),
PC+5 → PC
BGT label
if((VF^NF) | ZF=0),
PC+4+d7(label)+H → PC
if((VF^NF) | ZF=1),
PC+4 → PC
BGT label
if((VF^NF) | ZF=0),
PC+5+d11(label)+H → PC
if((VF^NF) | ZF=1),
PC+5 → PC
Flag Code
Operation
VF NF CF ZF Size
0 0 3
→ temp, Dn.lsb → CF
0 3
→ CF , Dn >> 1 → Dn
0 0 3
→ temp, Dn >> 1 → Dn
0 3
0 0 5
0 0 4
0 0 7
0 0 5
0 0 4
0 0 7
0 0 5
0 0 7
- - - - 3
- - - - 4
- - - - 5
- - - - 3
- - - - 4
- - - - 5
- - - - 4
- - - - 5
- - - - 4
- - - - 5
- - - - 4
- - - - 5
- - - - 4
- - - - 5
- - - - 4
- - - - 5
- - - - 5
- - - - 6
Execution
REP
Cycle Ext. 1 2 3
1 0010 0010 10Dn
1 0010 0011 10Dn
1 0010 0011 11Dn
1 0010 0010 11Dn
2+2d 0011 1000 0bp. <io8
2+2d 1011 0bp. <abs
2+2d 0011 1100 0bp. <abs
2+2d 0011 1000 1bp. <io8
2+2d 1011 1bp. <abs
2+2d 0011 1100 1bp. <abs
1 0010 0000 11Dm <#8.
2+d 0011 1101 0bp. <abs
000H
1/3+i 1001 <d4>
1/3+i 1000 1010 <d7.
1/3+i 1001 1010 <d11
1/3+i 1001 001H <d4>
1/3+i 1000 1011 <d7.
1/3+i 1001 1011 <d11
1/3+i 1000 1000 <d7.
1/3+i 1001 1000 <d11
1/3+i 1000 1100 <d7.
1/3+i 1001 1100 <d11
1/3+i 1000 1101 <d7.
1/3+i 1001 1101 <d11
1/3+i 1000 1110 <d7.
1/3+i 1001 1110 <d11
1/3+i 1000 1111 <d7.
1/3+i 1001 1111 <d11
1/3+i 0010 0010 0001 <d7.
1/3+i 0010 0011 0001 <d11
*1 d4 sign-extention
*2 d7 sign-extention
*3 d11 sign-extention
*4 not taken / taken
Machine Code
4 5 6 7 8 9 10
...>
8..>
16.. .... ...>
...>
8..>
16.. .... ...>
...>
16.. .... ...>
...H
.... ...H
...H
.... ...H
...H
.... ...H
...H
.... ...H
...H
.... ...H
...H
.... ...H
...H
.... ...H
...H
.... ...H
Instruction set
Chapter 20
Appendix
Notes
11
*1 *4
*2 *4
*3 *4
*1 *4
*2 *4
*3 *4
*2 *4
*3 *4
*2 *4
*3 *4
*2 *4
*3 *4
*2 *4
*3 *4
*2 *4
*3 *4
*2 *4
*3 *4
XX - 7