Panasonic MN101L Series User Manual page 466

Chapter 14
DMA Controller
DMA Control Register 1 upper side (DMCTR1H: 0x03E03)
bp
Bit name
At reset
Access
bp Bit name
7-5
4 DMOVF
3-1
0 DMRQF
XIV - 8 DMA Controller Control Registers
7 6
- -
0 0
R R
- Always read as "0".
DMA-Error detection
When the DMA-Error occurs, the DMOVF is set to "1".
The DMOVF is cleared to "0" by writing DMCTR1L.DMTEN.
0: Not Detect
1: Detect
- Always read as "0".
DMA Busy monitor
The DMRQF is set to "1" when the DMA start trigger occurs.
In the case of the single transfer, the DMRQF is cleared to "0" at the end of single data transfer.
In the case of the burst transfer, the DMRQF is cleared to "0" at the end of the last burst data transfer.
0: Not Busy
1: Busy
5 4
- DMOVF
0 0
R R
Description
3 2
- -
0 0
R R
1 0
- DMRQF
0 0
R R