Panasonic MN101L Series User Manual page 428

Lsi
Table of Contents

Advertisement

Chapter 13
Serial Interface
Reception Timing
SBTn
SBOn/SBIn
SCnRBSY
(Set data to
Communication
completion interrupt
SBTn
SBOn/SBIn
SCnRBSY
(Set data to
Communication
completion interrupt
XIII - 40
Clock-Synchronous Communication
Twait
(=3.5T)
)
TXBUFn
Figure:13.3.13 Reception Timing (At Rising Edge, SCnCKPH bit = 0)
Twait
T
(=3.5T)
1st
Bit
)
TXBUFn
Figure:13.3.14 Reception Timing (At Falling Edge, SCnCKPH bit = 0)
T
1st
2nd
3rd
4th
Bit
Bit
Bit
Bit
2nd
3rd
4th
Bit
Bit
Bit
Writing period to TXBUFn
(when consecutive communication mode)
5th
6th
7th
Bit
Bit
Bit
Writing period to TXBUFn
(when consecutive communication mode)
5th
6th
7th
Bit
Bit
Bit
8th
Bit
8th
Bit

Hide quick links:

Advertisement

Table of Contents
loading

This manual is also suitable for:

Mn101lr05dMn101lr04dMn101lr03dMn101lr02d

Table of Contents