Panasonic MN101L Series User Manual page 319

Count Timing of High-Precision PWM Output
(when compare register 2 is set to "compare register 1" - 1)
Count
clock
TMnEN
bit
Compare
register 1
Compare
register 2
Binary
0000 0001
counter
TMnIO output
(PWM output)
Figure:9.7.3 Count Timing of High-Precision PWM Output (When TMnOC2 is set to TMnOC1 - 1)
When outputting the high-precision PWM, set the TMnMD2.TMnBCR to "1" to select
TMnOC1 compare match as the binary counter clear source and the PWM set source (to
"High" state).
..
Also, set the TMnMD2.TnPWMSL to "1" to select TMnOC2 compare match as the PWM
reset source (to "Low" state).
..
The PWM output at the initial state is "Low". It changes to "High" at the time the PWM opera-
tion is selected by setting the TMnMD2.TMnPWM.
.. ..
When outputting the high-precision PWM, set the values of TMnOC1 and 2 as follow:
TMnOC2 < TMnOC1
If TMnOC2 ≥ TMnOC1, the PWM output is fixed to "High".
..
..
N
N-1
N-1 N
16-bit High-Precision PWM Output (with Continuously Variable Period/Duty)
0000 0001
Chapter 9
16-bit Timer
IX - 37