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Chapter 3
Interrupts
NMI Processing
Figure:3.1.8 shows the processing sequence of NMI.
(
(
III - 14
Overview
Main Program
PSW.IM1-0="11"
NMI 1 occurs
)
IM1-0="00"
Interrupt acceptance cycle
*2
)
IM1-0="00"
Interrupt acceptance cycle
*1 :
The multiple interrupts are not accepted during NMI handler.
After RTI instruction, NMI 2 is accepted.
If the undefined instruction occurs, the following processing is not guaranteed.
*2 :
If the request of NMI 1 is not cleared, NMI 1 is accepted again after RTI instruction.
Figure:3.1.8 Processing Sequence for Non-Maskable Interrupt
NMI handler: 1
NMI 2 occurs
*1
RTI
NMI handler: 2
RTI
Parentheses () indicates hardware processing.
(
)
IM1-0="11"
(
)
IM1-0="11"
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