Page 1 MICROCOMPUTER MN101C MN101C77C/F77G LSI User’s Manual Pub.No.21477-011E...
Page 3 PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names, logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations. Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the "Foreign Exchange and Foreign...
Page 4: Overview
About This Manual Organization In this LSI manual, this LSI functions are presented in the following order : overview, basic CPU functions, interrupt functions, port functions, timer functions, serial functions, and other peripheral hardware functions. Each section contains overview of function, block diagram, control register, operation, and setting example. Manual Configuration Each section of this manual consists of a title, summary, main text, key information, precautions and warnings, and references.
Page 5 Finding Desired Information This manual provides three methods for finding desired information quickly and easily. (1) Consult the index at the front of the manual to locate the beginning of each section. (2) Consult the table of contents at the front of the manual to locate desired titles. (3) Chapter names are located at the top outer corner of each page, and section titles are located at the bottom outer corner of each page.
Page 7 Chapter 1 Overview Chapter 2 CPU Basics Chapter 3 Interrupts Chapter 4 I/O Ports Chapter 5 Prescaler Chapter 6 8-bit Timers Chapter 7 16-bit Timer Chapter 8 Time Base Timer / 8-bit Free-running Timer Chapter 9 Watchdog Timer Chapter 10 Buzzer Chapter 11 Serial Interface 0,1...
Page 8: Table Of Contents
Contents Chapter 1 Overview Overview ... I - 2 1-1-1 Overview ... I - 2 1-1-2 Product Summary ... I - 2 Hardware Functions ... I - 3 Pin Description ... I - 9 1-3-1 Pin Configuration ... I - 9 1-3-2 Pin Specification ...
Page 9 2-3-1 Bus Controller ... II - 15 2-3-2 Control Registers ... II - 16 Standby Function ... II - 19 2-4-1 Overview ... II - 19 2-4-2 CPU Mode Control Register ... II - 21 2-4-3 Transition between SLOW and NORMAL ... II - 22 2-4-4 Transition to STANDBY Modes ...
Page 10 3-3-8 Chapter 4 I/O Ports Overview ... IV - 2 4-1-1 4-1-2 4-1-3 Port 0 ... IV - 6 4-2-1 4-2-2 4-2-3 Port 1 ... IV - 12 4-3-1 4-3-2 4-3-3 Port 2 ... IV - 17 4-4-1 4-4-2 4-4-3 Port 5 ...
Page 11 4-10-1 Registers ... IV - 45 4-10-2 Operation... IV - 46 4-11 Synchronous Output (Port 7) ... IV - 48 4-11-1 Block Diagram ... IV - 48 4-11-2 Registers ... IV - 49 4-11-3 Operation... IV - 50 4-11-4 Setup Example ... IV - 52 Chapter 5 Prescaler Overview ...
Page 12 6-7-1 6-7-2 Serial Interface Transfer Clock Output ... VI - 33 6-8-1 6-8-2 Simple Pulse Width Measurement ... VI - 36 6-9-1 6-9-2 6-10 Cascade Connection ... VI - 39 6-10-1 6-10-2 6-11 Remote Control Carrier Output ... VI - 43 6-11-1 6-11-2 Chapter 7...
Page 13 7-8-1 Operation ... VII - 31 7-8-2 Setup Example ... VII - 32 16-bit Timer Capture ... VII - 34 7-9-1 Operation ... VII - 34 7-9-2 Setup Example ... VII - 37 Chapter 8 Time Base Timer / 8-bit Free-running Timer Overview ...
Page 14 11-1 Overview ... XI - 2 11-1-1 11-1-2 11-2 Control Registers ... XI - 6 11-2-1 11-2-2 11-2-3 11-2-4 11-2-5 11-3 Operation... XI - 21 11-3-1 11-3-2 11-3-3 11-3-4 11-3-5 11-3-6 11-3-7 11-3-8 Chapter 12 Serial Interface 3 12-1 Overview ... XII - 2 12-1-1 12-1-2 12-2 Control Registers ...
Page 15 13-1-2 Block Diagram ... XIII - 3 13-2 Control Registers ... XIII - 4 13-2-1 Registers List ... XIII - 4 13-2-2 Data Register ... XIII - 5 13-2-3 Mode Registers ... XIII - 6 13-3 Operation... XIII - 9 13-3-1 Setup Example of the Slave IIC Serial Interface ...
Page 16 15-1-2 15-2 Control Registers ... XV - 4 15-2-1 15-2-2 15-2-3 15-3 Operation... XV - 8 15-3-1 15-3-2 15-3-3 Chapter 16 D/A Converter 16-1 Overview ... XVI - 2 16-1-1 16-2 Operation... XVI - 3 16-3 Control Registers ... XVI - 4 16-3-1 16-3-2 16-3-3...
Page 17 18-4 Reprogramming Flow ... XVIII - 9 18-5 PROM writer mode ... XVIII - 10 18-6 Onboard Serial Programming Mode ... XVIII - 12 18-6-1 Overview ... XVIII - 12 18-6-2 Circuit Requirements for the Target Board (in Clock Synchronous Communication using the YDC Serial Writer) ...
Page 19: Chapter 1 Overview
Chapter 1 Overview...
Page 20: Overview
Chapter 1 Overview Overview 1-1-1 Overview The MN101C series of 8-bit single-chip microcontroller incorporates multiple types of peripheral functions. This chip series is well suited for camera, VCR, MD, TV, CD, LD, printer, telephone, home automation products, pager, air conditioner, PPC remote control, fax machine, musical instrument, and other applica- tions.
Page 21: Hardware Functions
Hardware Functions CPU Core MN101C Core - LOAD-STORE architecture (3-stage pipeline) - Half-byte instruction set / Handy addressing - Memory addressing space is 256 KB - Minimum instructions execution time (3.0 V to 3.6 V for Flash version) Low speed oscillation - Operation modes Memory bank Data memory space expansion by bank form (4 banks unit : 64 KB / 1 bank)
Page 22: Overview
Chapter 1 Overview < Serial interface interrupts > - Serial interface 0 reception interrupt (Full-Duplex UART) - Serial interface 0 transmission interrupt (synchronous + Full-Duplex UART) - Serial interface 1 reception interrupt (Full-Duplex UART) - Serial interface 1 transmission interrupt (synchronous + Full-Duplex UART) - Serial interface 3 interrupt (synchronous + single master IIC) - Serial interface 4 interrupt (slave IIC) <...
Page 23 Timer 4 ( 8-Bit timer for general use or UART baud rate timer ) - Square wave output ( Timer pulse output ), PWM output, Event count Simple pulse width measurement, Serial interface transfer clock - Clock source fosc, fosc/4, fosc/16, fosc/32, fosc/64, fs/2, fs/4, fx, external clock Timer 5 ( 8-Bit timer for general use or UART baud rate timer ) - Square wave output ( Timer pulse output ), PWM output, Event count, Remote control carrier output, Simple pulse width measurement,...
Page 24 Chapter 1 Overview Watchdog timer - Watchdog timer frequency can be selected from fs/2 Remote control output Based on the timer 0, and timer 3 output, a remote control carrier with duty cycle of 1/2 or 1/3 can be output. Synchronous output Timer synchronous output, Interrupt synchronous output - Port 6 outputs the latched data, on the event timing of the synchronous...
Page 25 Serial interface 1 ( Full-Duplex UART / Synchronous serial interface ) Synchronous serial interface - Transfer clock source - MSB/LSB can be selected as the first bit to be transferred. Any transfer size 1 to 8 bits can be selected. - Sequence transmission, sequence reception or both are available.
Page 26 Chapter 1 Overview On Flash version MN101CF77G, NC pin cannot be used as user pin as it is used as V pin. Refer to chapter 18 Flash EEPROM when designing your board for compatibility with Flash version. Set V + to V - to V even when A/D converter is not used.
Page 27: Pin Description
Pin Description 1-3-1 Pin Configuration AN3/PA3 AN4/PA4 AN5/PA5 AN6/PA6 NC(VPP) VREF+ OSC2 OSC1 MMOD NRST/P27 TXD1A/SBO1A/P00 SDA4B/RXD1A/SBI1A/P01 On Flash version of MN101CF77G, NC pin is VPP. Figure 1-3-1 MN101C77C - 64 pin for general use - Pin Configuration ( 64 LQFP/64TQFP : Top view ) Chapter 1 Overview P73/SBO1B/TXD1B P72/SBT0B...
Page 28: Pin Specification
Chapter 1 Overview 1-3-2 Pin Specification Function Input/output SBO1A TXD1A in/out SBI1A RXD1A in/out SDA4B SBT1A SCL4B in/out SBO0A TXD0A in/out SBI0A RXD0A in/out SBT0A in/out BUZZER in/out TCO0A RMOUTA in/out RMOUTB TCIO0B in/out TCO4A in/out TCIO4B in/out TCIO7 in/out IRQ0 in/out in/out...
Page 29: Pin Functions
1-3-3 Pin Functions Table 1-3-3 Name Power supply pin OSC1 Input Clock input pin OSC2 Output Clock output pin Input Clock input pin Output Clock output pin NRST Reset pin I/O port 0 I/O port 1 Pin Function Summary (1/6) Function Other Function Supply 1.8 V to 3.6 V to VDD and 0 V to VSS.
Page 30 Chapter 1 Overview Name Input I - 12 Pin Description Table 1-3-4 Pin Function Summary (2/6) Function Other Function 5-Bit CMOS tri-state I/O port. I/O port 2 IRQ0 A pull-up resistor for each bit can be selected IRQ1, ACZ individually by the P2PLU register. IRQ2 At reset, pull-up resistors are disabled IRQ3...
Page 31 Table 1-3-5 Name Function Serial interface SBO0A Output transmission data SBO0B output pins SBO1A SBO1B SBO3 Serial interface SBI0A Input reception data input SBI0B pins SBI1A SBI1B SBI3 Serial interface SBT0A clock I/O pins SBT0B SBT1A SBT1B SBT3 UART transmission TXD0A Output data output pins...
Page 32: Control Registers
Chapter 1 Overview Name UART reception RXD0A Input data input pin RXD0B RXD1A RXD1B Timer I/O pins TCO0A TCI00B TCI01 TCO4A TCI04B TCI05 Serial interface SDA4A data I/O pins SDA4B Serial interface 4 SCL4A clock I/O pins SCL4B RMOUT Remote control transmission signal output pin I - 14...
Page 33 Table 1-3-7 Name Function BUZZER 21 Output Buzzer output TCI07 Timer I/O pin VREF+ + power supply for A/D converter VREF- - power supply for A/D converter Input Analog input pins Output Analog output pins PA0, AN0 External interrupt IRQ0 Input input pins IRQ1...
Page 34: Functions
Chapter 1 Overview Nam e Key interrupt input KEY0 pins KEY1 KEY2 KEY3 KEY4 KEY5 KEY6 KEY7 MMOD Input Mem ory m ode s witching input pins I - 16 Pin Description Table 1-3-8 Pin Function Summary (6/6) Function Other Function P60, SDO0 P61, SDO1 P62, SDO2...
Page 35: Block Diagram
Block Diagram 1-4-1 Block Diagram TXD1A,SBO1A,P00 SDA4B,RXD1A,SBI1A,P01 SCL4B,SBT1A,P02 TXD0A,SBO0A,P03 RXD0A,SBI0A,P04 SBT0A,P05 BUZZER,P06 RMOUTA,TCO0A,P10 ROMUTB,TCIO0B,P11 TCO4A,P12 TCIO4B,P13 TCIO7,P14 IRQ0,P20 ACZ,IRQ1,P21 IRQ2,P22 IRQ3,P23 IRQ4,P24 NRST,P27 Low Speed High Speed oscillator oscillator 48KB External Interrupt 8-Bit Timer 0 8-Bit Timer 1 Serial Interface 1 8-Bit Timer 4 8-Bit Timer 5 16-Bit Timer 7...
Page 36: Electrical Characteristics
Chapter 1 Overview Electrical Characteristics Model MN101C77 Contents Structure CMOS integrated circuit Application General purpose Function 8-Bit single-chip microcontroller 1-5-1 Absolute Maximum Ratings Parameter Power supply voltage Input clamp voltage Input pin voltage Output pin voltage I/O pin voltage Port 8 *4 Peak output Other than Port 8 current...
Page 37: Operating Conditions
1-5-2 Operating Conditions Parameter Power supply voltage Power supply voltage Voltage to maintain RAM data Operation speed *1 Minimum instruction execution time Crystal osillator 1 Figure 1-5-1 Crystal frequency External capasitors Internal feedback resistor Crystal osillator 2 Figure 1-5-2 Crystal frequency External capasitors Internal feedback resistor tc1, tc2, tc3 : 1/2 of high speed oscillation...
Page 38 Chapter 1 Overview Parameter External clock input 1 OSC1 (OSC2 is opened) Clock frequency High level pulse width Low level pulse width Rising time Falling time External clock input 2 XI (XO is opened) Clock frequency High level pulse width Low level pulse width Rising time Falling time...
Page 39 Chapter 1 Overview 0.9V 0.1V Figure 1-5-3 OSC1 Timing Chart 0.9V 0.1V Figure 1-5-4 XI Timing Chart I - 21 Electrical Characteristics...
Page 40: Dc Characteristics
Chapter 1 Overview 1-5-3 DC Characteristics Parameter Symbol Power supply current (not load at output pin) *1 Power supply current Supply current during HALT1 mode Supply current during STOP mode Measured under conditions of Ta=25 °C, without load. - The supply current during operation, I After all I/O pins are set to input mode and the oscillation is set to <NORMAL mode>, the MMOD pin is connected to V (8.39 MHz) square wave of V...
Page 41 Parameter Symbol Input pin 1 MMOD Input high voltage Input low voltage Input leakage current Input pin 2 P21 (at used as ACZ) Input high voltage 1 Input low voltage 1 Input high voltage 2 Input low voltage 2 Input leakage current Rising time Falling time Input voltage level 1...
Page 42 Chapter 1 Overview Param eter Input pin 3 P27 (NRST) Input high voltage Input low voltage Input high current I/O pin 4 PA0 to PA6 Input high voltage Input low voltage Input leakage current Input high current Input low current Output high voltage Output low voltage I/O pin 5 P00 to P06, P10 to P14, P20 to P24, P50 to P54, P60 to P67...
Page 43 Parameter Symbol I/O pin 7 P80 to P87 Input high voltage Input low voltage Input leakage current Input high current Output high voltage Output low voltage Output low voltage (LED) OLL7 VDD=1.8 V to 3.6 V VSS=0 V Ta=-40 C to +85 Conditions 0.8V =0 V to V...
Page 44: A/D Converter Characteristics
Chapter 1 Overview 1-5-4 A/D Converter Characteristics *2 Param eter Res olution Non-linearity error 1 Differential non-linearity error 1 Non-linerarity error Differential non-linearity error 2 Zero trans ition voltage Full-s cale trans ition voltage A/D convers ion tim e Sam pling tim e Reference voltage Analog input voltage Analog input leakage...
Page 45: D/A Converter Characteristics
1-5-5 D/A Converter Characteristics *2 Parameter Resolution *1 Reference voltage low level Reference voltage high level Zero-scale output voltage *1 Full-scale output voltage *1 Analog output resistance (minimum reference resistance) Non-linearity error Differenctial non-linearity error Settling time *1 *1 The standard value is guaranteed under condition of V *2 The value is measured with D/A Converter, not with A/D Converter.
Page 46: Precautions
Chapter 1 Overview Precautions 1-6-1 General Usage Connection of V pin, and V All V pins should be connected directly to the power supply and all Vss pins should be connected to ground in the external. The following shows the correct connections and the incorrect connections. Please consider the LSI chip orientation before mounting it on the printed circuit board.
Page 47: Unused Pins
Chapter 1 Overview 1-6-2 Unused Pins Unused Pins (only for input) Insert 10 k to 100 k resistor to unused pins (only for input) for pull-up or pull-down. If the input is unstable, Pch transistor and Nch transistor of input inverter are on, and through current goes to the input circuit.
Page 48 Chapter 1 Overview Unused pins (for I/O) Unused I/O pins should be set according to pins' condition at reset. If the output is high impedance (Pch / Nch transistor : output off) at reset, to stabilize input, set 10 k to 100 k resistor to be pull-up or pull- down.
Page 49: Power Supply
1-6-3 Power Supply The Relation between Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on. If the input pin voltage is applied supplies before power supply is on, a latch up occurs and causes the destruction of micro controller by a large current flow.
Page 50: Power Supply Circuit
Chapter 1 Overview 1-6-4 Power Supply Circuit Cautions for Setting Power Supply Circuit The CMOS logic microcontroller is high speed and high density. So, the power circuit should be de- signed, taking into consideration of AC line noise, ripple caused by LED driver. Figure 1-6-6 shows an example for emitter follower type power supply circuit.
Page 51: Package Dimension
Chapter 1 Overview Package Dimension Package Code : LQFP064-P-1414 Units : mm I - 33 Package Dimension...
Page 52 Chapter 1 Overview Package Code : TQFP064-P-1010C Units : mm I - 34 Precautions...
Page 53: Cpu Basics
Chapter 2 CPU Basics...
Page 54: Overview
Chapter 2 CPU Basics Overview The MN101C CPU has a flexible optimized hardware configuration. It is a high speed CPU with a simple and efficient instruction set. Specific features are as follows: 1. Minimized code sizes with instruction lengths based on 4-bit increments The series keeps code sizes down by adopting a basic instruction length of one byte and variable instruction lengths based on 4-bit increments.
Page 55: Block Diagram
2-1-1 Block Diagram Address registers Stack pointer ABUS BBUS Program counter Incrementer Program address ROM bus Internal ROM Uses a clock oscillator circuit driven by an external crystal or ceramic resonator to supply clock signals Clock generator to CPU blocks. Generates addresses for the instructions to be inserted into the instruction queue.
Page 56: Cpu Control Registers
Chapter 2 CPU Basics 2-1-2 CPU Control Registers This LSI locates the peripheral circuit registers in memory space (x'03F00' to x'03FFF') with memory- mapped I/O. CPU control registers are also located in this memory space. Registers Address x'03F00' CPUM R/W *1 x'03F01' MEMCTR x'03F0E'...
Page 57: Instruction Execution Controller
2-1-3 Instruction Execution Controller The instruction execution controller consists of four blocks: memory, instruction queue, instruction regis- ters, and instruction decoder. Instructions are fetched in 1-byte units, and temporarily stored in the 2-byte instruction queue. Transfer is made in 1-byte or half-byte units from the instruction queue to the instruction register to be decoded by the instruction decoder.
Page 58: Pipeline Process
Chapter 2 CPU Basics 2-1-4 Pipeline Process Pipeline process means that reading and decoding are executed at the same time on different instruc- tions, then instructions are executed without stopping. Pipeline process makes instruction execution continual and speedy. This process is executed with instruction queue and instruction decoder. Instruction queue is buffer that fetches the second instruction in advance.
Page 59: Registers For Data
Address Registers (A0, A1) These registers are used as address pointers specifying data locations in memory. They support the operations involved in address calculations (i.e. addition, subtraction and comparison). Those pointers are 2 bytes data. Transfers between these registers and memory are always in 16-bit units. Either odd or even address can be transferred.
Page 60: Processor Status Word
Chapter 2 CPU Basics 2-1-7 Processor Status Word Processor status word (PSW) is an 8-bit register that stores flags for operation results, interrupt mask level, and maskable interrupt enable. PSW is automatically pushed onto the stack when an interrupt occurs and is automatically popped when return from the interrupt service routine. Reserved Figure 2-1-3 II - 8...
Page 61 Zero Flag (ZF) Zero flag (ZF) is set to "1", when all bits are '0' in the operation result. Otherwise, zero flag is cleared to "0". Carry Flag (CF) Carry flag (CF) is set to "1", when a carry from or a borrow to the MSB occurs. Carry flag is cleared to "0", when no carry or borrow occurs.
Page 62: Addressing Modes
Chapter 2 CPU Basics 2-1-8 Addressing Modes The MN101C77G series supports the nine addressing modes. Each instruction uses a combination of the following addressing modes. 1) Register direct 2) Immediate 3) Register indirect 4) Register relative indirect 5) Stack relative indirect 6) Absolute 7) RAM short 8) I/O short...
Page 63 Table 2-1-4 Addressing mode Dn/DWn An/SP Register direct imm4/imm8 Immediate imm16 (An) Register indirect (d8, An) (d16, An) Register relative indirect (d4, PC) (branch instructions only) (d7, PC) (branch instructions only) (d11, PC) (branch instructions only) (d12, PC) (branch instructions only) (d16, PC) (branch instructions only) (d4, SP)
Page 64: Memory Space
Chapter 2 CPU Basics Memory Space 2-2-1 Memory Mode ROM is the read only area and RAM is the memory area which contains readable/writable data. In addition to these, peripheral resources such as memory-mapped special registers are allocated. The MN101C series supports single chip mode in its memory model. Memory mode Single chip mode MMOD pin should be fixed to "L"...
Page 65: Single-Chip Mode
2-2-2 Single-chip Mode In single-chip mode, the system consists of only internal memory. This is the optimized memory mode and allows construction of systems with the highest performance. The single-chip mode uses only internal ROM and internal RAM. The MN101C series devices offer up to 12 KB of RAM and up to 240 KB of ROM.
Page 66: Special Function Registers
Chapter 2 CPU Basics 2-2-3 Special Function Registers The MN101C series locates the special function registers (I/O spaces) at the addresses x'03F00' to x'03FFF' in memory space. The special function registers of this LSI are located as shown below. Table 2-2-3 Register Map II - 14 Memory Space...
Page 67: Bus Interface
Bus Interface 2-3-1 Bus Controller The MN101C series provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads and thus realize faster operation. There are three such buses: ROM bus, RAM bus, and peripheral expansion bus (I/O bus). They connect to the internal ROM, internal RAM, and internal peripheral circuits respectively.
Page 68: Control Registers
Chapter 2 CPU Basics 2-3-2 Control Registers Bus interface is controlled by these 8 bytes of registers : the memory control register (MEMCTR), memory area control register (AREACTR) and bus mode control register (CSMDn). Memory Control Register (MEMCTR) IVBM IOW1 IOW0 MEMCTR Figure 2-3-2 EXW1 to 0, EXWH and IOW1 to 0 flags of the memory control register (MEMCTR) need not...
Page 69 Memory Area Control Register (AREACTR) AREACTR CS8EXT CS7EXT CS6EXT CS5EXT CS4EXT CS3EXT CS2EXT CS1EXT Figure 2-3-3 Memory Area Control Register (AREACTR : x'03F03', R/W) In CS0 area, MMOD pin selects internal ROM/external memory. In CS9 area, only external memory can be selected as internal memory is not available.
Page 70 Chapter 2 CPU Basics Bus Mode Control Register (CSMDn) CSMD01 CS1MD CS1W2 CS1W1 CS1W0 (X'03F05') CSMD23 CS3MD CS3W2 CS3W1 CS3W0 CS2MD CS2W2 CS2W1 CS2W0 (X'03F06') CSMD45 CS5MD CS5W2 CS5W1 CS5W0 CS4MD CS4W2 CS4W1 CS4W0 (X'03F07') CSMD67 CS7MD CS7W2 CS7W1 CS7W0 CS6MD CS6W2 CS6W1 CS6W0 (X'03F08') CSMD89 CS9W2 CS9W1 CS9W0 CS8MD CS8W2 CS8W1 CS8W0...
Page 71: Standby Function
Standby Function 2-4-1 Overview This LSI has two sets of system clock oscillator (high speed oscillation, low speed oscillation) for two CPU operating modes (NORMAL and SLOW), each with two standby modes (HALT and STOP). Power consumption can be decreased with using those modes. Reset XI: Low-frequency oscillation clock (32 kHz) Figure 2-4-1...
Page 72 Chapter 2 CPU Basics HALT Modes (HALT0, HALT1) The CPU stops operating. But both of the oscillators remain operational in HALT0 and only the high- frequency oscillator stops operating in HALT1. An interrupt returns the CPU to the previous CPU operating mode that is, to NORMAL from HALT0 or to SLOW from HALT1.
Page 73: Cpu Mode Control Register
2-4-2 CPU Mode Control Register Transition from one mode to another mode is controlled by the CPU mode control register (CPUM). OSCSEL1 CPUM SOSCDBL At reset : Operation STOP HALT mode NORMAL IDLE SLOW HALT0 HALT1 STOP0 STOP1 Figure 2-4-2 Operating Mode and Clock Oscillation (CPUM : x'3F00', R/W) The procedure for transition from NORMAL to HALT or STOP mode is given below.
Page 74: Transition Between Slow And Normal
Chapter 2 CPU Basics 2-4-3 Transition between SLOW and NORMAL This LSI has two CPU operating modes, NORMAL and SLOW. Transition from SLOW to NORMAL requires passing through IDLE mode. A sample program for transition from NORMAL to SLOW mode is given below. Program 1 MOV x'3', D0 MOV D0, (CPUM)
Page 75: Transition To Standby Modes
2-4-4 Transition to STANDBY Modes The program initiates transitions from a CPU operating mode to the corresponding STANDBY (HALT/ STOP) modes by specifying the new mode in the CPU mode control register (CPUM). Interrupts initiate the return to the former CPU operating mode. Before initiating a transition to a STANDBY mode, however, the program must Set the maskable interrupt enable flag (MIE) in the processor status word (PSW) to '0' to disable all maskable interrupts temporarily.
Page 76 Chapter 2 CPU Basics Transition to HALT modes The system transfers from NORMAL mode to HALT0 mode, and from SLOW mode to HALT1 mode. The CPU stops operating, but the oscillators remain operational. There are two ways to leave a HALT mode: a reset or an interrupt.
Page 77: Clock Switching
Clock Switching This LSI can select the best operation clock for system by switching clock cycle division factor by program. Division factor is determined by both flags of the CPU mode control register (CPUM) and the Oscillator frequency control register (OSCMD). At the highest-frequency, CPU can be operated in the same clock cycle to the external clock hence providing wider operating frequency range.
Page 78 Chapter 2 CPU Basics High-frequency Low-frequency SOSC2DS OSCSEL1 Figure 2-5-4 OSCSEL1 Figure 2-5-5 On clock switching, set each flag of OSCDBL, OSCSEL, SOSCSEL and OSC0, individually. Even if those flags are mapped on the same special functions register, set twice. Set the OSC0 flag to "0"...
Page 79: Bank Function
Bank Function 2-6-1 Overview CPU of MN101C00 series has basically 64 KB memory address space. On this LSI, address space can be expanded up to 4 banks (256 KB) based on units of 64 KB, by bank function. 2-6-2 Bank Setting Bank function can be used by setting the proper bank area to the bank register for source address (SBNKR) or the bank register for destination address (DBNKR).
Page 80 Chapter 2 CPU Basics Bank Register for Source Address The SBNKR register is used to specify bank area for loading instruction from memory to register. Once this register is specified, bank control is valid for all addressing modes except I/O short instruction and stack relative indirect instruction.
Page 81: Bank Memory Space
2-6-3 Bank Memory Space When bank function is used, the memory space, where CPU can access as data, shows as the following hatched part. Single Chip Mode In single chip mode used internal ROM and internal RAM, an expanded bank area (bank 1, 2 and a part of bank 3) is in the memory space of internal ROM.
Page 82: Rom Correction
Chapter 2 CPU Basics ROM Correction 2-7-1 Overview This LSI can correct and change max. 3 parts in a program on mask ROM with ROM correction function. The correct program is read from the external to the RAM space by using the external EEPROM or by using the serial transmission.
Page 83 The ROM correction setup procedure is as follows. (1) Set the head address of the program to be corrected to the ROM correction address setting register (RCnAPH/M/L). (2) Set the correct program at RAM area. (3) Set the head address of the correct program to RC vector table (RCnV(L), RCnV(H)). (4) Set the RCnEN flag of ROM correction control register (RCCTR) to enable the ROM correction.
Page 84: Rom Correction Control Register
Chapter 2 CPU Basics 2-7-3 ROM Correction Control Register ROM correction control register (RCCTR) and ROM correction address setting register (RCnAPL, RCnAPM, RCnAPH) control the ROM correction. ROM correction control register (RCCTR) enables/disables the ROM correction function to 3 parts of the program to be corrected.
Page 85: Control Registers
This register set the head address, which instructions to be corrected are stored to. Once the instruction execution address reaches to the set value to this register, program counter branches indirectly to the set address to the RC vector table (RCnV(L), RCnV(H)). When the ROM correction should be valid, set the RCnEN flag of the ROM correction control register (RCCTR) after setting the address to this register.
Page 86: Control Registers
Chapter 2 CPU Basics ROM Correction Address 2 Setting Register (RC2AP) RC2APL7 RC2APL6 RC2APL5 RC2APL4 RC2APL3 RC2APL2 RC2APL1 RC2APL0 ( At reset : X X X X X X X X) RC2APL Figure 2-7-9 RC2APM RC2APM7 RC2APM6 RC2APM5 RC2APM4 RC2APM3 RC2APM2 RC2APM1 RC2APM0 ( At reset : X X X X X X X X ) Figure 2-7-10 RC2APH Figure 2-7-11...
Page 87: Rom Correction Setup Example
2-7-4 ROM Correction Setup Example Initial Routine with ROM Correction The following routine should be set to correct the program. Also store the ROM correction setup and the correct program to the external EEPROM, in advance. Here is the steps for ROM correction execution. Enable the ROM correction operation Figure 2-7-12 Initial Setup...
Page 88 Chapter 2 CPU Basics ROM Correction Setup Example The setup procedure with ROM correction to correct 2 parts of the program is shown below. For the step to execute the ROM correction, refer to figure 2-7-12. Initial Routine for ROM correction on the previous page.
Page 89 [Setup for the second correction] Set the head address of the program to be corrected at second to the ROM correction address 1 setting register (RC1AP). RC1APL = x'FD' RC1APM = x'08' RC1APH = x'01' Set the internal RAM address x'06BC' that stored the second correct program to the RC vector table address (RC1V(L), RC1V(H).
Page 90: Reset
Chapter 2 CPU Basics Reset 2-8-1 Reset operation The CPU contents are reset and registers are initialized when the NRST pin is pulled to low. Initiating a Reset There are two methods to initiate a reset. Drive the NRST pin low. NRST pin should be held "low"...
Page 91: Oscillation Stabilization Wait Time
Sequence at Reset When reset pin comes to high level from low level, the innternal 14-bit counter (It can be used as watchdog timer, too.) starts its operation by system clock. The period from starting its count from its overflow is called oscillation stabilization wait time. During reset, internal register and special function register are initiated.
Page 92 Chapter 2 CPU Basics 2-8-2 Oscillation Stabilization Wait time Oscillation stabilization wait time is the period from the stop of oscillation circuit to the stablization for oscillation. Oscillation stabilization wait time is automatically inserted at releasing from reset and at recovering from STOP mode.
Page 93 Oscillation Stabilization Wait Time Control Register DLYCTR BUZOE BUZS2 BUZS1 BUZS0 Figure 2-8-4 Oscillation Stabilization Wait Time Control Register (DLYCTR : x'03F4D', R/W) Control the Oscillation Stabilization Wait Time At recovering from STOP mode, the bit 3-2 (DLYS1, DLYS0) of the oscillation stabilization wait time control register can be set to select the oscillation stabilization wait time from 2 clock.
Page 94: Register Protection
Chapter 2 CPU Basics Register Protection 2-9-1 Overview This LSI features a function to protect important register data. When this function is enabled, data is rewritten only when write is done for several times to a register and other write is disabled. Registers with this function are as follows.
Page 95: Chapter 3 Interrupts
Chapter 3 Interrupts...
Page 96: Overview
Chapter 3 Interrupts Overview This LSI speeds up interrupt response with circuitry that automatically loads the branch address to the corresponding interrupt service routine from an interrupt vector table : reset, non-maskable interrupts (NMI), 16 maskable peripheral interrupts, and 5 external interrupts. For interrupts other than reset, the interrupt processing sequence consists of interrupt request, interrupt acceptance, and hardware processing.
Page 97: Peripheral Functions
3-1-1 Functions Interrupt type Vector number Table address Starting address Interrupt level Interrupt factor External RST pin input Generated operation Direct input to CPU core Accept operation Machine cycles until acceptance All flags are cleared PSW status after acceptance Table 3-1-1 Interrupt Functions Reset (interrupt) Non-maskable interrupt...
Page 98: Block Diagram
Chapter 3 Interrupts 3-1-2 Block Diagram IRQLVL III - 4 Overview Level deter- mined IRQNM1 IRQ0ICR xxx ICR Figure 3-1-1 Interrupt Block Diagram Interrupt CPU core Vector 1 NMICR WDOG Vector 2 x x x LV1-0 xxxIE xxxIR Peripheral function xxxLV : Interrupt Level xxxIE : Interrupt Enable xxxIR : Interrupt Request...
Page 99: Operation
3-1-3 Operation Interrupt Processing Sequence For interrupts other than reset, the interrupt processing sequence consists of interrupt request, interrupt acceptance, and hardware processing. The program counter (PC) and processor status word (PSW) and handy addressing data (HA) are saved onto the stack, and execution branches to the address specified by the corresponding interrupt vector.
Page 100 Chapter 3 Interrupts Interrupt Sources and Vector Addresses Here is the list of interrupt vector address and interrupt group. Table 3-1-2 Vector Vector Number Address x'04000' Reset x'04004' Non-maskable interrupt x'04008' External interrupt 0 x'0400C' External interrupt 1 x'04010' External interrupt 2 x'04014' External interrupt 3 x'04018'...
Page 101 Interrupt Level and Priority This LSI allocated vector numbers and interrupt control registers (except reset interrupt) to each inter- rupt. The interrupt level (except reset interrupt, non-maskable interrupt) can be set by software, per each interrupt group. There are three hierarchical interrupt levels. If multiple interrupts have the same priority, the one with the lowest vector number takes priority.
Page 102 Chapter 3 Interrupts Determination of Interrupt Acceptance The following is the procedure from interrupt request input to acceptance. The interrupt request flag (xxxIR) in the corresponding external interrupt control register(IRQnICR) or internal interrupt control register (xxxICR) is set to '1'. An interrupt request is input to the CPU, If the interrupt enable flag (xxxIE) in the same register is '1'.
Page 103 MIE='0' and interrupts are disabled when: MIE in the PSW is reset to '0' by a program Reset is detected MIE='1' and interrupts are enabled when: MIE in the PSW is set to '1' by a program The interrupt mask level (IM=IM1 - IM0) in the processor status word (PSW) changes when: The program alters it directly, A reset initializes it to 0 (00b), The hardware accepts and thus switches to the interrupt level (IL) for a maskable interrupt, or...
Page 104 Chapter 3 Interrupts Interrupt Acceptance Operation When accepting an interrupt, this LSI hardware saves the handy address register, the return address from the program counter, and the processor status word (PSW) to the stack and branches to the interrupt handler using the starting address in the vector table. The following is the hardware processing sequence after by interrupt acceptance.
Page 105 Maskable Interrupt Figure 3-1-6 shows the processing flow when a second interrupt with a lower priority level (xxxLV1- xxxLV0='10') arrives during the processing of one with a higher priority level (xxxLV1-xxxLV0='00'). (Clear MIE IM0,1='00') Interrupt 1 generated (xxxLV1,0='00') Interrupt acceptance cycle (IM1,0='00') Interrupt acceptance cycle (IM1,0='10')
Page 106 Chapter 3 Interrupts Multiplex Interrupt When an MN101C77 series device accepts an interrupt, it automatically disables acceptance of subse- quent interrupts with the same or lower priority level. When the hardware accepts an interrupt, it copies the interrupt level (xxxLVn) for the interrupt to the interrupt mask (IM) in the PSW. As a result, subsequent interrupts with the same or lower priority levels are automatically masked.
Page 107 Chapter 3 Interrupts Figure 3-1-7 shows the processing flow for multiple interrupts (interrupt 1: xxxLV1-xxxLV0='10', and interrupt 2: xxxLV1-xxxLV0='00'). Main program IM1,0='11' Accepted because xxxLV1,0 Interrupt 1 generated <IM (xxxLV1,0='10') Interrupt acceptance cycle IM1,0='10' Interrupt service routine: 1 * Interrupt 2 generated Accepted because xxxLV1,0 <IM (xxxLV1,0='00')
Page 108: Interrupt Flag Setup
Chapter 3 Interrupts 3-1-4 Interrupt Flag Setup Interrupt request flag (IR) setup by the software The interrupt request flag is operated by the hardware. That is set to "1" when any interrupt factor is generated, and cleared to "0" when the interrupt is accepted. If you want to operate it by the software, the IRWE flag of MEMCTR should be set to "1".
Page 109: Control Registers
Control Registers 3-2-1 Registers List Table 3-2-1 Register Address NMICR x'03FE1' Non-maskable interrupt control register IRQ0ICR x'03FE2' External interrupt 0 control register IRQ1ICR x'03FE3' External interrupt 1 control register IRQ2ICR x'03FE4' External interrupt 2 control register IRQ3ICR x'03FE5' External interrupt 3 control register IRQ4ICR x'03FE6' External interrupt 4 control register...
Page 110: Interrupt Control Registers
Chapter 3 Interrupts 3-2-2 Interrupt Control Registers The interrupt control registers include the maskable interrupt control registers (xxxICR) and the non- maskable interrupt control register (NMICR). Non-Maskable Interrupt Control Register (NMICR address: x'03FE1') The non-maskable interrupt control register (NMICR) stores the non maskable interrupt request. When the non-maskable interrupt request is generated, the interrupt is accepted regardless of the interrupt mask level (IMn) of PSW.
Page 111 External Interrupt 0 Control Register (IRQ0ICR) The external interrupt 0 control register (IRQ0ICR) controls interrupt level of the external interrupt 0, active edge, interrupt enable and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". IRQ0 IRQ0 IRQ0ICR...
Page 112 Chapter 3 Interrupts External Interrupt 1 Control Register (IRQ1ICR) The external interrupt 1 control register (IRQ1ICR) controls interrupt level of external interrupt 1, active edge, interrupt enable and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". IRQ1 IRQ1 IRQ1ICR...
Page 113 External Interrupt 2 Control Register (IRQ2ICR) The external interrupt 2 control register (IRQ2ICR) controls interrupt level of external interrupt 2, active edge, interrupt enable and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". IRQ2 IRQ2 IRQ2ICR...
Page 114 Chapter 3 Interrupts External Interrupt 3 Control Register (IRQ3ICR) The external interrupt 3 control register (IRQ3ICR) controls interrupt level of external interrupt 3, active edge, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". IRQ3 IRQ3 REDG3...
Page 115 External Interrupt 4 Control Register (IRQ4ICR) The external interrupt 4 control register (IRQ4ICR) controls interrupt level of external interrupt 4, active edge, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". IRQ4 IRQ4 REDG4...
Page 116 Chapter 3 Interrupts Timer 0 Interrupt Control Register (TM0ICR) The timer 0 interrupt control register (TM0ICR) controls interrupt level of timer 0 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0". TM0ICR Figure 3-2-8 Timer 0 Interrupt Control Register (TM0ICR : x'03FE9', R/W)
Page 117 Timer 1 Interrupt Control Register (TM1ICR) The timer 1 interrupt control register (TM1ICR) controls interrupt level of timer 1 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0". TM1ICR Figure 3-2-9 Timer 1 Interrupt Control Register (TM1ICR : x'03FEA', R/W)
Page 118 Chapter 3 Interrupts Timer 4 Interrupt Control Register (TM4ICR) The timer 4 interrupt control register (TM4ICR) controls interrupt level of timer 4 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0". TM4ICR Figure 3-2-12 Timer 4 Interrupt Control Register (TM4ICR : x'03FED', R/W)
Page 119 Timer 5 Interrupt Control Register (TM5ICR) The timer 5 interrupt control register (TM5ICR) controls interrupt level of timer 5 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0". TM5ICR Figure 3-2-13 Timer 5 Interrupt Control Register (TM5ICR : x'03FEE', R/W)
Page 120 Chapter 3 Interrupts Timer 6 Interrupt Control Register (TM6ICR) The timer 6 interrupt control register (TM6ICR) controls interrupt level of timer 6 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0". TM6ICR Figure 3-2-14 Timer 6 Interrupt Control Register (TM6ICR : x'03FEF', R/W)
Page 121 Time Base Interrupt Control Register (TBICR) The time base interrupt control register (TBICR) controls interrupt level of time base interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0". TBICR Figure 3-2-15 Time Base Interrupt Control Register (TBICR : x'03FF0', R/W)
Page 122 Chapter 3 Interrupts Timer 7 Interrupt Control Register (TM7ICR) The timer 7 interrupt control register (TM7ICR) controls interrupt level of timer 7 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0". TM7ICR Figure 3-2-16 Timer 7 Interrupt Control Register (TM7ICR : x'03FF1', R/W)
Page 123 Timer 7 Compare Register 2-match Interrupt Control Register (TOC2ICR) The timer 7 compare register 2-match interrupt control register (TOC2ICR) controls interrupt level of timer 7 compare register 2-match interrupt , interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". T7OC2 T7OC2 T7OC2ICR...
Page 124 Chapter 3 Interrupts Serial Interface 0 Reception Interrupt Control Register (SC0RICR) The serial Interface 0 reception interrupt control register (SC0RICR) controls interrupt level of serial Interface 0 reception interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". SC0R SC0R SC0RICR...
Page 125 Serial Interface 0 Transmission Interrupt Control Register (SC0TICR) The serial Interface 0 transmission interrupt control register (SC0TICR) controls interrupt level of serial Iinterface 0 transmission interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". SC0T SC0T SC0TICR...
Page 126 Chapter 3 Interrupts Serial Interface 1 Reception Interrupt Control Register (SC1ICR) The serial Interface 1 reception interrupt control register (SC1ICR) controls interrupt level of serial Interface 1 reception interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". SC1R SC1R SC1RICR...
Page 127 Serial Interface 1 Transmission Interrupt Control Register (SC1TICR) The serial Interface 1 transmission interrupt control register (SC1TICR) controls interrupt level of serial Iinterface 1 transmission interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". SC1T SC1T SC1TICR...
Page 128 Chapter 3 Interrupts Serial Interface 3 Interrupt Control Register (SC3ICR) The serial interface 3 interrupt control register (SC3ICR) controls interrupt level of serial interface 3 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". SC3ICR Figure 3-2-23 Serial Interface 3 Interrupt Control Register (SC3ICR : x'03FF9', R/W)
Page 129 Serial Interface 4 Interrupt Control Register (SC4ICR) The serial interface 4 interrupt control register (SC4ICR) controls interrupt level of serial interface 4 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". SC4ICR Figure 3-2-24 Serial Interface 4 Interrupt Control Register (SC4ICR : x'03FF3', R/W)
Page 130 Chapter 3 Interrupts A/D Converter Interrupt Control Register (ADICR) The A/D converter interrupt control register (ADICR) controls interrupt level of A/D converter interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0". ADICR Figure 3-2-25 A/D Converter Interrupt Control Register (ADICR : x'03FFA', R/W)
Page 131 ATC 1 Interrupt Control Register (ATC1ICR) The ATC 1 interrupt control register (ATC1ICR) controls interrupt level of ATC 1 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0". ATC1 ATC1 ATC1ICR...
Page 132: External Interrupts
Chapter 3 Interrupts External Interrupts There are 5 external interrupts in this LSI. The circuit (external interrupt interface) for the external interrupt input signal, is built-in between the external interrupt input pin and the interrupt controller block. This external inter- rupt interface can manage to do with any kind of external interrupts.
Page 133: Block Diagram
3-3-2 Block Diagram External Interrupt 0 Interface, External Interrupt 1 Interface, Block Diagram PSCMD PSCEN 3-bit prescaler fosc/2 fosc/2 (Prescaler fosc/2 output signal) fosc/2 fosc P20/IRQ0 P21/IRQ1/ACZ Figure 3-3-1 External Interrupt 0 Interface and External Interrupt 1 Interface Block Diagram Standby mode signal Noise filter 0 Standby mode signal...
Page 134 Chapter 3 Interrupts External Interrupt 2 Interface, External Interrupt 3 Interface, Block Diagram P22/IRQ2 Noise filter2 P23/IRQ3 Noise filter3 Figure 3-3-2 External Interrupt 2 Interface and External Interrupt 3 Interface, Block Diagram III - 40 External Interrupts IRQ2ICR IRQ2IR IRQ2IE REDG2 IRQ2LV0 IRQ2LV1...
Page 135 External Interrupt 4 Interface Block Diagram Noise filter 4 P24/IRQ4 P60/KEY0 P61/KEY1 P62/KEY2 P63/KEY3 P64/KEY4 P65/KEY5 P66/KEY6 P67/KEY7 Figure 3-3-3 Polarity Inversion Edge detection P6IMD P6KYEN1 P6KYEN2 P6KYEN3 P6KYEN4 IRQ4SEL External Interrupt 4 Interface Block Diagram Chapter 3 Interrupts IRQ4ICR EDGDT EDGSEL0 IRQ4IR...
Page 136: Control Registers
Chapter 3 Interrupts 3-3-3 Control Registers The external interrupt input signal, which operated in each external interrupt 0 to 4 interface generate interrupt requests. External interrupt 0 to 4 interface are controlled by the external interrupt control register (IRQnICR) and the both edges interrupt control register (EDGDT).
Page 137: Registers
Noise Filter Control Register 0 (NFCTR0) The noise filter control register (NFCTR0) sets the noise remove function for IRQ0 and IRQ1 and also selects the sampling cycle of noise remove function. And this register also set the AC zero cross detec- tion function for IRQ1.
Page 138 Chapter 3 Interrupts Noise Filter Control Register 1 (NFCTR1) The noise filter control register (NFCTR1) sets the noise remove function for IRQ2 to IRQ4. NFCTR1 Figure 3-3-5 III - 44 External Interrupts NF4EN NF3EN NF2EN Noise Filter Control Register 1 (NFCTR1 : x'03F8D', R/W) ( At reset : - - - - - 0 0 0) NF2EN IRQ2/ noise filter setup...
Page 139 Both Edges Interrupt Control Register (EDGDT) The both edges interrupt control register (EDGDT) selects interrupt edges of IRQ0 to IRQ4. Interrupts are generated at both edges, or at single edge. The external interrupt control register (IRQ0ICR to IRQ4ICR) specifies whether interrupts are generated. EDGDT Reserved EDGSEL4...
Page 140 Chapter 3 Interrupts Port 6 Key Interrupt Control Register (P6IMD) The port 6 key interrupt control register (P6IMD) selects if key interrupt is approved, and if external interrupt IRQ4 is approved. Also, this register selects, by 2 bits, which pin on port 6 approved key interrupt. P6IMD IRQ4SEL Figure 3-3-7 Port 6 Key Interrupt Control Register (P6IMD : x'03F3E', R/W)
Page 141: Programmable Active Edge Interrupt
3-3-4 Programmable Active Edge Interrupt Programmable Active Edge Interrupts (External interrupts 0 to 4) Through register settings, external interrupts 0 to 5 can generate interrupt at the selected edge either rising or falling edge. Programmable Active Edge Interrupt Setup Example (External interrupt 0 to 4) External interrupt 4 (IRQ4) is generated at the rising edge of the input signal from P24.
Page 142: Both Edges Interrupt
Chapter 3 Interrupts 3-3-5 Both Edges Interrupt Both Edges Interrupt (External interrupts 0 to 4) Both edges interrupt can generate interrupt at both the falling edge and the rising edge by the input signal from external input pins. CPU also can be returned from standby mode by both edges interrupt. Both Edges Interrupt Setup Example (External interrupts 0 to 4) External interrupt 2 (IRQ2) is generated at the both edges of the input signal from P22 pin.
Page 143: Key Input Interrupt
3-3-6 Key Input Interrupt Key Input Interrupt (External interrupt 4) This LSI can set port 6 pin (P60 to P67) by 2 bits to key input pin. Key input interrupt can generate an interrupt at the falling edge, if at least 1 key input pin outputs low level. Key input pin should be pull-up in advance.
Page 144 Chapter 3 Interrupts Key Input Interrupt Setup Example (External interrupt 4) After P60 to P63 of port 6 are set to key input pins and key is input (low level), the external interrupt 4 (IRQ4) is generated. An example setup procedure, with a description of each step is shown below. Setup Procedure (1) Set the key input pin to input.
Page 145: Noise Filter
3-3-7 Noise Filter Noise Filter (External interrupts 0 to1) Noise filter reduce noise by sampling the input waveform from the external interrupt pins (IRQ0, IRQ1). Its sampling cycle can be selected from 4 types (fosc, fosc/2 Noise Remove Selection (External interrupts 2 to 4) Noise filter reduce noise by sampling the input waveform from the external interrupt pins (IRQ2 to IRQ4).
Page 146 Chapter 3 Interrupts Noise Remove Function Operation (External interrupts 0 to 4) After sampling the input signal to the external interrupt pins ( IRQ0 to IRQ4) by the set sampling time, if the same level comes continuously three times, that level is sent to the inside of LSI. If the same level does not come continuously three times, the previous level is sent.
Page 147 Noise Filter Setup Example (External interrupt 0 and 1) Noise remove function is added to the input signal from P20 pin to generate the external interrupt 0 (IRQ0) at the rising edge. The sampling clock is set to fosc, and the operation state is fosc = 20 MHz. An example setup procedure, with a description of each step is shown below.
Page 148: Ac Zero-Cross Detector
Chapter 3 Interrupts 3-3-8 AC Zero-Cross Detector This LSI has AC zero-cross detector circuit. The P21 / ACZ pin is the input pin of AC zero-cross detector circuit. AC zero-cross detector circuit output the high level when the input level is at the middle, and outputs the low level at other level.
Page 149 AC Zero-Cross Detector Setup Example (External interrupt 1) AC zero-cross detector generates the external interrupt 1 (IRQ1) by using P21/ACZ pin. An example setup procedure, with a description of each step is shown below. Setup Procedure Select the AC zero-cross detector signal.
Page 151: Chapter 4 I/O Ports
Chapter 4 I/O Ports...
Page 152: Overview
Chapter 4 I/O Ports Overview 4-1-1 I/O Port Diagram A total of 54 pins on this LSI, including those shared with special function pins, are allocated for the 8 I/O ports of ports 0 to 2, ports 5 to 8 and port A. Each I/O port is assigned to its corresponding special function register area in memory.
Page 153: I/O Port Status At Reset
4-1-2 I/O Port Status at Reset Table 4-1-1 Port Name I/O mode Port 0 Input mode Port 1 Input mode Port 2 Input mode Port 5 Input mode Port 6 Input mode Port 7 Input mode Port 8 Input mode Port A Input mode I/O Port Status at Reset (Single chip mode)
Page 154: Control Registers
Chapter 4 I/O Ports 4-1-3 Control Registers Ports 0 to 2, ports 5 to 8 and port A are controlled by the data output register (PnOUT), the data input register (PnIN), the I/O direction control register (PnDIR), the pull-up resistor control register (PnPLU) and the pull-up / pull-down resistor control resister (PnPLUD) and registers (P1OMD, P1TCNT, PAIMD, FLOAT) that control special function pin.
Page 155 Table 4-1-3 I/O Port Control Registers List (2/2) Register Address P7OUT x'03F17' P7IN x'03F27' Port 7 P7DIR x'03F37' P7PLUD x'03F47' P8OUT x'03F18' P8IN x'03F28' Port 8 P8DIR x'03F38' P8PLU x'03F48' P8LED x'03F1D' PAOUT x'03F1A' PAIN x'03F2A' Port A PADIR x'03F3A' PAPLUD x'03F4A' PAIMD...
Page 156: Description
Chapter 4 I/O Ports Port 0 4-2-1 Description General Port Setup Each bit of the port 0 control I/O direction register (P0DIR) can be set individually to set each pin as input or output. The control flag of the port 0 direction control register (P0DIR) should be set to "1" for output mode, and "0"...
Page 157: Registers
4-2-2 Registers P0OUT P0OUT6 P0OUT5 P0OUT4 P0OUT3 P0OUT2 P0OUT1 P0OUT0 Port 0 output register (P0OUT : x'03F10', R/W) P0IN P0IN6 P0IN5 P0IN4 Port 0 input register (P0IN : x'03F20', R) P0DIR P0DIR6 P0DIR5 P0DIR4 P0DIR3 P0DIR2 P0DIR1 P0DIR0 Port 0 direction control register (P0DIR : x'03F30', R/W) P0PLU P0PLU6 P0PLU5 P0PLU4 P0PLU3 P0PLU2 P0PLU1 P0PLU0...
Page 158: Block Diagram
Chapter 4 I/O Ports 4-2-3 Block Diagram Pull-up resistor control I/O direction control Port output data Port input data Serial interface 1 transmission data output/ UART transmission data output SC1MD1 register SC1SBOS flag Nch open-drain control Pull-up resistor control I/O direction control Port output data Port input data Serial interface 4 transmission data output...
Page 159: Block Diagram
Nch open-drain control Pull-up resistor control I/O direction control Port output data Port input data Serial interface 1 clock input Serial interface 4 clock input Serial interface 1 clock output Serial interface 4 clock output SC1MD1 register SC1SBTS flag SC4AD1 register SELI2C flag Nch open-drain control Pull-up resistor control...
Page 160 Chapter 4 I/O Ports Pull-up resistor control I/O direction control Port output data Port input data Serial interface 0 reception data input UART reception data input Nch open-drain control Write Pull-up resistor control Write I/O direction control Write Port output data Write Port input data Serial interface 0 clock input...
Page 161 Reset Pull-up resistor control Write Reset I/O direction control Write Reset Port output data Write Port input data Buzzer output DLYCTR register bp7 P0PLU6 Read P0DIR6 Read P0OUT6 Read P0IN6 Read Figure 4-2-8 Block Diagram (P06) Chapter 4 I/O Ports IV - 11 Port 0...
Page 162: Description
Chapter 4 I/O Ports Port 1 4-3-1 Description General Port Setup Each bit of the port 1 control I/O direction register (P1DIR) can be set individually to set pins as input or output. The control flag of the port 1 direction control register (P1DIR) should be set to "1" for output mode, and "0"...
Page 163 4-3-2 Registers P1OUT4 P1OUT Port 1 output register (P1OUT : x'03F11', R/W) P1IN P1IN4 Port 1 input register (P1IN : x'03F21', R) P1DIR4 P1DIR Port 1 direction control register (P1DIR : x'03F31', R/W) P1PLU4 P1PLU Port 1 pull-up resistor control register (P1PLU : x'03F41', R/W) P1OUT3 P1OUT2 P1OUT1 P1OUT0 ( At reset : - - - 0 0 0 0 0 ) ( At reset : - - - X X X X X )
Page 164 Chapter 4 I/O Ports P1OMD P1OMD6 P1OMD5 P1OMD4 Port 1 output mode register (P1OMD: X'03F2F', R/W) IV - 14 Port 1 ( At reset : - 0 0 0 0 0 0 0 ) P1OMD3 P1OMD2 P1OMD1 P1OMD0 Figure 4-3-2 Port 1 Registers (2/3) P1OMD0 P10 output mode selection I/O port...
Page 165 P1TCNT P1CNT5 P1CNT4 P10 Output Control register ( P1TCNT : X'03F7E', R/W) P1CNT3 P1CNT2 P1CNT1 P1CNT0 Figure 4-3-3 Port 1 Registers (3/3) Chapter 4 I/O Ports (At reset : - - 0 0 0 0 0 0 ) P10 Output Control P1CNT1 P1CNT0 I/O port...
Page 166 Chapter 4 I/O Ports 4-3-3 Block Diagram External interrupt 0 (IRQ0) Reset Pull-up resistor control Write Reset I/O direction control Write Port output data Write Reset Output mode control Write Reset Output control Write Port input data Read Timer input Timer output Figure 4-3-4 Pull-up resistor control...
Page 167 Port 2 4-4-1 Description General Port Setup Each bit of the port 2 control I/O direction register (P2DIR) can be set individually to set pins as input or output. The control flag of the port 2 direction control register (P2DIR) should be set to "1" for output mode, and "0"...
Page 168 Chapter 4 I/O Ports 4-4-2 Registers P2OUT P2OUT7 Port 2 output register(P2OUT : x'02F12', R/W) P2IN P2IN7 Port 2 input register(P2IN : x'02F22', R) P2DIR Port 2 direction control register (P2DIR : x'02F32', R/W) P2PLU Port 2 pull-up resistor control register(P2PLU : x'02F42', R/W) IV - 18 Port 2 P2OUT4 P2OUT3 P2OUT2 P2OUT1 P2OUT0...
Page 169: Block Diagram
4-4-3 Block Diagram Reset Pull-up resistor control Write Reset I/O direction control Write Reset Port outut data Write Port input data Read External interrupt Figure 4-4-2 Pull-up resistor control Write Reset I/O direction control Write Reset Port output data Write Port input data NFCTR register bp7 AC zero-cross input...
Page 170: Block Diagram
Chapter 4 I/O Ports Port output data Port input data Reset IV - 20 Port 2 Reset P2OUT7 Write Read Reset P2IN7 Read Schmitt trigger input Noise filter Figure 4-4-4 Block Diagram (P27)
Page 171: Description
Port 5 4-5-1 Description General Port Setup Each bit of the port 5 control I/O direction register (P5DIR) can be set individually to set pins as input or output. The control flag of the port 5 direction control register (P5DIR) is set to "1" for output mode, and "0"...
Page 172: Registers
Chapter 4 I/O Ports 4-5-2 Registers P5OUT Port 5 output register (P5OUT : x'03F15', R/W) P5IN Port 5 input register (P5IN : x'03F25', R) P5DIR Port 5 direction control register (P5DIR : x'03F35', R/W) P5PLU Port 5 pull-up resistor control register (P5PLU : x'03F45', R/W) IV - 22 Port 5 P5OUT4 P5OUT3 P5OUT2 P5OUT1 P5OUT0...
Page 173 4-5-3 Block Diagram Pull-up resistor control I/O direction control Port output data Port input data Serial interface 3 reception data input Nch open-drain control Pull-up resistor control I/O direction control Port output data Port input data Serial interface 3 transmission output SC3MD1 register SC3SBOS flag Reset...
Page 174: Block Diagram
Chapter 4 I/O Ports Nch open-drain control Pull-up resistor control I/O direction control Port output data Port input data Serial interface 3 clock input Serial interface 3 clock output SC3MD1 register SC3SBTS flag Nch open-drain control Pull-up resistor control I/O direction control Port output data Port input data Serial interface 4 reception data input...
Page 175: Registers
Nch open-drain control Write Pull-up resistor control Write I/O direction control Write Port output data Write Port input data Serial interface 4 clock input Serial interface 4 clock output SC4AD1 register SELI2C flag Reset SC4ODC11 Read Reset P5PLU4 Read Reset P5DIR4 Read Reset...
Page 176 Chapter 4 I/O Ports Port 6 4-6-1 Description General port Setup Each bit of the port 6 control I/O direction register (P6DIR) can be set individually to set pins as input or output. The control flag of the port 6 direction control register (P6DIR) is set to "1" for output mode, and "0"...
Page 177 4-6-2 Registers P6OUT P6OUT7 P6OUT6 P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0 Port 6 output register (P6OUT : x'03F16', R/W) P6IN P6IN7 P6IN6 P6IN5 P6IN4 Port 6 intput register (P6IN : x'03F26', R) P6DIR P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIR0 Port 6 direction control register (P6DIR : x'03F36', R/W) P6PLU P6PLU7...
Page 178 Chapter 4 I/O Ports P6SYO P6SYO5 P6SYO7 P6SYO6 Port 6 Synchronous Output Control Register (P6SYO:X'03F1E', R/W) FLOAT PARDWN Pull-up/pull-down resistor selection, pin control register (FLOAT: X'03F2E', R/W) IV - 28 Port 6 P6SYO0 P6SYO4 P6SYO3 P6SYO2 P6SYO1 P7RDWN SYOEVS1SYOEVS0 Figure 4-6-2 Port 6 Registers (2/2) ( At Reset: 0 0 0 0 0 0 0 0 ) I/O port, P6SYO...
Page 179 4-6-3 Block Diagram Reset Pull-up resistor control Write Reset I/O direction control Write Reset Port output data Write Port input data Syncronous output control Write Figure 4-6-3 Block Diagram (P60 to P67) P6PLU0-7 Read P6DIR0-7 Read Reset P6OUT0-7 Read P6IN0-7 Read Syncronous output event Reset...
Page 180 Chapter 4 I/O Ports Port 7 4-7-1 Description General Port Setup Each bit of the port 7 control I/O direction register (P7DIR) can be set individually to set pins as input or output. The control flag of the port 5 direction control register (P7DIR) is set to "1" for output mode, and "0"...
Page 181 4-7-2 Registers P7OUT P7OUT7 P7OUT6 P7OUT5 P7OUT4 P7OUT3 P7OUT2 P7OUT1 P7OUT0 Port 7 output register (P7OUT : x'03F17', R/W) P7IN P7IN7 P7IN6 P7IN5 P7IN4 Port 7 input register (P7IN : x'03F27', R) P7DIR P7DIR7 P7DIR6 P7DIR5 P7DIR4 P7DIR3 P7DIR2 P7DIR1 P7DIR0 Port 7 direction control register (P7DIR : x'03F37', R/W) P7PLUD P7PLUD7...
Page 182 Chapter 4 I/O Ports FLOAT PARDWN P7RDWN Pull-up / Pull-down resistor selection, Pin control register (FLOAT : x'03F2E', R/W) IV - 32 Port 7 SYOEVS1 SYOEVS0 ( At reset : - 0 - 0 - - 0 0 ) Figure 4-7-2 Port 7 Registers (2/2) P7 Synchronous output SYOEVS1 SYOEVS0...
Page 183 4-7-3 Block Diagram Nch open-drain control Pull-up/down resistor control Pull-up/down resistor selection I/O direction control Port output data Port input data Serial interface 0 transmission data output UART transmission data output SC0MD1 register SC0SBOS flag Pull-up/down resistor control Write Pull-up/down resistor selection Write I/O direction control Write...
Page 184 Chapter 4 I/O Ports Nch open-drain control Write Pull-up/down resistor control Write Pull-up/down resistor selection Write I/O direction control Write Port output data Port input data Serial interface 0 clock input Serial interface 0 clock output SC0MD1 register SC0SBOS flag Pull-up/down resistor control Pull-up/down resistor selection I/O direction control...
Page 185 Pull-up/down resistor control Write Pull-up/down resistor selection Write I/O direction control Write Port output data Write Port input data Serial interface 1 reception data output UART reception data output Pull-up/down resistor control Write Pull-up/down resistor selection Write I/O direction control Write Port output data Write...
Page 186 Chapter 4 I/O Ports Pull-up/down resistor control Write Pull-up/down resistor selection Write I/O direction control Write Port output data Write Output mode control Write Port input data Timer input Timer output IV - 36 Port 7 Reset P7PLUD6,7 Read Reset FLOAT(bp4) Read Reset...
Page 187 Chapter 4 I/O Ports 4-8 Port 8 4-8-1 Description General Port Setup Each bit of the port 8 control I/O direction register (P8DIR) can be set individually to set each pin as input or output. The control flag of the port 8 direction control register (P8DIR) is set to "1" for output mode, and "0"...
Page 188: Registers
Chapter 4 I/O Ports 4-8-2 Registers P8OUT P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUT0 Port 8 output register (P8OUT : x'03F18', R/W) P8IN P8IN7 P8IN6 P8IN5 Port 8 input register (P8IN : x'03F28', R) P8DIR P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIR0 Port 8 direction control register (P8DIR : x'03F38', R/W) P8PLU P8PLU7...
Page 189 P8LED P8LED7 P8LED6 P8LED5 P8LED4 P8LED3 P8LED2 P8LED1 P8LED0 Port 8 LED Control register (P8LED : x'03F1D', R/W) ( At reset : 0 0 0 0 0 0 0 0 ) Figure 4-8-2 Port 8 Registers (2/2) Chapter 4 I/O Ports P8LED Transistor selection Normal output...
Page 190 Chapter 4 I/O Ports 4-8-3 Block Diagram Pull-up resistor control Write I/O direction control Write Port output data Write Function switching output buffer Write Port input data IV - 40 Port 8 Reset P8PLU0-7 Read Reset P8DIR0-7 Read Reset P8OUT0-7 Read Reset P8LED0-7...
Page 191: Port A
Port A 4-9-1 Description General Port Setup Each bit of the port A control I/O direction register (PADIR) can be set individually to set each pin as input or output. The control flag of the port A direction control register (PADIR) should be set to "1" for output mode, and "0"...
Page 192: Registers
Chapter 4 I/O Ports 4-9-2 Registers PAOUT PAOUT6 PAOUT5 PAOUT4 PAOUT3 PAOUT2 PAOUT1 PAOUT0 Port A output register (PAOUT: X'03F1A', R/W) PAIN PAIN6 PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAIN0 Port A intput register (PAIN: X'03F2A', R) PADIR PADIR6 PADIR5 PADIR4 PADIR3 PADIR2 PADIR1 PADIR0 Port A direction control register (PADIR: X'03F3A', R/W) PAPLUD PAPLUD6...
Page 193 PAIMD PAIMD6 PAIMD5 PAIMD4 PAIMD3 PAIMD2 PAIMD1 PAIMD0 Port A Input control register (PAIMD: X'03F3C', R/W) FLOAT PARDWN P7RDWN Pull-up/pull-down resistor selection, Pin control register (FLOAT: X'03F2E', R/W) SYOEVS1 SYOEVS0 Figure 4-9-2 Port A Registers (2/2) Chapter 4 I/O Ports ( At reset: - 0 0 0 0 0 0 0 ) I/O port / PAIMD...
Page 194 Chapter 4 I/O Ports 4-9-3 Block Diagram Pull-up/down resistor control Write Pull-up/down resistor selection Write I/O direction control Write Port output data Write Write Port input data Analog input DA output Pull-up/down resistor control Write Pull-up/down resistor selection Write I/O direction control Write Port output data Write...
Page 195: Registers
4-10 Real Time Output Control (Port 1) P10 , P12 and P14 has a real time output function that can switch pin's output at the falling edge of the external interrupt 0 pin (P20/IRQ0). Real time control can change timer output signal (PWM output, timer pulse output, remote control carrier output), without setting on the program, in synchronization with external event.
Page 196: 4-10-2 Operation
Chapter 4 I/O Ports 4-10-2 Operation Real Time Output Pin Setup The real time output pin is set by the port 1 output control register(P1TCNT). The selectable pins are P10, P12 and P14. Those can be specified by each pin. Select the output mode by the port 1 direction control register (P1DIR).
Page 197 Timing P1n output (n=0, 2, 4) : Timer output P1TCNT set level : "0" (Low) output Timer output External interrupt 0 (IRQ0) PITCNT set value="0" P1n output (n=0,2,4) Figure 4-10-1 Writing to P1OUT register Real Time Output Control Timing Real Time Output Control (Port 1) Chapter 4 I/O Ports IV - 47...
Page 198: Block Diagram
Chapter 4 I/O Ports 4-11 Synchronous output (Port 6) Port 6 has the synchronous output function that outputs the any set data to pins, in synchronization with the generation of the specified event. Synchronous event is selected from the external interrupt 2 (P22/ IRQ2), timer 1 interrupt, timer 5 interrupt or timer 7 interrupt signal.
Page 199 4-11-2 Registers Table 4-11-1 shows the synchronous output control registers of port 6. Table 4-11-1 Synchronous Output Control Registers Register Address FLOAT x'03F2E' P6SYO x'03F1F' Port 6 P6DIR x'03F36' P6PLU x'03F46' P6OUT x'03F16' Function Pin control register 1 Synchronous output control register Port 6 direction control register Port 6 Pull-up/pull-down control register Port 6 output register...
Page 200: Operation
Chapter 4 I/O Ports 4-11-3 Operation Synchronous Output Setup The synchronous output control register (P6SYO) selects the synchronous output pin of the port 6, in each bit. The synchronous output event is selected by the pin control register (FLOAT). Synchronous output port Output event When the external interrupt 2 (IRQ2) is selected, the interrupt edge should be specified.
Page 201 Port 6 Synchronous Output (External interrupt 2 IRQ2)) The synchronous output timing when the synchronous output event is set at the falling edge of the external interrupt 2, is shown below. The latched data on port 6 is output in synchronization with the falling edge of the IRQ2.
Page 202: Setup Example
Chapter 4 I/O Ports 4-11-4 Setup Example A setup example of the port 6 synchronous output by the external interrupt 2 (IRQ2) is shown as follows. As it is operated, the initial output data of port 6 is "55", the synchronous output data is "AA", and the rising edge of the IRQ2 is selected at the synchronous event.
Page 203: Chapter 5 Prescaler
Chapter 5 Prescaler...
Page 204: Overview
Chapter 5 Prescaler Overview This LSI has 2 prescalers that can be used by its peripheral functions at the same time. Each of them count with fosc or fs as a base clock. Its hardware is constructed as follows ; Prescaler 0 (fosc count) Prescaler 1 (fs count) Prescaler 0 outputs fosc/2, fosc/4, fosc/16, fosc/32, fosc/64, fosc/128 as cycle clock.
Page 205: Peripheral Functions
5-1-1 Peripheral Functions Table 5-1-1 shows several kinds of clock source that can be selected by each peripheral functions from prescaler output. Table 5-1-1 Clock source External External selection interrupt 0 interrupt 1 fosc/2 fosc/4 fosc/16 fosc/32 fosc/64 fosc/128 fs/2 fs/4 fs/8 Timer 4...
Page 206 Chapter 5 Prescaler 5-1-2 Block Diagram 7bit Prescaler fosc PSC0 CK0MD TM0BAS TM0PSC0 TM0PSC1 CK1MD TM1BAS TM1PSC0 TM1PSC1 CK4MD TM4BAS TM4PSC0 TM4PSC1 CK5MD TM5BAS TM5PSC0 TM5PSC1 SC0CKS SC0PSC0 SC0PSC1 SC0PSC2 SC1CKS SC1PSC0 SC1PSC1 SC1PSC2 SC3CKS SC3PSC0 SC3PSC1 SC3PSC2 V - 4 Overview 3bit Prescaler Timer5 Out...
Page 207: Registers List
Control Register 5-2-1 Registers List Table 5-2-1 shows registers to control prescaler. Table 5-2-1 Register Address PSCMD x'03F6F' CK0MD x'03F56' CK1MD x'03F57' CK4MD x'03F66' CK5MD x'03F67' SC0CKS x'03F97' SC1CKS x'03F9F' SC3CKS x'03FAF' R/W : Readable/Writable Prescaler Control Registers Function Prescaler control register Timer 0 prescaler selection register Timer 1 prescaler selection register Timer 4 prescaler selection register...
Page 208 Chapter 5 Prescaler 5-2-2 Control Registers Registers that select prescaler outputs cycle clock and prescaler operation control, consists of the prescaler control register (PSCMD), the timer prescaler selection register (CKnMD) and the serial trans- fer clock selection register (SCnCKS). The prescaler control register controls if counting of prescaler is permitted or not. Prescaler Control Register (PSCMD) PSCMD Figure 5-2-1...
Page 209 The timer prescaler selection register selects the count clock that used in 8-bit timer. Timer 0 Prescaler Selection Register (CK0MD) CK0MD Figure 5-2-2 Timer 0 Prescaler Selection Register (CK0MD : x'03F56', R/W) Timer 1 prescaler selection register (CK1MD) CK1MD Figure 5-2-3 Timer 1 Prescaler Selection Register (CK1MD : x'03F57', R/W) TM0PSC1 TM0PSC0...
Page 210 Chapter 5 Prescaler Timer 4 Prescaler Selection Register (CK4MD) CK4MD Figure 5-2-4 Timer 4 Prescaler Selection Register (CK4MD : x'03F66', R/W) Timer 5 Prescaler Selection Register (CK5MD) CK5MD Figure 5-2-5 Timer 5 Prescaler Selection Register (CK5MD : x'03F67', R/W) V - 8 Control Registers TM4PSC1 TM4PSC0...
Page 211 The serial interface transfer clock selection register (SCnCKS) selects the transfer clock used for serial data transfer. Serial Interface 0 Transfer Clock Selection Register (SC0CKS) SC0CKS Figure 5-2-6 Serial Interface 0 Transfer Clock Selection Register (SC0CKS : x'03F97', R/W) Serial Interface 1 Transfer Clock Selection Register (SC1CKS) SC1CKS Figure 5-2-7 Serial Interface 1 Transfer Clock Selection Register (SC1CKS : x'03F9F', R/W)
Page 212 Chapter 5 Prescaler Serial Interface 3 Transfer Clock Selection Register (SC3CKS) SC3CKS Figure 5-2-8 Serial Interface 3 Transfer Clock Selection Register (SC3CKS : x'03FAF', R/W) V - 10 Control Registers Reserved SC3PSC2 SC3PSC1 SC3PSC0 SC3PSC2 ( At reset : - - - - 0 X X X ) SC3PSC1 SC3PSC0 Clock source selection...
Page 213: Operation
Operation 5-3-1 Operation Prescaler Operation (Prescaler 0 to 1) Prescaler 0 is a 7-bit and prescaler 1 is a 3-bit free-running counter that divides the base clock. This prescaler can be started or stopped by the PSCEN flag of the prescaler control register (PSCMD). Count Timing of Prescaler Operation (Prescaler 0 and 1) Prescaler 0 counts up at the falling edge of fosc.
Page 214 Chapter 5 Prescaler 5-3-2 Setup Example Prescaler Setup Example (Timer 0 count clock) Select the clock of fosc/16 that is output from the prescaler 0, to the count clock of the timer 0. An example setup procedure , with a description of each step is shown below. Setup Procedure Select the prescaler output.
Page 215: Chapter 6 8-Bit Timers
Chapter 6 8-bit Timers...
Page 216: Overview
Chapter 6 8-bit Timers Overview This LSI contains two general purpose 8-bit timers (Timers 0 and 1) and two 8-bit timers (Timers 4 and 5) that can be also used as baud rate timer. The general purpose 8-bit timers can be used as 16-bit timers with cascade connection.
Page 217: Block Diagram
Chapter 6 8-bit Timers 6-1-2 Block Diagram Timers 0 and 1 Block Diagram Figure 6-1-1 Timers 0 and 1 Block Diagram VI - 3 Overview...
Page 218 Chapter 6 8-bit Timers Timer 4 and 5 Block Diagram Figure 6-1-2 Timer 4 and 5 Block Diagram VI - 4 Overview...
Page 219: Overview
Chapter 6 8-bit Timers Remote Control Carrier Output Block Diagram Figure 6-1-3 Remote Control Carrier Output Block Diagram VI - 5 Overview...
Page 220: Control Registers
Chapter 6 8-bit Timers Control Registers Timers 0, 1, 4 and 5 consist of the binary counter (TMnBC) and the compare register (TMnOC). And they are controlled by the mode register (TMnMD). When the prescaler output is selected as the count clock source of timers 0, 1 4 and 5, they should be controlled by the prescaler control register (PSCMD) and the prescaler selection register (CKnMD).
Page 221: Control Registers
Register TM4BC TM4OC TM4MD CK4MD Timer 4 PSCMD TM4ICR P1OMD P1DIR TM5BC TM5OC TM5MD CK5MD Timer 5 PSCMD TM5ICR P1OMD P7DIR Remote control RMCTR carrier output R/W : Readable / Writable R : Readable only Address x'03F60' Timer 4 binary counter x'03F62' R/W Timer 4 compare register x'03F64'...
Page 222: Programmable Timer Registers
Chapter 6 8-bit Timers 6-2-2 Programmable Timer Registers Each of timers 0, 1, 4 and 5 has 8-bit programmable timer registers. Programmable timer register consists of compare register and binary counter. Compare register is 8-bit register which stores the value to be compared to binary counter. Timer 0 Compare Register (TM0OC) TM0OC7 TM0OC6 TM0OC5 TM0OC4 TM0OC3 TM0OC2 TM0OC1 TM0OC0 TM0OC...
Page 223 Binary counter is 8-bit up counter. If any data is written to compare register during counting is stopped, binary counter is cleared to x'00'. Timer 0 Binary Counter (TM0BC) TM0BC7 TM0BC6 TM0BC5 TM0BC4 TM0BC3 TM0BC2 TM0BC1 TM0BC0 TM0BC Figure 6-2-5 Timer 0 Binary Counter (TM0BC : x'03F50', R) Timer 1 Binary Counter (TM1BC) TM1BC7 TM1BC6 TM1BC5 TM1BC4 TM1BC3 TM1BC2 TM1BC1 TM1BC0 TM1BC...
Page 224: Timer Mode Registers
Chapter 6 8-bit Timers 6-2-3 Timer Mode Registers Timer mode register is readable/writable register that controls timers 0, 1, 4 and 5. Timer 0 Mode Register (TM0MD) TM0MD TM0MOD Figure 6-2-9 VI - 10 Control Registers TM0PWM TM0EN TM0CK2 TM0CK1 TM0CK0 Timer 0 Mode Register (TM0MD : x'03F54', R/W) ( At reset : - - 0 0 0 0 0 0 )
Page 225 Timer 1 Mode Register (TM1MD) TM1MD TM1CAS Figure 6-2-10 TM1EN TM1CK2 TM1CK1 TM1CK0 Timer 1 Mode Register (TM1MD : x'03F55', R/W) Chapter 6 8-bit Timers ( At reset : - - - 0 0 0 0 0 ) Clock source TM1CK2 TM1CK1 TM1CK0...
Page 226 Chapter 6 8-bit Timers Timer 4 Mode Register (TM4MD) TM4MD TM4MOD Figure 6-2-11 VI - 12 Control Registers TM4PWM TM4EN TM4CK2 TM4CK1 TM4CK0 Timer 4 Mode Register (TM4MD : x'03F64', R/W) ( At reset : - - 0 0 0 0 0 0 ) Clock source TM4CK2 TM4CK1...
Page 227 Timer 5 Mode Register (TM5MD) TM5MD TM5MOD TM5PWM Figure 6-2-12 TM5EN TM5CK2 TM5CK1 TM5CK0 Timer 5 Mode Register (TM5MD : x'03F65', R/W) Chapter 6 8-bit Timers ( At reset : - - 0 0 0 0 0 0 ) TM5CK2 TM5CK1 TM5CK0 Clock source...
Page 228 Chapter 6 8-bit Timers Remote Control Carrier Output Control Register (RMCTR) RMCTR Figure 6-2-13 Remote Control Carrier Output Control Register (RMCTR : x'03F6E', R/W) VI - 14 Control Registers TM0RM RMOEN RMDTY0 RMBTMS ( At reset : - - - 0 0 - 0 0 ) Remote control carrier base RMBTMS timer selection...
Page 229: Bit Timer Count
8-bit Timer Count 6-3-1 Operation The timer operation can constantly generate interrupts. 8-bit Timer Operation (Timers 0, 1, 4 and 5) The generation cycle of timer interrupts is set by the clock source selection and the setting value of the compare register (TMnOC), in advance.
Page 230 Chapter 6 8-bit Timers Count Timing of Timer Operation (Timers 0, 1, 4 and 5) Binary counter counts up with selected clock source as a count clock. The basic operation of the whole function of 8-bit timer is as follows ; Count clock TMnEN...
Page 231: Setup Example
6-3-2 Setup Example Timer Operation Setup Example (Timers 0, 1, 4 and 5) Timer function can be set by using timer 0 that generates the constant interrupt. By selecting fs/4 (at fosc = 20 MHz) as a clock source, interrupt is generated every 250 clock cycles (100 µs). An example setup procedure, with a description of each step is shown below.
Page 232 Chapter 6 8-bit Timers Setup Procedure (7) Enable the interrupt. TM0ICR (x'3FE9') :TM0IE (8) Start the timer operation. TM0MD (x'3F54') :TM0EN The TM0BC starts to count up from 'x00'. When the TM0BC reaches the setting value of the TM0OC register, the timer 0 interrupt request flag is set at the next count clock, then the value of the TM0BC becomes x'00' and restart to count up.
Page 233: Bit Event Count
8-bit Event Count 6-4-1 Operation Event count operation has 2 types ; TMnIO input and synchronous TMnIO input can be selected as the count clock. 8-bit Event Count Operation Event count means that the binary counter (TMnBC) counts the input signal from external to the TMnIO pin.
Page 234 Chapter 6 8-bit Timers Count Timing of Synchronous TMnIO Input (Timers 0, 1, 4 and 5) If the synchronous TMnIO input is selected, the synchronizing circuit output signal is input to the timer n count clock. The synchronizing circuit output signal is changed at the falling edge of the system clock after TMnIO input signal is changed.
Page 235: Setup Example
6-4-2 Setup Example Event Count Setup Example (Timers 0, 1, 4 and 5) If the falling edge of the TM0IO input pin signal is detected 5 times with using timer 0, an interrupt is generated. An example setup procedure, with a description of each step is shown below. Setup Procedure (1) Stop the counter.
Page 236 Chapter 6 8-bit Timers Setup Procedure (7) Enable the interrupt. TM0ICR (x'3FE9') :TM0IE (8) Start the event counting. TM0MD (x'3F54') :TM0EN Every time TM0BC detects the falling edge of TM0IO input , TM0BC counts up from 'x00'. When TM0BC reaches the setting value of theTM0OC register, the timer 0 interrupt request flag is set at the next count clock, then the value of TM0BC becomes x'00' and counting up is restarted.
Page 237: Bit Timer Pulse Output
8-bit Timer Pulse Output 6-5-1 Operation The TMnIO pin can output a pulse signal with any cycle. Operation of Timer Pulse Output (Timers 0, 1, 4 and 5) The timers can output 2 x cycle signal, compared to the setting value in compare register (TMnOC). Output pins are as follows ;...
Page 238 Chapter 6 8-bit Timers 6-5-2 Setup Example Timer Pulse Output Setup Example (Timers 0, 1, 4 and 5) TM0IO (P10) pin outputs 50 kHz pulse by using timer 0. For this, select fosc as clock source, and set a 1/ 2 cycle (100 kHz) for the timer 0 compare register (at fosc=20 MHz).
Page 239 TM0BC counts up from x'00'. If TM0BC reaches the setting value of the TM0OC register, then TM0BC is cleared to x'00', TM0IO output signal is inverted and TM0BC restarts to count up from x'00'. At TMnOC = x'00', timer pulse output has the same waveform to at x'01'. If any data is written to compare register binary counter is stopped, timer output is reset to "L".
Page 240: Operation
Chapter 6 8-bit Timers 8-bit PWM Output The TMnIO pin outputs the PWM waveform, which is determined by the match timing for the compare register and the overflow timing of the binary counter. 6-6-1 Operation Operation of 8-bit PWM Output (Timers 0, 4 and 5) The PWM waveform with any duty cycle is generated by setting the duty cycle of PWM "H"...
Page 241 Count Timing of PWM Output (when the compare register is x'00') (Timers 0, 4 and 5) Here is the count timing when the compare register is set to x'00' ; Count clock TMnEN flag Compare register Binary counter TMnIO output (PWM output) Figure 6-6-2 Count Timing of PWM Output (when compare register is x'00')
Page 242 Chapter 6 8-bit Timers 6-6-2 Setup Example PWM Output Setup Example (Timers 0, 4 and 5) The 1/4 duty cycle PWM output waveform is output from the TM0IO output pin at 128 Hz by using timer 0 (at fx=32.768 kH ).
Page 243 Setup Procedure (5) Set the period of PWM "H" output. TM0OC (x'3F52') (6) Start the timer operation. TM0MD (x'3F54') :TM0EN TM0BC counts up from x'00'. PWM source waveform outputs "H" till TM0BC reaches the setting value of the TM0OC register, and outputs "L" after that. Then, TM0BC continues counting up, and PWM source waveform outputs "H"...
Page 244: Bit Timer Synchronous Output
Chapter 6 8-bit Timers 8-bit Timer Synchronous Output 6-7-1 Operation When the binary counter of the timer reaches the set value of the compare register, the latched data is output from port 6 at the next count clock. Synchronous Output Operation by 8-bit timer (Timer 1, Timer 5) The port 6 latched data is output from the output pin at the interrupt request generation by the match of the binary counter and the compare register.
Page 245: Setup Example
6-7-2 Setup Example Synchronous Output Setup Example (Timer 1, Timer 5) Setup example that latch data of port 6 is output constantly (100 µs) by using timer 1 from the synchronous output pin is shown below. The clock source of timer 1 is selected fs/8 (at fosc=8 MHz). An example setup procedure, with a description of each step is shown below.
Page 246 Chapter 6 8-bit Timers Setup Procedure (7) Set the synchronous output event generation cycle. TM1OC (x'3F53') (8) Start the timer operation. TM1MD (x'3F55') :TM1EN TM1BC counts up from x'00'. If any data is written to the port 6 output register (P6OUT), the data of port 6 is output from the synchronous output pin in every time an interrupt request is generated by the match of TM1BC and the set value of the TM1OC register.
Page 247: Serial Interface Transfer Clock Output
Serial Interface Transfer Clock Output 6-8-1 Operation Serial interface transfer clock can be created by using the timer output signal. Serial InterfaceTransfer Clock Operation by 8-bit Timer (Timers 4 and 5) Timer 4 output can be used as a transfer clock source for serial interface 1. Timer 5 output can be used as a transfer clock source for serial interface 0.
Page 248: Setup Example
Chapter 6 8-bit Timers 6-8-2 Setup Example Serial Interface Transfer Clock Setup Example (Timer 4) How to create a transfer clock for half duplex UART (Serial interface 1) using with timer 4 is shown below. The baud rate is selected to be 300 bps, the source clock of timer 4 is selected to be fs/4 (at fosc=8 MHz).
Page 249 Chapter 6 8-bit Timers TM4BC counts up from x'00'. Timer 4 output is the clock of the serial interface 1 at transmission and reception. For the compare register setup value and the serial operation setup, refer to chapter 11. Serial Interface 0,1.
Page 250: Operation
Chapter 6 8-bit Timers Simple Pulse Width Measurement 6-9-1 Operation Timer measures the "L" duration of the pulse signal input from the external interrupt pin. Simple Pulse Width Measurement Operation by 8-bit Timer (Timers 0, 4 and 5) During the input signal of the external interrupt pin (simple pulse width) is "L", the binary counter of the timer counts up.
Page 251: Setup Example
6-9-2 Setup Example Set up Example of Simple Pulse Width Measurement by 8-bit Timer (Timers 0, 4 and 5) The pulse width of 'L" period of the external interrupt 2 (IRQ2) input signal is measured by timer 0. The clock source of timer 0 is selected to fosc. An example setup procedure, with a description of each step is shown below.
Page 252 Chapter 6 8-bit Timers Setup Procedure (7) Enable the interrupt. IRQ2ICR (x'3FE4') :IRQ2IE (8) Enable the timer operation. TM0MD (x'3F54') :TM0EN TM0BC starts to count up with negative edge of the external interrupt 2 (IRQ2) input as a trigger. Timer 0 continues to count up during "L" period of IRQ2 input, then stop the counting with positive edge of IRQ2 input as a trigger.
Page 253: Cascade Connection
6-10 Cascade Connection 6-10-1 Operation Cascading timers 0 and 1 form a 16-bit timer. 8-bit Timer Cascade Connection Operation (Timer 0 + Timer 1) Timer 0 and timer 1 are combined to be a 16-bit timer. Cascading timer is operated at clock source of timer 0 which is lower 8 bits.
Page 254 Chapter 6 8-bit Timers At cascade connection, the binary counter and the compare register are operated as a 16 bit regis- ter. At operation, set the TMnEN flag of the upper and lower 8-bit timers to "1" to be operated. Also, the clock source is the one which is selected in the lower 8-bit timer.
Page 255: Setup Example
6-10-2 Setup Example Cascade Connection Timer Setup Example (Timer 0 + Timer 1) Setting example of timer function that an interrupt is constantly generated by cascade connection of timer 0 and timer 1, as a 16-bit timer is shown. An interrupt is generated in every 2500 cycles (1 ms) by selecting source clock to fs/4 (fosc=20 MHz at operation).
Page 256 Chapter 6 8-bit Timers Setup Procedure Disable the lower timer interrupt. TM0ICR (x'3FE9') :TM0IE Set the level of the upper timer interrupt. TM1ICR (x'3FEA') bp7-6 :TM1LV1-0 = 10 Enable the upper timer interrupt. TM1ICR (x'3FEA') :TM1IE (10) Start the upper timer operation. TM1MD (x'3F55') :TM1EN (11) Start the lower timer operation.
Page 257: Remote Control Carrier Output
6-11 Remote Control Carrier Output 6-11-1 Operation Carrier pulse for remote control can be generated. Operation of Remote Control Carrier Output (Timer 0, Timer 5) Remote control carrier pulse is based on output signal of timer 0 or timer 5. Duty cycle is selected from 1/ 2, 1/3.
Page 258: Setup Example
Chapter 6 8-bit Timers 6-11-2 Setup Example Remote Control Carrier Output Setup Example (Timer 0, Timer 5) Here is the setting example that the RMOUT pin outputs the 1/3 duty carrier pulse signal with "H" period of 36.7 kHz, by using timer 0. The source clock of timer 0 is set to fosc (at 8 MHz). An example setup procedure, with a description of each step is shown below.
Page 259 Setup Procedure (6) Select the normal timer operation. TM0MD (x'3F54') : TM0PWM = 0 : TM0MOD = 0 (7) Select the count clock source. TM0MD (x'3F54') bp2-0 : TM0CK2-0 = 000 (8) Set the base cycle of remote control carrier. TM0OC (x'3F52') (9) Start the timer operation.
Page 261: Chapter 7 16-Bit Timer
Chapter 7 16-bit Timer...
Page 262: Overview
Chapter 7 16-bit Timer Overview This LSI contains a general-purpose 16-bit timer (Timer 7). Its compare register is double buffer type. Timer 7 (high function 16-bit timer) has 2 sets of compare registers with double buffering. Also, as an independent interrupt it has a timer 7 interrupt and a timer 7 compare register 2 match interrupt. 7-1-1 Functions Table 7-1-1 shows the functions of timer 7.
Page 263: Block Diagram
Chapter 7 16-bit Timer 7-1-2 Block Diagram Timer 7 Block Diagram Figure 7-1-1 Timer 7 Block Diagram VII - 3 Overview...
Page 264: Control Registers
Chapter 7 16-bit Timer Control Registers Timer 7 contains the binary counter (TM7BC), the compare register 1 (TM7OC1), and its double buffer preset register (TM7PR1), the compare register 2 (TM7OC2) and its double buffer preset register 2 (TM7PR2), the capture register (TM7IC). The mode register 1 (TM7MD1) and the mode register 2 (TM7MD2) controls timer 7.
Page 265: Programmable Timer Registers
7-2-2 Programmable Timer Registers Timer 7 has a 16-bit programmable timer register. It contains a compare register, a preset register, a binary counter and a capture register. Each register has 2 sets of 8-bit register. Operate by 16-bit ac- cess. Compare register is a 16-bit register stores the value that compared to binary counter.
Page 266 Chapter 7 16-bit Timer The timer 7 preset register 1 and 2 are buffer registers of the timer 7 compare register 1 and 2. If the set value is written to the timer 7 preset register 1 and 2 when the counting is stopped, the same set value is loaded to the timer 7 compare register 1 and 2.
Page 267 Binary counter is a 16-bit up counter. If any data is written to a preset register when the counting is stopped, the binary counter is cleared to x'0000'. Timer 7 Binary Counter (TM7BC) TM7BCL TM7BCL7 TM7BCL6 TM7BCL5 TM7BCL4 TM7BCL3 TM7BCL2 TM7BCL1 TM7BCL0 Figure 7-2-9 Timer 7 Binary Counter Lower 8 bits (TM7BCL : x'03F70', R) TM7BCH...
Page 268: Timer Mode Registers
Chapter 7 16-bit Timer 7-2-3 Timer Mode Registers This is a readable / writable register that controls timer 7. Timer 7 Mode Register 1 (TM7MD1) TM7MD1 RESERVED TM7CL RESERVED Figure 7-2-13 VII - 8 Control Registers TM7EN TM7PS1 TM7PS0 TM7CK1 TM7CK0 Timer 7 Mode Register 1 (TM7MD1 : x'03F78', R/W) ( At reset : 0 0 1 0 0 0 0 0 )
Page 269 Timer 7 Mode Register 2 (TM7MD2) TM7MD2 T7ICEDG T7PWMSL TM7BCR TM7PWM Figure 7-2-14 TM7IRS1 T7ICEN T7ICT1 T7ICT0 Timer 7 Mode Register 2 (TM7MD2 : x'03F79', R/W) Chapter 7 16-bit Timer ( At reset : 0 0 0 0 0 0 0 0 ) Capture trigger selection T7ICT1 T7ICT0...
Page 270: Bit Timer Count
Chapter 7 16-bit Timer 16-bit Timer Count 7-3-1 Operation The timer operation can constantly generate interrupts. 16-bit Timer Operation (Timer 7) The generation cycle of an timer interrupt is set by the clock source selection and the set value of the compare register 1 (TM7OC1), in advance.
Page 271 Table 7-3-2 shows the clock source that can be selected. Table 7-3-2 Count Timing of Timer Operation (Timer 7) The binary counter counts up with the selected clock source as the count clock. The basic operation of the whole function of 16-bit timer is as follows ; Count clock TM7EN...
Page 272 Chapter 7 16-bit Timer Even if the preset register is rewritten as the TM7EN flag is "1", the binary counter is not changed. If the binary counter reaches the value of the compare register 1, the set value of the preset register is loaded to the compare register at the next count clock.
Page 273 7-3-2 Setup Example Timer Operation Setup Example (Timer 7) Timer 7 generates an interrupt constantly for timer function. Fosc/2 (fosc=20 MHz) is selected as a clock source to generate an interrupt every 1000 cycles (100 µs). An example setup procedure, with a description of each step is shown below. Setup Procedure (1) Stop the counter.
Page 274 Chapter 7 16-bit Timer Setup Procedure (7) Start the timer operation. TM7MD1 (x'3F78') : TM7EN TM7BC counts up from x'0000'. When TM7BC reaches the set value of the TM7OC1 register, the timer 7 interrupt request flag is set to "1" at the next count clock and the TM7BC becomes x'0000' and counts up, again.
Page 275: Bit Event Count
16-bit Event Count 7-4-1 Operation Event count operation has 2 types ; TM7IO input and synchronous TM7IO input can be selected as the count clock. Each type can select 1/1, 1/2, 1/4 or 1/6 as a count clock source. 16-bit Event Count Operation (Timer 7) Event count means that the binary counter (TM7BC) counts the input signal from external to the TM7IO pin.
Page 276 Chapter 7 16-bit Timer Count Timing of Synchronous TM7IO Input (Timer 7) If the synchronous TM7IO input is selected, the synchronizing circuit output signal is input to the count clock. The synchronizing circuit output signal is changed at the falling edge of the system clock after the TM7IO input signal is changed.
Page 277: Setup Example
7-4-2 Setup Example Event Count Setup Example (Timer 7) If the falling edge of the TM7IO input pin signal is detected 5 times with using timer 7, an interrupt is generated. An example setup procedure, with a description of each step is shown below. Setup Procedure (1) Stop the counter.
Page 278 Chapter 7 16-bit Timer Setup Procedure (6) Set the interrupt level. TM7ICR (x'3FF1') bp7-6 :TM7LV1-0 = 10 (7) Enable the interrupt. TM7ICR (x'3FF1') : TM7IE (8) Start the event count. TM7MD1 (x'3F78') : TM7EN Every time TM7BC detects the falling edge of the TM7IO input, TM7BC counts up from x'0000'. When the TM7BC reaches the setting value of the TM7OC1 register, the timer 7 interrupt request flag is set at the next count clock, then the value of TM7BC becomes x'0000' and counting up is restarted.
Page 279: Operation
16-bit Timer Pulse Output 7-5-1 Operation TM7IO pin can output a pulse signal with an arbitrary frequency. 16-bit Timer Pulse Output Operation (Timer 7) The timers can output 2 x cycle signal, compared to the setting value to the compare register 1 (TM7OC1) or 1/2 the frequency of the 16-bit full count.
Page 280 Chapter 7 16-bit Timer Count Timing of Timer Pulse Output (Timer 7) Count clock TM7EN flag Compare register 1 Binary 0000 0001 counter Interrupt request flag TM7IO output Figure 7-5-1 The TM7IO pin outputs 2 x cycle, compared to the value in the compare register 1. If the binary counter reaches the compare register, and the binary counter is cleared to x'0000' or the full count overflow, the TM7IO output (timer output) is inverted.
Page 281 7-5-2 Setup Example Timer Pulse Output Setup Example (Timer 7) TM7IO pin outputs 50 kHz pulse by using timer 7. For this, select fosc as clock source, and set a 1/2 cycle (100 kHz) for the timer 7 compare register (at fosc=20 MHz). An example setup procedure, with a description of each step is shown below.
Page 282 Chapter 7 16-bit Timer Setup Procedure Set the timer pulse output cycle. TM7PR1 (X'3F75', X'3F74')=x'00C7' Release the reset of the timer pulse output. TM7MD1 (x'3F78') : TM7CL Start the timer operation. TM7MD1 (x'3F78') : TM7EN TM7BC counts up from x'0000'. If TM7BC reaches the set value of the TM7OC1 register and TM7BC is cleared to x'0000', the signal of the TM7IO output is inverted and TM7BC counts up from x'0000', again.
Page 283: 16-Bit Standard Pwm Output
16-bit Standard PWM Output (Only duty can be changed consecutively) The TM7IO pin outputs the standard PWM output, which is determined by the over flow timing of the binary counter, and the match timing of the timer binary counter and the compare register. 7-6-1 Operation 16-bit Standard PWM Output (Timer 7)
Page 284 Chapter 7 16-bit Timer Count Timing of Standard PWM Output (when Compare Register 1 is x'0000')(Timer 7) Here is the count timing at setting x'0000' to the compare register 1. Count clock TM7EN flag Compare regsiter 1 Binary 0000 0001 counter TM7IO output (PWM output)
Page 285: Operation
7-6-2 Setup Example Standard PWM Output Setup Example (Timer 7) The TM7IO output pin outputs the 1/4 duty PWM output waveform at 305.18 Hz with timer 7. The high frequency oscillation (fosc) is set to be operated at 20 MHz. One cycle of the PWM output waveform is decided by the overflow of a binary counter.
Page 286 Chapter 7 16-bit Timer Setup Procedure Select the count clock source. TM7MD1 (x'3F78') bp1-0 : TM7CK1-0 = 00 bp3-2 : TM7PS1-0 = 00 Set "H" period of the PWM output. TM7PR1 (x'3F75', x'3F74')=x'4000' Start the timer operation. TM7MD1 (x'3F78') : TM7EN TM7BC counts up from x'0000'.
Page 287: Operation
16-bit High Precision PWM Output (Cycle/Duty can be changed consecutively) The TM7IO pin outputs high precision PWM output, which is determined by the match timing of the timer binary counter and the compare register 1 and the match timing of the binary counter and the compare register 2.
Page 288 Chapter 7 16-bit Timer Count Timing of High Precision PWM Output (When compare register 2 is x'0000'l) (Timer 7) Here is the count timing as the compare register 2 is set to x'0000' ; Count clock TM7EN flag Compare register 1 Compare register 2 Binary...
Page 289 7-7-2 Setup Example High Precision PWM Output Setup Example (Timer 7) The TM7IO output pin outputs the 1/4 duty PWM output waveform at 400 Hz with timer 7. Select fosc/2 (at fosc = 20 MHz) as a clock source. One cycle of the PWM output waveform is decided by the set value of a compare register 1.
Page 290 Chapter 7 16-bit Timer Setup Procedure Select the count clock source. TM7MD1 (x'3F78') bp1-0 : TM7CK1-0 = 00 bp3-2 : TM7PS1-0 = 01 Set the PWM output cycle. TM7PR1 (x'3F75',x'3F74') = x'61a7' Set the "H" period of the PWM output. TM7PR2 (x'3F7D',x'3F7C')=x'186a' Start the timer operation.
Page 291: Bit Timer Synchronous Output
16-bit Timer Synchronous Output 7-8-1 Operation When the binary counter of the timer reaches the set value of the compare register, the latched data is output from port 6 at the next count clock. Synchronous Output Operation by 16-bit Timer (Timer 7) The port 6 latched data is output from the output pin at the interrupt request generation by the match of the binary counter (TM7OC1) or by the full count overflow.
Page 292: Setup Example
Chapter 7 16-bit Timer 7-8-2 Setup Example Synchronous Output Setup Example (Timer 7) Setup example that latched data of port 6 is output constantly (100 µs) by using timer 7 from the synchro- nous output pin is shown below. The clock source of timer 7 is selected fs/4 (at fosc=8 MHz). An example setup procedure, with a description of each step is shown below.
Page 293 Setup Procedure (7) Start the timer operation. TM7MD1 (x'3F78') : TM7EN TM7BC counts up from x'0000'. If any data is written to the port 6 output register (P6OUT), TM7BC reaches the set value of TM7OC1 register and the synchronous output pin outputs data of port 7 in every time an interrupt request is generated.
Page 294: 16-Bit Timer Capture
Chapter 7 16-bit Timer 16-bit Timer Capture 7-9-1 Operation The value of a binary counter is stored to register at the timing of the external interrupt input signal, or the timing of writing operation with an arbitrary value to the capture register. Capture Operation with External Interrupt Signal as a Trigger (Timer 7) Capture trigger of input capture function is generated at the external interrupt signal that passed through the external interrupt interface block.
Page 295 with the automatic data transfer function (ATC1). In the transfer mode 5 of ATC1, set the address of the input capture register TM7ICL to the memory pointer 1. The "H" period and "L" period of the input signal can be measured by transferring the value of the input capture register (TM7ICL, TM7ICH) to memory in every generation of a capture trigger.
Page 296 Chapter 7 16-bit Timer In the initial state after releasing the reset, the generation of trigger by the external interrupt signal is disabled. Set the T7ICEN flag of the TM7MD2 register to "1" to enable the trigger generation. Capture Operation that the writing to program is selected as a Trigger (Timer 7) A capture trigger can be generated by writing an arbitrary value to the input capture register (TM7IC), and at the same timing, the value of the binary counter can be stored to the input capture register.
Page 297 7-9-2 Setup Example Capture Function Setup Example (Timer 7) Pulse width measurement is enabled by storing the value of the binary counter to the capture register at the interrupt generation edge of the external interrupt 0 input signal with timer 7. The interrupt generation edge is specified to be the rising edge.
Page 298 Chapter 7 16-bit Timer Setup Procedure (6) Select the capture trigger generation edge. TM7MD2 (x'3F79') : T7ICEDG = 1 (7) Set the compare register. TM7PR1(x'3F75',x'3F74') = x'FFFF' (8) Set the interrupt level. IRQ0ICR (x'3FE2') bp7-6 : IRQ0LV1-0= 10 (9) Enable the interrupt. IRQ0ICR (x'3FE2') : IRQ0IE (10) Enable the capture trigger...
Page 299: Chapter 8 Time Base Timer / 8-Bit Free-Running Timer
Chapter 8 Time Base Timer / 8-bit Free-running Timer...
Page 300: Overview
Chapter 8 Time Base Timer / 8-bit Free-running Timer Overview This LSI has a time base timer and a 8-bit free-running timer (timer 6). Time base timer is a 15-bit timer counter. These timers can stop the timer counting only at stand-by mode (STOP mode).
Page 301: Block Diagram
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-1-2 Block Diagram Timer 6, Time Base Timer Block Diagram Figure 8-1-1 Block Diagram (Timer 6, Time Base Timer) VIII - 3 Overview...
Page 302: Control Registers
Chapter 8 Time Base Timer / 8-bit Free-running Timer Control Registers Timer 6 consists of binary counter (TM6BC), compare register (TM6OC), and is controlled by mode register (TM6MD). Time base timer is controlled by mode register (TM6MD) and time base timer clear register (TBCLR), too.
Page 303 8-2-2 Programmable Timer Registers Timer 6 is a 8-bit programmable counter. Programmable counter consists of compare register (TM6OC) and binary counter (TM6BC). Binary counter is a 8-bit up counter. When the TM6CLRS flag of the timer 6 mode register (TM6MD) is "0"...
Page 304: Control Registers
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-2-3 Timer Mode Registers This is a readable / writable register that controls timer 6 and time base timer. Timer 6 Mode Register (TM6MD) TM6MD TM6CLRS TM6IR2 TM6IR1 Figure 8-2-4 VIII - 6 Control Registers TM6IR0 TM6CK3...
Page 305: 8-Bit Free-Running Timer
8-bit Free-running Timer 8-3-1 Operation 8-bit Free-running Timer (Timer 6) The generation cycle of the timer interrupt is set by the clock source selection and the setting value of the compare register (TM6OC), in advance. If the binary counter (TM6BC) reaches the setting value of the compare register, an interrupt is generated at the next count clock, then the binary counter is cleared and counting is restarted from x'00'.
Page 306 Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-bit Free-running Timer as a 1 minute-timer, a 1 second-timer Table 8-3-2 shows the clock source selection and the TM6OC register setup, when a 8-bit free-running timer is used as a 1 minute-timer, a 1 second-timer. Table 8-3-2 Interrupt Generation Cycle...
Page 307: Operation
Count Timing of Timer Operation (Timer 6) Binary counter counts up with the selected clock source as a count clock. Count clock TM6CLRS flag Compare register Binary 02/00 counter Interrupt request flag Figure 8-3-2 When any data is written to the compare register as the TM6CLRS flag is "0", the binary counter is cleared to x'00'.
Page 308: Setup Example
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-3-2 Setup Example Timer Operation Setup (Timer 6) Timer 6 generates an interrupt constantly for timer function. Fs(fosc = 20 MHz) is selected as a clock source to generate an interrupt every 250 cycles (25 µs). An example setup procedure, with a description of each step is shown below.
Page 309 Chapter 8 Time Base Timer / 8-bit Free-running Timer If the TM6CLRS flag of the TM6MD register is set to "0", TM6BC can be initialized in every rewriting of TM6OC register, but in that state the timer 6 interrupt is disabled. If the timer 6 interrupt should be enabled, set the TM6CLRS flag to "1"...
Page 310: Time Base Timer
Chapter 8 Time Base Timer / 8-bit Free-running Timer Time Base Timer 8-4-1 Operation Time Base Timer (Time Base Timer) The Interrupt is constantly generated. Table 8-4-1 shows the interrupt generation cycle in combination with the clock source ; Table 8-4-1 Selected clock source fosc...
Page 311 Count Timing of Timer Operation (Time Base Timer) The counter counts up with the selected clock source as a count clock. Figure 8-4-1 Count Timing of Timer Operation (Time Base Timer) When the selected interrupt cycle has passed, the interrupt request flag of the time base interrupt control register (TBICR) is set to "1".
Page 312: Setup Example
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-4-2 Setup Example Timer Operation Setup (Time Base Timer) An interrupt can be generated constantly with time base timer in the selected interrupt cycle. The inter- rupt generation cycle is as fosc An example setup procedure, with a description of each step is shown below.
Page 313: Chapter 9 Watchdog Timer
Chapter 9 Watchdog Timer...
Page 314: Overview
Chapter 9 Watchdog Timer Overview This LSI has a watchdog timer. This timer is used to detect software processing errors. It is controlled by the watchdog timer control register (WDCTR). And, once an overflow of watchdog timer is generated, a watchdog interrupt (WDIRQ) is generated.
Page 315: Control Registers
Control Registers The watchdog timer is controlled by the watchdog timer control register (WDCTR). Watchdog Timer Control Register (WDCTR) WDCTR WDTC2 WDTC1 Figure 9-2-1 Watchdog Timer Control Register (WDCTR : x'03F02', R/W) WDTC0 WDTS1 WDTS0 WDEN WDTS1 WDTC2 Chapter 9 Watchdog Timer ( At reset: - - 0 0 0 1 1 0 ) Watchdog timer enable WDEN...
Page 316: Operation
Chapter 9 Watchdog Timer Operation 9-3-1 Operation The watchdog timer counts system clock (fs) as a clock source. If the watchdog timer is overflowes, the watchdog interrupt (WDIRQ) is generated as an non maskable interrupt (NMI). At reset, the watchdog timer is stopped, but once the operation is enabled, it cannot be stopped except at reset.
Page 317 How to Clear Watchdog Timer The watchdog timer can be cleared by writing to the watchdog timer control register (WDCTR). The watchdog timer can be cleared regardless of the writing data to the register. The bit-set (BSET) that does not change the value is recommended. Watchdog Timer Period The watchdog timer period is decided by the bp2, 1 (WDTS1-0) of the watchdog timer control register (WDCTR) and the system clock (fs).
Page 318 Chapter 9 Watchdog Timer Watchdog Timer and CPU Mode The relation between this watchdog timer and CPU mode features are as follows ; (1) In NORMAL, IDLE, SLOW mode, the system clock is counted. (2) The counting is continued regardless of switching at NORMAL, IDLE, SLOW mode. (3) In HALT mode, the watchdog timer is stopped.
Page 319: Setup Example
9-3-2 Setup Example The watchdog timer detects errors. On the following example, the watchdog timer period is set to 2 system clock, the lowest value for watchdog timer clear is set to 2 An example setup procedure, with a description of each step is shown below. Initial Setup Program (Watchdog Timer Initial Setup Example) Setup Procedure (1) Set the time-out period.
Page 320 Chapter 9 Watchdog Timer Interrupt Service Routine Setup Setup Procedure (1) Set the watchdog interrupt service routine. NMICR (x'03FE1') TBNZ (NMICR) WDIR, WDPRO ..... The operation, just before the WDOG interrupt may be executed wrongly.
Page 321: Chapter 10 Buzzer
Chapter 10 Buzzer...
Page 322: Overview
Chapter 10 Buzzer 10-1 Overview This LSI has a buzzer. It can output the square wave, having a frequency 1/2 oscillation clock, or by 1/2 to 1/2 10-1-1 Block Diagram Buzzer Block Diagram fosc DLYCTR DLYS0 DLYS1 BUZS0 BUZS1 BUZS2 BUZOE X - 2 Overview...
Page 323: Control Register
10-2 Control Register Oscillation Stabilization Wait Timer Control Register DLYCTR BUZOE BUZS2 BUZS1 BUZS0 Figure 10-2-1 DLYS2 DLYS1 DLYS0 DLYS2 Note : After reset is released, the oscillation stabilization wait period is fixed at 2 BUZS2 Oscillation Stabilization Wait Time Control Register (DLYCTR : x'03F4D', R/W) Chapter 10 Buzzer (At reset : 0 0 0 0 0 0 0 - )
Page 324: Operation
Chapter 10 Buzzer 10-3 Operation 10-3-1 Operation Buzzer Buzzer outputs the square wave, having a frequency 1/2 (fosc), or by 1/2 to 1/2 of the low speed oscillation clock (fx). The BUZS 2, 1, 0 flag of the oscillation stabilization wait control register (DLYCTR) set the frequency of buzzer output. The BUZOE flag of the oscillation stabilization wait control register (DLYCTR) sets buzzer output ON / OFF.
Page 325: Setup Example
10-3-2 Setup Example Buzzer outputs the square wave of 2 kHz from P06 pin. It is used 8.38 MHz as the high oscillation clock (fosc). An example setup procedure, with a description of each step is shown below. Setup Procedure (1) Set the buzzer frequency.
Page 327: Chapter 11 Serial Interface
Chapter 11 Serial Interface 0,1...
Page 328: Overview
Chapter 11 Serial Interface 0, 1 11-1 Overview This LSI contains a serial interface 0 and 1 that can be used for both communication types of clock synchronous and UART (duplex). Also, the pins are changable to A (port 0) or B (port 7). Table 11-1-1 Serial Interface 0 Serial Interface 1...
Page 329: Functions
11-1-1 Functions Table 11-1-1 shows functions of serial interface 0, 1. Table 11-1-1 Communication style clock synchronous SC0TIRQ Interrupt Used pins SBO0,SBI0,SBT0 3 channels type 2 channels type (SBO0, SBT0) 1 channel type Specification of transfer bit 1 to 8 bits count / Frame selection Selection of parity bit Parity bit control...
Page 330: Block Diagram
Chapter 11 Serial Interface 0, 1 11-1-2 Block Diagram Serial Interface 0 Block Diagram Figure 11-1-1 Serial Interface 0 Block Diagram XI - 4 Overview...
Page 331 Chapter 11 Serial Interface 0, 1 Serial Interface 1 Block Diagram Figure 11-1-2 Serial Interface 1 Block Diagram XI - 5 Overview...
Page 332: Control Registers
Chapter 11 Serial Interface 0, 1 11-2 Control Registers 11-2-1 Registers Table 11-2-1 shows registers to control serial interface 0, 1. Table 11-2-1 Register Address SC0MD0 x'03F92' SC0MD1 x'03F93' SC0MD2 x'03F94' SC0MD3 x'03F95' RXBUF0 x'03F90' TXBUF0 x'03F91' SC0ODC x'03F96' Serial interface 0 SC0CKS x'03F97' PSCMD...
Page 333: Serial Interface 0 Data Buffer Registers
11-2-2 Serial Interface 0 Data Buffer Registers Serial Interface 0 has each 8-bit data buffer register for transmission, and for reception. Serial Interface 0 Reception Data Buffer (RXBUF0) RXBUF0 RXBUF07 RXBUF06 RXBUF05 Figure 11-2-1 Serial Interface 0 Reception Data Buffer (RXBUF0 : x'03F90', R) Serial Interface 0 Transmissin Data Buffer (TXBUF0) TXBUF0 TXBUF07...
Page 334: Serial Interface 0 Mode Registers
Chapter 11 Serial Interface 0, 1 11-2-3 Serial Interface 0 Mode Registers Serial Interface 0 Mode Register 0 (SC0MD0) SC0MD0 SC0CE1 SC0REN SC0TRN Figure 11-2-3 Serial Interface 0 Mode Register 0 (SC0MD0 : x'03F92', R/W) XI - 8 Control Registers SC0DIR SC0STE SC0LNG2...
Page 335 Serial Interface 0 Mode Register 1 (SC0MD1) SC0MD1 SC0IOM SC0SBTS SC0SBIS SC0SBOS Figure 11-2-4 Serial Interface 0 Mode Register 1 (SC0MD1 : x'03F93', R/W) SC0CKM SC0MST SC0CMD Chapter 11 Serial Interface 0, 1 (At reset : 0 0 0 0 0 0 - 0 ) Synchronous serial / SC0CMD Duplex UART selection...
Page 336 Chapter 11 Serial Interface 0, 1 Serial Interface 0 Mode Register 2 (SC0MD2) SC0BRKF flag is only for reading. SC0MD2 SC0FM1 SC0FM0 SC0PM1 Figure 11-2-5 Serial Interface 0 Mode Register 2 (SC0MD2 : x'03F94', R/W) XI - 10 Control Registers SC0PM0 SC0NPE SC0BRKF...
Page 337: Serial Interface 0,1
Serial Interface 0 Mode Register 3 (SC0MD3) All flags are only for reading. SC0MD3 SC0TBSY SC0RBSY SC0TEMP SC0REMP Figure 11-2-6 Serial Interface 0 Mode Register 3 (SC0MD3 : x'03F95', R) SC0FEF SC0PEK SC0ORE SC0ERE Chapter 11 Serial Interface 0, 1 (At reset : 0 0 0 0 0 0 0 0 ) SC0ERE Error monitor flag...
Page 338: Serial Interface 3
Chapter 11 Serial Interface 0, 1 Serial Interface 0 Port Control Register (SC0ODC) SC0ODC Reseved SC0SEL Figure 11-2-7 Serial Interface 0 Port Control Register (SC0ODC : x'03F96', R/W) XI - 12 Control Registers SC0ODC3 SC0ODC2 SC0ODC1 SC0ODC0 (At reset : 0 0 - - 0 0 0 0 ) PO3Nch open-drain control SC0ODC0 Push-pull...
Page 339: Serial Interface 4
Serial Interface 0 Transfer Clock Selection Register (SC0CKS) SC0CKS Figure 11-2-8 Serial Interface 0 Tranfer Clock Selection Register (SC0CKS : x'03F97', R/W) SC0PSC2 SC0PSC1 SC0PSC0 Chapter 11 Serial Interface 0, 1 (At reset : - - - - - X X X ) Clock selection SC0PSC2 SC0PSC1 SC0PSC0...
Page 340: Serial Interface 1 Data Buffer Registers
Chapter 11 Serial Interface 0, 1 11-2-4 Serial Interface 1 Data Buffer Registers Serial Interface 1 has each 8-bit data buffer register for transmission, and for reception. Serial Interface 1 Reception Data Buffer (RXBUF1) RXBUF1 RXBUF17 RXBUF16 RXBUF15 Figure 11-2-9 Serial Interface 1 Reception Data Buffer (RXBUF1 : x'03F98', R) Serial Interface 1 Transmissin Data Buffer (TXBUF1) TXBUF1...
Page 341: Serial Interface 1 Mode Registers
11-2-5 Serial Interface 1 Mode Registers Serial Interface1 Mode Register 0 (SC1MD0) SC1MD0 SC1CE1 SC1REN SC1TRN SC1DIR Figure 11-2-11 Serial Interface 1 Mode Register 0 (SC1MD0 : x'03F9A', R/W) SC1STE SC1LNG2 SC1LNG1 SC1LNG0 Chapter 11 Serial Interface 0, 1 (At reset : 0 0 0 0 0 1 1 1 ) Synchronous serial SC1LNG2 SC1LNG1...
Page 342 Chapter 11 Serial Interface 0, 1 Serial Interface 1 Mode Register 1 (SC1MD1) SC1MD1 SC1IOM SC1SBTS SC1SBIS Figure 11-2-12 XI - 16 Control Registers SC1SBOS SC1CKM SC1MST SC1CMD Serial Interface 1 Mode Register 1 (SC1MD1 : x'03F9B', R/W) (At reset : 0 0 0 0 0 0 - 0 ) Synchronous serial / SC1CMD Duplex UART selection...
Page 343 Serial Interface 1 Mode Register 2 (SC1MD2) SC1BRKF flag is only for reading. SC1MD2 SC1FM1 SC1FM0 SC1PM1 SC1PM0 Figure 11-2-13 Serial Interface 1 Mode Register 2 (SC1MD2 : x'03F9C', R/W) SC1NPE SC1RKF SC1BRKE Chapter 11 Serial Interface 0, 1 (At reset : 0 0 0 0 0 - 0 0 ) SC1BRKE Break status transmit control Data transmission...
Page 344 Chapter 11 Serial Interface 0, 1 Serial Interface 1 Mode Register 3 (SC1MD3) All flags are only for reading. SC1MD3 SC1TBSY SC1RBSY SC1TEMP Figure 11-2-14 XI - 18 Control Registers SC1REMP SC1FEF SC1PEK SC1ORE SC1ERE Serial Interface 1 Mode Register 3 (SC1MD3 : x'03F9D', R) (At reset : 0 0 0 0 0 0 0 0 ) Error monitor flag SC1ERE...
Page 345 Serial Interface 1 Port Control Register (SC1ODC) SC1ODC SC1SEL Reseved Figure 11-2-15 Serial Interface 1 Port Control Register (SC1ODC : x'03F9E', R/W) When port 7 is used as a pin for serial interface 1 and port 0 is used as the general port, P00 or P02 should be used as input port.
Page 346 Chapter 11 Serial Interface 0, 1 Serial Interface1 Transfer Clock Selection Register (SC1CKS) SC1CKS Figure 11-2-16 Serial Interface 1 Tranfer Clock Selection Register (SC1CKS : x'03F9F', R/W) XI - 20 Control Registers SC1PSC2 SC1PSC1 SC1PSC0 (At reset : - - - - - X X X ) Clock selection SC1PSC2 SC1PSC1 SC1PSC0...
Page 347: Operation
11-3 Operation Serial Interface 0, 1 can be used for both clock synchronous and duplex UART. 11-3-1 Clock Synchronous Serial Interface Activation Factor for Communication Table 11-3-1 shows activation factors for communication. At master, the transfer clock is generated by setting data to the transmission data buffer TXBUFn, or by receiving a start condition.
Page 348 Chapter 11 Serial Interface 0, 1 Start Condition Setup The SCnSTE flag of the SCnMD0 register sets if a start condition is enabled or not. If a start condition is enabled, and received at communication, a bit counter is cleared to restart the communication. The start condition, if the SCnCE1 flag of the SCnMD0 register is set to "0", is regarded when a data line (SBI pin (with 3 channels) or SBO pin (with 2 channels) is changed from "H"...
Page 349 Tranfer Bit Count and First Transfer Bit When the transfer bit is 1 bit to 7 bits, the data storing method to the transmission data buffer TXBUFn is different, depending on the first transfer bit selection. At MSB first, use the upper bits of TXBUFn for storing.
Page 350: Automatic Transfer
Chapter 11 Serial Interface 0, 1 Continuous Communication This serial has a function for continuous communication. If data is set to the transmission data buffer TXBUFn during communication, the transmission buffer empty flag SCnTEMP is automatically set to communicate continuously. Data setup to TXBUFn should be done till the communication complete interrupt SCnTIRQ is generated after the former data is set.
Page 351 Clock Setup The SCnCKS register selects a clock source from the special prescaler and timer 4 output. The special prescaler starts its operation after the PSCMD (x'03F6F') register selects "prescaler operation". The SCnMST flag of the SCnMD1 register can select the internal clock (clock master), or the external clock (clock slave).
Page 352 Chapter 11 Serial Interface 0, 1 Received Buffer Empty Flag When the reception is completed (the last data reception edge of the clock is input), data is stored to RXBUFn from the internal shift register, automatically. If data is stored to the shift register RXBUFn, the received buffer empty flag SCnREMP of the SCnMD3 register is set to "1".
Page 353 Emergency Reset It is possible to shut down communication. For a forced reset, the SCnSBOS flag and the SCnSBIOS flag of the SCnMD1 register should be set to "0" (SBO pin : port, input data : "1" input). At forced reset, the status registers (the SCnBRKF flag of the SCnMD2 register, all flags of the SCnMD3 register) are initialized as they are set at reset, but the control register holds the setting value.
Page 354 Chapter 11 Serial Interface 0, 1 Trasnmission Timing Clock (SBT pin) Output data (White SBO pin) Transfer bit counter SCnTBSY (Write data to TXBUFn) Interrupt (SCnTIRQ) Figure 11-3-5 Transmission Timing (falling edge, start condition is enabled) (at master) Tmax=1.5 T Clock (SBT pin) Output data...
Page 355 (at master) Tmax=2.5 T Clock (SBT pin) Output data (SBO pin) Transfer bit counter SCnTBSY (Write data to TXBUFn) Interrupt (SCnTIRQ) Figure 11-3-7 Transmission Timing (rising edge, start condition is enabled) (at master) Tmax=1.5 T Clock (SBT pin) Output data (SBO pin) Transfer bit counter SCnTBSY...
Page 356 Chapter 11 Serial Interface 0, 1 Reception Timing Clock (SBT pin) Input data (SBI pin) Transfer bit counter SCnRBSY (Write data to TXBUFn) Interrupt (SCnTIRQ) Figure 11-3-9 (at master) Tmax=1.5 T Clock (SBT pin) Input data (SBI pin) Transfer bit counter SCnRBSY (Write data to TXBUFn) Interrupt...
Page 357 (at master) Tmax=2.5 T Clock (SBT pin) Input data (SBI pin) Transfer bit counter SCnRBSY (Write data to TXBUFn) Interrupt (SCnTIRQ) Figure 11-3-11 Reception Timing (falling edge, start condition is enabled) (at master) Tmax=1.5 T Clock (SBT pin) Input data (SBI pin) Transfer bit counter SCnRBSY...
Page 358 Chapter 11 Serial Interface 0, 1 Transmission / Reception Timing When transmission and reception are operated at the same time, set the SCnCE1 flag of the SCnMD0 register to "0" or "1". Data is received at the opposite edge of the transmission clock, so that the recep- tion clock should be the opposite edge of the transmission clock from the other side.
Page 359: Serial Interface 0 Synchronous Serial Interface Pin Setup
11-3-2 Serial interface 0 Synchronous Serial Interface Pin Setup Serial Interface 0 Pins Setup (3 channels, at transmission) Table 11-3-6 shows the setup for synchronous serial interface pin with 3 channels (SBO0 pin, SBI0 pin, SBT0 pin) at transmission. Table 11-3-6 Setup for Synchronous Serial Interface 0 Pin (3 channels, at transmission) Data output pin Setup item...
Page 360 Chapter 11 Serial Interface 0, 1 Serial Interface 0 Pins Setup (3 channels, at transmission / reception) Table 11-3-8 shows the setup for synchronous serial interface pin with 3 lines (SBO0 pin, SBI0 pin, SBT0 pin) at transmission / reception. Table 11-3-8 Setup item Port Pin...
Page 361 Serial Interface 0 Pins Setup (2 channels, at transmission) Table 11-3-9 shows the setup for synchronous serial interface pin with 2 channels (SBO0 pin, SBT0 pin) at transmission. SBI0 pin can be used as a general port. Table 11-3-9 Setup for Synchronous Serial Interface 0 Pin (2 channels, at transmission) Setup item SBO0A pin/ SBO0B pin...
Page 362: Serial Interface 1 Synchronous Serial Interface Pin Setup
Chapter 11 Serial Interface 0, 1 11-3-3 Serial interface 1 Synchronous Serial Interface Pin Setup Serial Interface 1 Pins Setup (3 channels, at transmission) Table 11-3-11 shows the setup for synchronous serial interface pin with 3 channels (SBO1 pin, SBI1 pin, SBT1 pin) at transmission.
Page 363 Serial Interface 1 Pins Setup (3 channels, at transmission / reception) Table 11-3-13 shows the setup for synchronous serial interface pin with 3 lines (SBO1 pin, SBI1 pin, SBT1 pin) at transmission / reception. Table 11-3-13 (3 channels, at transmission / reception) Data output pin Setup item SBO0A pin/...
Page 364 Chapter 11 Serial Interface 0, 1 Serial Interface 1 Pins Setup (2 channels, at transmission) Table 11-3-14 shows the setup for synchronous serial interface pin with 2 channels (SBO1 pin, SBT1 pin) at transmission. SBI1 pin can be used as a general port. Table 11-3-14 Setup for Synchronous Serial Interface 1 Pin (2 channels, at transmission) Setup item Port Pin...
Page 365: Setup Example
11-3-4 Setup Example Transmission / Reception Setup Example The setup example for clock synchronous serial communication with serial 0 is shown. Table 11-3-16 shows the conditions at transmission / reception. Table 11-3-16 Setup Examples for Synchronous Serial Interface Transmission / Reception Setup item SBI / SBO pin Trans fer bit count...
Page 366 Chapter 11 Serial Interface 0, 1 Setup Procedure Select the transfer bit count. SC0MD0 (x'3F92') Select the start condition. SC0MD0 (x'3F92') bp3 : SC0STE = 0 Select the first bit to be transfered. SC0MD0 (x'3F92') bp4 : SC0DIR = 0 Select the transfer edge.
Page 367 Setup Procedure (15) Set the interrupt level. SC0TICR (x'3FF5') bp7-6 : SC0TLV1-0 = 10 (16) Enable the interrupt. SC0TICR (x'3FF5') bp1 : SC0TIE = 1 (17) Start serial transmission. Transmission data TXBUF0 (x'3F91') Received data input to SBI0A pin. Note : In (6) to (9), (10) to (11), (12) to (14),each settings can be set at once. When only reception with 3 "0"...
Page 368: Uart Serial Interface
Chapter 11 Serial Interface 0, 1 11-3-5 UART Serial Interface Serial 0, 1 can be used for duplex UART communication. Table 11-3-17 shows UART serial interface functions. Table 11-3-17 Communication style Interrupt Used pins Specification the first transfer bit Selection of parity bit Parity bit control Frame selection Continuous operation...
Page 369 Activation Factor for Communication At transmission, if any data is written to the transmission data buffer TXBUFn, a start condition is gener- ated to start transfer. At reception, if a start condition is received, communication is started. At reception, if the data length of "L" for start bit is longer than 0.5 bit, that can be regarded as a start condition. Transmission Data transfer is automatically started by writing data to the transmission data buffer TXBUFn.
Page 370 Chapter 11 Serial Interface 0, 1 Reception BUSY flag When the start condition is reagarded, the SCnRBSY flag of the SCnMD3 register is set to "1". That is cleared to "0" by the generation of the reception complete interrupt SCnRIRQ. If, during reception, the SCnSBIS flag is set to "0", the SCnRBSY flag is reset to "0".
Page 371 The SCnFM1 to 0 flag of the SCnMD2 register sets the frame mode. Table 11-3-19 is shown the UART Serial Interface Frame Mode setting. If the SCnCMD flag of the SCnMD1 register is set to "1", and UART communication is selected, the transfer bit count on the SCnLNG2 to 0 flag of the SCnMD0 register is no more valid.
Page 372 Chapter 11 Serial Interface 0, 1 Reception Error At reception , there are 3 types of error ; overrun error, parity error and framing error. Reception error can be determined by the SCnORE, SCnPEK, SCnFEF flag of the SCnMD3 register. Even one of those errors is detected, the SCnERE flag of the SCnMD3 register is set to "1".
Page 373 Transmission/reception data polarity switching In UART communication, polarity of transmission/reception data cannot be switched. At the same time, setups of the SCnTRN, SCnREN flags of the SCnMD0 register are invalid. Clock Setup At UART communication, the transfer clock is not needed, but the clock setup should be needed to decide the timing of the data transmission / reception in the serial interface.
Page 374 Chapter 11 Serial Interface 0, 1 The following items are same to clock synchronous serial. Reference as follows ; First Transfer Bit Setup Refer to : XI-21 Transmission Data Buffer Refer to : XI-21 Received Data Buffer Refer to : XI-21 Transfer Bit Count and First Transfer Bit Refer to : XI-22 Receive Bit Count and First Transfer Bit...
Page 375 Transmission Timing TXD pin SCnTBSY write data to TXBUFn Interrupt (SCnTIRQ) Figure 11-3-16 TXD pin SCnTBSY write data to TXBUFn Interrupt (SCnTIRQ) Figure 11-3-17 Transmission Timing (parity bit is enabled) Transmission Timing (parity bit is disabled) Chapter 11 Serial Interface 0, 1 stop parity stop...
Page 376 Chapter 11 Serial Interface 0, 1 Reception Timing Tmin=0.5 T RXD pin SCnRBSY input start condition Interrupt (SCnRIRQ) Figure 11-3-18 Tmin=0.5T RXD pin SCRBSY input start condition Interrupt (SCRIRQ) Figure 11-3-19 XI - 50 Operation Reception Timing (parity bit is enabled) Reception Timing (parity bit is disabled) Parity Stop...
Page 377: Bit Timers
Transfer Rate Baud rate timer (timer 2 and timer 4) can set any transfer rate. Tables 11-3-22, 23 show the setup example of the transfer rate. For detail of the baud rate timer setup, refer to chapter 6. 8-bit Timer. Table 11-3-22 Serial 0 clock source (timer output) Timer clock source selection...
Page 378 Chapter 11 Serial Interface 0, 1 Table 11-3-24-1 fosc Clock source (MHz) (timer) Set value Calculated Value fosc 4.00 fosc/4 fosc/16 fosc/32 fosc/64 fs/2 fs/4 4.19 fosc fosc/4 fosc/16 fosc/32 fosc/64 fs/2 fs/4 fosc 8.00 fosc/4 fosc/16 fosc/32 fosc/64 fs/2 fs/4 fosc 8.38...
Page 379 Table 11-3-24-2 fosc Clock source 9600 (MHz) (timer) Set value Calculated Value fosc 9615 4.00 fosc/4 fosc/16 fosc/32 fosc/64 fs/2 fs/4 4.19 fosc 9699 fosc/4 fosc/16 fosc/32 fosc/64 fs/2 fs/4 fosc 9615 8.00 fosc/4 9615 fosc/16 fosc/32 fosc/64 fs/2 9615 fs/4 fosc 9523...
Page 380: Serial Interface 0 Uart Serial Interface Pin Setup
Chapter 11 Serial Interface 0, 1 11-3-6 Serial interface 0 UART Serial Interface Pin Setup Serial Interface 0 Pin Setup (1, 2 channels, at transmission) Table 11-3-25 shows the pins setup at UART serial interface 0 transmission. The pins setup is common to the TXD0 pin, RXD0 pin, regardless of those pins are independent / connected.
Page 381 Serial Interface 0 Pin Setup (1 channel, at reception) Table 11-3-27 shows the pin setup at UART serial interface 0 reception with 1 channel (TXD0 pin). The RXD0 pin is not used, so can be used as a port. Table 11-3-27 UART Serial Interface 0 Pin Setup (1 channel, at reception) Port Pin Port Pin Setup...
Page 382: Serial Interface 1 Uart Serial Interface Pin Setup
Chapter 11 Serial Interface 0, 1 11-3-7 Serial interface 1 UART Serial Interface Pin Setup Serial Interface 1 Pin Setup (1, 2 channels, at transmission) Table 11-3-29 shows the pins setup at UART serial interface 1 transmission. The pins setup is common to the TXD1 pin, RXD1 pin, regardless of those pins are independent / connected.
Page 383 Serial Interface 1 Pin Setup (1 channel, at reception) Table 11-3-31 shows the pin setup at UART serial interface reception with 1 channel (TXD1 pin). The RXD1 pin is not used, so can be used as a port. Table 11-3-31 UART Serial Interface 1 Pin Setup (1 channel, at reception) Port Pin Port Pin Setup...
Page 384: Setup Example
Chapter 11 Serial Interface 0, 1 11-3-8 Setup Example Transmission / Reception Setup The setup example at UART transmission / reception with serial 0 is shown. Table 11-3-33 shows the conditions at transmission / reception. Table 11-3-33 TXD / RXD pin Frame mode specification First transfer bit Clock source...
Page 385: Functions
Setup Procedure Select the start condition. SC0MD0 (x'3F92') bp3 : SC0STE = 1 Select the first bit to be transfered. SC0MD0 (x'3F92') bp4 : SC0DIR = 0 Control the output data. SC0MD2 (x'3F94') bp0 : SC0BRKE = 0 Select the added parity bit. SC0MD2 (x'3F94') bp3 : SC0NPE = 0 bp5-4 : SC0PM1-0 = 00...
Page 386 Chapter 11 Serial Interface 0, 1 Setup Procedure (14) Enable the interrupt. SC0RICR (x'3FF4') bp1 : SC0RIE = 1 SC0TICR (x'3FF5') bp1 : SC0TIE = 1 (15) Set the baud rate timer. (16) Start serial communication. The transmission data The received data Note : (6) to (7), (8) to (10), (11) to (13) can be set at once.
Page 387 Chapter 12 Serial Interface 3...
Page 388: Overview
Chapter 12 Serial Interface 3 12-1 Overview This LSI contains a serial interface 3 can be used for both communication types of clock synchronous and simple IIC (single master). 12-1-1 Functions Table 12-1-1 shows the functions of serial interface 3. Table 12-1-1 Communication type Interrupt...
Page 389: Block Diagram
Chapter 12 Serial Interface 3 12-1-2 Block Diagram Serial Interface 3 Block Diagram Figure 12-1-1 Serial Interface 3 Block Diagram XII - 3 Overview...
Page 390: Control Registers
Chapter 12 Serial Interface 3 12-2 Control Registers 12-2-1 Registers Table 12-2-1 shows the registers to control serial interface 3. Table 12-2-1 Register SC3MD0 SC3MD1 SC3CTR SC3TRB SC3ODC Serial interface 3 SC3CKS PSCMD P5DIR P5PLU SC3ICR R / W : Readable / Writable XII - 4 Control Registers Serial Interface 3 Control Registers...
Page 391 12-2-2 Data Register Serial interface 3 has a 8-bit serial data register. Serial Interface 3 Transmit / Receive Shift Register (SC3TRB) SC3TRB SC3TRB7 SC3TRB6 SC3TRB5 Figure 12-2-1 Serial Interface 3 Transmit/Receive Shift Register (SC3TRB : x'03FAB', R/W) SC3TRB4 SC3TRB3 SC3TRB2 SC3TRB1 Chapter 12 Serial Interface 3...
Page 392: 12-2-3 Mode Registers
Chapter 12 Serial Interface 3 12-2-3 Mode Registers Serial Interface 3 Mode Register 0 (SC3MD0) SC3MD0 SC3BSY SC3CE1 Figure 12-2-2 Serial Interface 3 Mode Register 0 (SC3MD0 : x'03FA8', R/W) XII - 6 Control Registers SC3DIR SC3STE SC3LNG2 SC3LNG1 SC3LNG0 (At reset: 00 - 0 0 1 1 1 ) Transfer bit count SC3LNG2...
Page 393 Serial Interface 3 Mode Register 1 (SC3MD1) SC3MD1 SC3IOM SC3SBTS SC3SBIS SC3SBOS Figure 12-2-3 Serial Interface 3 Mode Register 1 (SC3MD1 : x'03FA9', R/W) SC3MST Chapter 12 Serial Interface 3 (At reset: 0 0 0 0 - 0 - -) Clock master/slave selection SC3MST Slave...
Page 394 Chapter 12 Serial Interface 3 Serial Interface 3 Control Register (SC3CTR) SC3CTR IICBSY SC3STC Figure 12-2-4 Serial Interface 3 Control Register (SC3CTR : x'03FAA', R/W) XII - 8 Control Registers SC3REX SC3CMD SC3ACKS SC3ACKO (At reset: 0 0 - - 0 0 0 0 ) ACK bit level specification SC3ACKO "L"...
Page 395 Serial Interface 3 Port Control Register (SC3ODC) SC3ODC Reserved Figure 12-2-5 Serial Interface 3 Port Control Register (SC3ODC : x'03FAE', R/W) Serial Interface 3 Transfer Clock Selection Register (SC3CKS) SC3CKS Figure 12-2-6 SC3ODC1 SC3ODC0 RESERVED SC3PSC2 SC3PSC1 SC3PSC0 SC3PSC2 RESERVED Serial Interface 3 Transfer Clock Selection Register (SC3CKS : x'03FAF', R/W) Chapter 12...
Page 396: Operation
Chapter 12 Serial Interface 3 12-3 Operation This LSI contains a serial interface 3 that can be used for both communication types of clock synchronous and single master IIC. 12-3-1 Clock Synchronous Serial Interface Activation Factor for Communication Table 12-3-1 shows the activation factor for communication. At master communication, the transfer clock is generated by setting data to the transmit/receive shift register SC3TRB, or by receiving start condition.
Page 397 First Transfer Bit Setup The first bit to be transferred can be set by the SC3DIR flag of the SC3MD0 register. MSB first or LSB first can be selected. Transmit /Receive Data Buffer Data register for transmission/reception is common. That is the transmit/receive shift register SC3TRB. The transmission data should be set to SC3TRB.
Page 398 Chapter 12 Serial Interface 3 Continuous Communication Serial interface 3 can be started by automatic data transfer function ATC1, built-in this LSI. If ATC1 is used for activation, data can be continuously transferred up to 255 byte. The communication blank, from the generation of the communication complete interrupt SC3IRQ to the generation of the next transfer clock, is up to 18 machine cycles + 2 transfer clocks.
Page 399 Table 12-3-3 Input Edge/Output Edge of Transmission/Received Data Transmission data output edge SC3CE1 Data Input Pin Setup There are 2 communication modes to be selected : 3 channels type (clock pin(SBT3 pin), data output pin (SBO3 pin), data input pin (SBI3 pin)), 2 channels type (clock pin (SBT3 pin), data I/O pin (SBO3 pin)). The SBI3 pin can be used only for serial data input.
Page 400 Chapter 12 Serial Interface 3 Transmission Timing at master Tmax=2.5 T Clock (SBT3 pin) Output data (SBO3 pin) Transfer bit counter SC3BSY (Write data to SC3TRB) Interrupt (SC3IRQ) Figure 12-3-2 Transmission Timing (Falling edge, Enable Start Condition) at master Tmax=1.5 T Clock (SBT3 pin) Output data...
Page 401 at master Tmax=2.5 T Clock (SBT3 pin) Output data (SBO3 pin) Transfer bit counter SC3BSY (Write data to SC3TRB) Interrupt (SC3IRQ) Figure 12-3-4 Transmission Timing (Rising edge, Enable Start Condition) at master Tmax=1.5 T Clock (SBT3 pin) Output data (SBO3 pin) Transfer bit counter SC3BSY (Write data to SC3TRB)
Page 402 Chapter 12 Serial Interface 3 Reception Timing at master Tmax=2.5 T Clock (SBT3 pin) Input data (SBI3 pin) Transfer bit counter SC3BSY (Write data to SC3TRB) interrupt (SC3IRQ) Figure 12-3-6 at master Tmax=1.5 T Clock (SBT3 pin) Input data (SBI3 pin) Transfer bit counter SC3BSY (Write data to SC3TRB)
Page 403 at master Tmax=2.5 T Clock (SBT3 pin) Input data (SBI3 pin) Transfer bit counter SC3BSY (Write data to SC3TRB) Interrupt (SC3IRQ) Figure 12-3-8 Reception Timing (Falling edge, Enable Start Condition) at master Tmax=1.5 T Clock (SBT3 pin) Input data (SBI3 pin) Transfer bit counter SC3BSY (Write data to SC3TRB)
Page 404 Chapter 12 Serial Interface 3 Transmission/Reception Simultaneous timing When transmission and reception are operated at the same time, data is recieved at the opposite edge of the transmission clock. SBT3 pin SBI3 pin SBO3 pin Figure 12-3-10 Transmission/Reception Timing (Reception : Rising edge, Transmission : Falling edge) SBT3 pin SBI3 pin SBO3 pin...
Page 405 Pin Setup (3 channels, at transmission) Table 12-3-5 shows the pins setup at synchronous serial interface transmission with 3 channels (SBO3 pin, SBI3 pin, SBT3 pin). Table 12-3-5 Synchronous Serial Interface Pin Setup (3 channels, at transmission) Data output pin Item SBO3 pin SBI3/SBO3 independent...
Page 406 Chapter 12 Serial Interface 3 Pin Setup (3 channels, at reception) Table 12-3-6 shows the pins setup at synchronous serial interface reception with 3 channels (SBO3 pin, SBI3 pin, SBT3 pin). Table 12-3-6 Synchronous Serial Interface Pin Setup (3 channels, at reception) Data output pin Item SBO3 pin...
Page 407 Pin Setup (3 channels, at transmission/reception) Table 12-3-7 shows the pins setup at synchronous serial interface transmission/reception with 3 channels (SBO3 pin, SBI3 pin, SBT3 pin). Table 12-3-7 Data output pin Item SBO3 pin SBI3/SBO3 independent SBI3/SBO3 pin SC3MD1(SC3IOM) Serial data output Function SC3MD1(SC3SBOS) Push-pull/...
Page 408 Chapter 12 Serial Interface 3 Pin Setup (2 channels, at transmission) Table 12-3-8 shows the pins setup at synchronous serial interface transmission with 2 channels (SBO3 pin, SBT3 pin). The SBI3 pin is not used, so that it can be used as a general port. Table 12-3-8 Synchronous Serial Interface Pin Setup (2 channels, at transmission) Data output pin...
Page 409 Pin Setup (2 channels, at reception) Table 12-3-9 shows the pins setup at synchronous serial interface reception with 2 channels (SBO3 pin, SBT3 pin). The SBI3 pin is not used, so that it can be used as a general port. Table 12-3-9 Synchronous Serial Interface Pin Setup (2 channels, at reception) Data output pin...
Page 410: Setup Example
Chapter 12 Serial Interface 3 13-3-2 Setup Example Transmission/Reception Setup Example Here is the setup example for transmission/reception with serial interface 3. Table 12-3-10 shows the conditions. Table 12-3-10 Setup conditions for Synchronous Serial Interface Transmission/Reception Item SBI3/SBO3 pin Transfer bit count Start condition First bit to be transfered Input edge...
Page 411 Setup Procedure (6) Select the transfer bit count. SC3MD0 (x'3FA8') bp2-0 : SC3LNG2-0 = 111 (7) Select the start condition. SC3MD0 (x'3FA8') bp3 : SC3STE = 1 (8) Select the first transfer bit. SC3MD0 (x'3FA8') bp4 : SC3DIR = 0 (9) Select the transfer edge.
Page 412 Chapter 12 Serial Interface 3 Setup Procedure (15) Start serial transmission. Transmission data SC3TRB (x'3FAB') Note : In the above settings, (6) to (9), (10) to (11),can be set at once. If the communication is only for transmission, the data that input by setting the SC3SBIS of the SC3MD1 register to "0"...
Page 413: Single Master Iic Interface
12-3-3 Single Master IIC Interface IIC serial communication in single master is available at serial interface 3. Communication of this IIC interface is based on the data transfer format of Philips, IIC-BUS. Table 12-3-11 shows the functions of IIC serial interface. Table 12-3-11 Interrupt Transfer bit count...
Page 414 Chapter 12 Serial Interface 3 Start Condition Setup At IIC communication, enable start condition by the SC3STE flag of the SC3MD0 register at the begin- ning of communication. The SC3STE flag of the SC3MD0 register can select if start condition is enabled or not.
Page 415 Reception of Acknowledgement (ACK) Bit after Data Transmission This LSI does not contain the function of receiving the acknowledgement (ACK) bit after data transmission. To receive ACK bit after transmitting data, select sc3acks= "0" (No ACK bit) before data transmisison. By transmitting the 8-bit data, an interrupt generates.
Page 416 Chapter 12 Serial Interface 3 Transfer Format On IIC bus, there are 2 transfer formats : the addressing format that transmits/receives data after 1 byte data (address data) that consists of slave address (7 bits) and R/W bit (1 bit) is transferred after start condition, and the free data format that transmits data after start condition.
Page 417 Transmission/Reception Mode Setup and Operation The SC3REX flag of the SC3CTR register selects the status of the transmission or the reception. The first data is always added start condition for communication. The start condition is output from the mas- ter, this serial. If the communication is continued (no stop condition is generated), start condition should not be added from the next data.
Page 418 Chapter 12 Serial Interface 3 Master Transmission Timing 8-bit transmission Interrupt IICBSY Set data to SC3TRB (1) Output start condition. (2) Bus released period, ACK bit is received. (3) Interrupt transaction. (4) Receive ACK bit. (5) Interrupt transaction. (6) Generates stop condition. Figure 12-3-16 Master Transmission Timing XII - 32 Operation...
Page 419 Master Reception Timing 8-bit transmission Interrupt IICBSY Set data to SC3TRB (1) Output start condition. (2) Bus released period, ACK bit is received. (3) Interrupt transaction (4) Output ACK bit. (5) Bus released period, interrupt transaction (6) Generate stop condition. Figure 12-3-17 Set data to SC3TRB [Set dummy data]...
Page 420 Chapter 12 Serial Interface 3 Pin Setup (2 channels, at transmission) Table 12-3-13 shows the pins setup at IIC serial interface transmission with 2 channels (SDA pin, SCL pin). Table 12-3-13 Pin Setup (2 channels, at transmission) Item SBI3/SBO3 pin Function Type Pull-up...
Page 421 Pin Setup (2 channels, at reception) Table 12-3-14 shows the pins setup at IIC serial interface reception with 2 channels (SDA pin, SCL pin). Table 12-3-14 Item SBI3/SBO3 pin Function Type Pull-up Pin Setup (2 channels, at reception) Data output pin Data input pin SDA pin SBI3/SBO3 connection...
Page 422: 12-3-4 Setup Example
Chapter 12 Serial Interface 3 12-3-4 Setup Example Master Transmission Setup Example Here is the setup example for the transmission of the plural data to the all devices on IIC bus with IIC interface function of serial 3. Figure 12-3-15 shows the conditions. Figure 12-3-15 Item SBI3/SBO3 pins...
Page 423 Setup Procedure Set ACK bit. SC3CTR (x'3FAA') bp0 : SC3ACKO = x bp1 : SC3ACKS = 1 (6) Select the communication type. SC3CTR (x'3FAA') bp2 : SC3CMD = 1 <Transmission setup> (7) Select the transmission/reception mode. SC3CTR (x'3FAA') bp3 : SC3REX = 0 (8) Initialize the monitor flag.
Page 424 Chapter 12 Serial Interface 3 Setup Procedure (13) Select the transfer clock. SC3MD1 (x'3FA9') bp2 : SC3MST = 1 (14) Control the pin function. SC3MD1 (x'3FA9') bp4 : SC3SBOS = 1 bp5 : SC3SBIS = 1 bp6 : SC3SBTS = 1 bp7 : SC3IOM = 1 (15) Set the interrupt level.
Page 425 Setup Procedure (19) Judge the ACK bit level. SC3CTR (x'3FAA') bp0 : SC3ACKO (20) Select the transfer bit count. SC3MD0 (x'3FA8') bp2-0 : SC3LNG2-0 = 0 (21) Select the start condition. SC3MD0 (x'3FA8') bp3 : SC3STE = 0 <The next data transmission is started.> (22) Serial transmission is started.
Page 426 Chapter 12 Serial Interface 3 It is possible to shut down the communication. When the communication should be stopped by force, set the SC3SBOS and the SC3SBIS of the SC3MD1 register to "0". Setup for each flag should be done in order. The activation of communication should be done after all control registers (except table 13-2-1 : SC3TRB) are set.
Page 427: Chapter 13 Serial Interface
Chapter 13 Serial Interface 4...
Page 428: Overview
Chapter 13 Serial Interface 4 13-1 Overview This LSI contains a serial interface 4, which is compatible with IIC serial interface (slave) communication. 13-1-1 Functions Table 13-1-1 shows the functions of serial interface 4. Table 13-1-1 Serial interface 4 Functions List Communication type IIC (slave) Interrupt...
Page 429: Block Diagram
Chapter 13 Serial Interface 4 13-1-2 Block Diagram Serial interface 4 Block Diagram Figure 13-1-1 Serial interface 4 Block Diagram XIII - 3 Overview...
Page 430: Control Registers
Chapter 13 Serial Interface 4 13-2 Control Registers 13-2-1 Registers Table 13-2-1 shows the registers to control serial interface 4. Table 13-2-1 Register SC4AD0 SC4AD1 SC4TXB SC4RXB SC4STR P0DIR P0PLU P0OUT P5DIR P5PLU P5OUT SC4ODC0 SC4ODC1 SC4ICR R / W : Readable / Writable XIII - 4 Control Registers Serial interface 4 Control Registers...
Page 431: 13-2-2 Data Register
Chapter 13 Serial Interface 4 13-2-2 Data Register Serial interface 4 has a 8-bit buffer registers for transmission/reception. Serial interface 4 Reception Data Buffer (SC4RXB) ( At reset: X X X X X X X X ) SC4RXB I2CRXB7 I2CRXB6 I2CRXB5 I2CRXB4 I2CRXB3...
Page 432: 13-2-3 Mode Registers
Chapter 13 Serial Interface 4 13-2-3 Mode Registers Serial interface 4 Addressing Register 0 (SC4AD0) SC4AD0 I2CAD7 I2CAD6 Figure 13-2-3 Serial interface 4 Addressing Register 0 (SC4AD0 : x'03FA3', R/W) Serial interface 4 Addressing Register 1 (SC4AD1) SELI2C RESERVED RESERVED SC4AD1 Figure 13-2-4 Serial interface 4 Addressing Register 1 (SC4AD1 : x'03FA4', R/W) XIII - 6...
Page 433 Serial interface 4 Status Register (SC4STR) I2CINT STRT RSTRT SC4STR Figure 13-2-5 Serial interface 4 Status Register (SC4STR : x'03FAC', R) I2CBSY SLVBSY ACKVALID Chapter 13 Serial Interface 4 ( At reset: X X X X X X X X) ACK detection flag ACKVALID Undetected...
Page 434 Chapter 13 Serial Interface 4 Serial interface 4 Port Control Register 0 (SC4ODC0) SC4ODC0 Figure 13-2-6 Serial interface 4 Port Control Register 0 (SC4ODC0 : x'03F3F', R/W) Serial interface 4 Port Control Register 1 (SC4ODC1) SC4ODC1 Figure 13-2-7 Serial interface 4 Port Control Register 1 (SC4ODC1 : x'03F3D', R/W) XIII - 8 Control Registers SC4ODC01 SC4ODC00...
Page 435: Operation
13-3 Operation Activation and Termination Factors Set the SELI2C flag of the SC4AD1 register to "1" to activate this serial interface. For the termination, set the flag to "0". The ports used for communication can be used as general-purpose port while the serial interface is not in operative state.
Page 436 Chapter 13 Serial Interface 4 Busy Flag This serial interface contains 2 busy flags (SLVBSY, I2CBSY). The SLVBSY flag is set to "1" when address transmitted from master matches with the slave address. The I2CBSY flag is set to "1" during communication on IIC bus. In 10 bits addresss mode, if the upper 2 bits address which is first to be transmitted from master matches with the I2CAD9-8 of the SC4AD1 register, the SLVBSY flag is set to "1"...
Page 437: Setup Example Of The Slave Iic Serial Interface
13-3-1 Setup Example of the Slave IIC Serial Interface Setup Example of the Data Transmission This section describes the setup example of slave transmission using serial interface 4. Table 13-3-2 shows the conditions for transmission routine. An example setup procedure, with a description of each step is shown below. Setup Procedure Control the pin type.
Page 438 Chapter 13 Serial Interface 4 Setup Procedure (5) Set the slave address. SC4AD0 (x'3FA3') bp7-1 : I2CAD7-1 = 0110011 (6) IIC communication start (7) Data transmission/reception confirmation SC4STR (x'3FAC') : WRS = 0 Transmission data setup SC4TXB (x'3FA5') bp7-0 : I2CTXB7-0 = x'55' The transfer rate at IIC communication should be set to under 10 dividing of the system clock.
Page 439: Chapter 14 Automatic Transfer Controller
Chapter 14 Automatic Transfer Controller...
Page 440: Overview
Chapter 14 Automatic Transfer Controller 14-1 Overview 14-1-1 ATC1 This LSI contains an automatic transfer controller (ATC) that uses direct memory access (DMA) to transfer the contents of the whole memory space (256 KB) using the hardware. This ATC block is called ATC1. ATC1 is activated by an interrupt or a flag set by the software.
Page 441: Functions
14-1-2 Functions Table 14-1-1 and 14-1-2 provide a list of the ATC1 trigger factors and transfer modes. ATC1 Trigger Factors ATC Transfer Modes Transfer Direction (*) Transfer Mode Cycle Source Address AT1MAP0 Transfer mode 0 Transfer mode 1 AT1MAP1 (I/O area) Transfer mode 2 AT1MAP0 Transfer mode 3...
Page 442: 14-1-3 Block Diagram
Chapter 14 Automatic Transfer Controller 14-1-3 Block Diagram ATC1 Block Diagram Figure 14-1-1 ATC1 Block Diagram XIV - 4 Overview...
Page 443: Control Registers
14-2 Control Registers 14-2-1 Registers Table 14-2-1 shows the registers used to control ATC1. Register AT1CNT0 x'03FD0' AT1CNT1 x'03FD1' AT1TRC x'03FD2' AT1MAP0L x'03FD3' ATC1 AT1MAP0M x'03FD4' AT1MAP0H x'03FD5' AT1MAP1L x'03FD6' AT1MAP1M x'03FD7' AT1MAP1H x'03FD8' R/W : Readable / Writable Table 14-2-1 ATC1 Control Registers Address ATC1 control register 0 ATC1 control register 1...
Page 444 Chapter 14 Automatic Transfer Controller ATC1 Control Register 0 (AT1CNT0) AT1CNT0 FMODE AT1ACT AT1MD3 AT1MD2 AT1MD1 Figure 14-2-1 ATC1 Control Register 0 (AT1CNT0 : x'03FD0', R/W) XIV - 6 Control Registers AT1MD0 Reserved AT1EN x x x x (At reset : 0 0 0 0 ) AT1EN ATC1 transfer enable flag...
Page 445 ATC1 Control Register 1 (AT1CNT1) AT1CNT1 Figure 14-2-2 ATC1 Control Register 1 (AT1CNT1 : x'03FD1', R/W) ATC1 Transfer Counter (AT1TRC) AT1TRC AT1TRC7 AT1TRC6 AT1TRC5 AT1TRC4 AT1TRC3 Figure 14-2-3 ATC1 Transfer Data Counter (AT1TRC : x'03FD2', R/W) BTSTP AT1IR3 AT1IR2 AT1IR1 AT1IR0 AT1TRC2 AT1TRC1 AT1TRC0 AT1TRC7 to 0 ATC1 Transfer Data Count Setting ·...
Page 446 Chapter 14 Automatic Transfer Controller ATC1 Memory Pointer 0 (AT1MAP0) AT1MAP0L Figure 14-2-4 ATC1 Memory Pointer 0 : Lower 8 bits (AT1MAP0L : x'03FD3', R/W) AT1MAP0M bp15 bp14 bp13 Figure 14-2-5 ATC1 Memory Pointer 0 : Middle 8 bits (AT1MAP0M : x'03FD4', R/W) AT1MAP0H Figure 14-2-6 ATC1 Memory Pointer 0 : Upper 2 bits (AT1MAP0H : x'03FD5', R/W) ATC1 Memory Pointer 1 (AT1MAP1)
Page 447: Operation
14-3 Operation 14-3-1 Basic Operations and Timing ATC1 is a DMA block that enables the hardware to transfer the whole memory space (256 KB). This section provides a description of and timing for the basic ATC1 operations. System clock (fs) DMA start request (synchronous signal) BREQ...
Page 448 Chapter 14 Automatic Transfer Controller Data transfer The basic ATC1 operation cycle is the "byte-data transfer cycle", in which ATC1 transfers a single byte of data. This operation consists of two instruction cycles, a load and a store cycle. In the load cycle, ATC1 reads the data from the source address of the source memory, and in the store cycle, ATC1 stores the read data to the destination address of the destination memory.
Page 449: Setting The Memory Address
14-3-2 Setting the Memory Address Setting the transfer addresses to the memory pointers The address of the memory space for an automatically data transfer of ATC1 should be set in the both of memory pointer 0 (AT1MAP0) and memory pointer 1 (AT1MAP1). In each transfer mode, one of those pointer is the source address, and another is the destination address.
Page 450: 14-3-3 Setting The Data Transfer Count
Chapter 14 Automatic Transfer Controller 14-3-3 Setting the Data Transfer Count Transfer data counter (AT1TRC) function You can preset the data transfer count is preset for ATC1. Set the value in the ATC1 transfer counter (AT1TRC). The counter decrements by one each time ATC1 transfers one byte of data. The value in the transfer data counter is indeterminate upon reset.
Page 451: 14-3-4 Setting The Data Transfer Modes
Chapter 14 Automatic Transfer Controller 14-3-4 Setting the Data Transfer Modes Data transfer modes There are two types of ATC1 transfers, standard and burst, and sixteen transfer modes. Set the transfer mode in ATC1 control register 0 (AT1CNT0). Table 14-1-2 Transfer Modes ] Standard and burst transfers The ATC1 transfer modes are divided into standard transfer modes and burst transfer modes.
Page 452: Transfer Mode 0
Chapter 14 Automatic Transfer Controller 14-3-5 Transfer Mode 0 In transfer mode 0, ATC1 automatically transfers one byte of data from any memory space to the I/O space (special registers : x'03F00' - x'03FFF') every time an ATC1 activation request occurs. Set the source address in 18-bit memory pointer 0 (AT1MAP0H, M, L), and set the destination I/O address in lower 8 bits of memory pointer 1(AT1MAP1L).
Page 453: Transfer Mode 1
14-3-6 Transfer Mode 1 In transfer mode 1, ATC1 automatically transfers one byte of data from the I/O space (special registers : x'03F00' - x'03FFF') to any memory space every time an ATC1 activation request occurs. Memory Pointer 0 00000 - 3FFFF Set the source I/O address in lower 8 bits of memory pointer 1 (AT1MAP1L), and set the destination address in 18-bit memory pointer 0 (AT1MAP0H, M, L).
Page 454: Transfer Mode 2
Chapter 14 Automatic Transfer Controller 14-3-7 Transfer Mode 2 In transfer mode 2, ATC1 automatically transfers one byte of data from any memory space to the I/O space (special registers : x'03F00' - x'03FFF') every time an ATC1 activation request occurs. Set the source address in 18-bit memory pointer 0 (AT1MAP0H, M, L), and set the destination I/O address in lower 8 bits of memory pointer 1(AT1MAP1L).
Page 455: Transfer Mode 3
14-3-8 Transfer Mode 3 In transfer mode 3, ATC1 automatically transfers one byte of data from the I/O space (special registers : x'03F00' - x'03FFF') to any memory space every time an ATC1 activation request occurs. Set the source I/O address in lower 8 bits of memory pointer 1 (AT1MAP1L), and set the destination address in 18-bit memory pointer 0 (AT1MAP0H, M, L).
Page 456: Transfer Mode 4
Chapter 14 Automatic Transfer Controller 14-3-9 Transfer Mode 4 In transfer mode 4, ATC1 automatically transfers two bytes (one word) of data from any memory space to the I/O space (special registers : x'03F00' - x'03FFF') every time an ATC1 activation request occurs. Set the source address in 18-bit memory pointer 0 (AT1MAP0H, M, L), and set the destination I/O address in the lower 8 bits of memory pointer 1(AT1MAP1L).
Page 457: Transfer Mode 5
14-3-10 Transfer Mode 5 In transfer mode 5, ATC1 automatically transfers two bytes (one word) of data from the I/O space (special registers : x'03F00' - x'03FFF') to any memory space every time an ATC1 activation request occurs. Memory Pointer 0 Set the source I/O address in lower 8 bits of memory pointer 1 (AT1MAP1L), and set the destination address in 18-bit memory pointer 0 (AT1MAP0H, M, L).
Page 458: Transfer Mode 6
Chapter 14 Automatic Transfer Controller 14-3-11 Transfer Mode 6 In transfer mode 6, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs. In this mode the transfer direction indicated by memory pointers 0 and 1 reverses for the second data byte transfer.
Page 459 To execute a continuous serial transaction, you must pre-store the serial transmission data in the memory space that memory pointer 0 points, the transmission data must fill every other address in the space. Once the serial transaction ends, the received data is stored empty (skipped) addresses and the transmission and reception data at stored in an alternating pattern.
Page 460: Transfer Mode 7
Chapter 14 Automatic Transfer Controller 14-3-12 Transfer Mode 7 In transfer mode 7, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs. In this mode the transfer direction indicated by memory pointers 0 and 1 reverses for the second data byte transfer.
Page 461 To execute a continuous serial transaction, you must pre-store the serial transmission data in the memory space that memory pointer 0 points, once the serial communication ends, the MCU has written to the reception data over the transmission data, so that only reception data remains in the memory.
Page 462: Transfer Mode 8
Chapter 14 Automatic Transfer Controller 14-3-13 Transfer Mode 8 In transfer mode 8, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs. In this mode the transfer direction indicated by memory pointers 0 and 1 reverses for the second data byte transfer.
Page 463 Transfer mode 8 can be used to support continuous transmission/ reception for serial inter- face 0 and 1. Set the memory pointer 1 to point to the serial reception buffer (RXBUF0, RXBUF1) and select serial interrupts as the ATC1 trigger factor. In this way, each the serial communication ends, the MCU continuously reads the reception data (first data byte trans- fer), then writes the transmission data to the transmission buffer (TXBUF0, TXBUF1) (sec- ond data byte transfer) up to 255 times, entirely through the hardware.
Page 464: Transfer Mode 9
Chapter 14 Automatic Transfer Controller 14-3-14 Transfer Mode 9 In transfer mode 9, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs. In this mode the transfer direction indicated by memory pointers 0 and 1 reverses for the second data byte transfer.
Page 465 Transfer mode 9 can be used to support continuous transmission/ reception for serial inter- face 0 and 1. Set the memory pointer 1 to point to the serial reception buffer (RXBUF0, RXBUF1) and select serial interrupts as the ATC1 trigger factor. In this way, each the serial communication ends, the MCU continuously reads the reception data (first data byte trans- fer), then writes the transmission data to the transmission buffer (TXBUF0, TXBUF1) (sec- ond data byte transfer) up to 255 times, entirely through the hardware.
Page 466: 14-3-15 Transfer Mode A
Chapter 14 Automatic Transfer Controller 14-3-15 Transfer mode A In transfer mode A, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs. Set the source address in 18-bit memory pointer 0 (AT1MAP0H, M, L), and set the destination address in 18-bit memory pointer 1 (AT1MAP0H, M, L).
Page 467: 14-3-16 Transfer Mode B
14-3-16 Transfer Mode B In transfer mode B, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs. Set the source address in 18-bit memory pointer 1 (AT1MAP1H, M, L), and set the destination address in 18-bit memory pointer 0 (AT1MAP0H, M, L).
Page 468: 14-3-17 Transfer Mode C
Chapter 14 Automatic Transfer Controller 14-3-17 Transfer Mode C In transfer mode C, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs. Set the source address in 18-bit memory pointer 0 (AT1MAP0H, M, L), and set the destination address in 18-bit memory pointer 1 (AT1MAP1H, M, L).
Page 469: 14-3-18 Transfer Mode D
14-3-18 Transfer Mode D In transfer mode D, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs. Memory Pointer 0 Set the source address in 18-bit memory pointer 1 (AT1MAP1H, M, L), and set the destination address in 18-bit memory pointer 0 (AT1MAP0H, M, L).
Page 470: 14-3-19 Transfer Mode E
Chapter 14 Automatic Transfer Controller 14-3-19 Transfer Mode E Transfer mode E is a burst mode. In this mode, when ATC1 is activated, it automatically transfers the number of data bytes set in the transfer data counter (AT1TRC) in one continuous operation. Set the source address in 18-bit memory pointer 0 (AT1MAP0H, M, L), and set the destination address in 18-bit memory pointer 1 (AT1MAP1H, M, L).
Page 471: Transfer Mode F
14-3-20 Transfer Mode F Transfer mode F is a burst mode. In this mode, when ATC1 is activated, it automatically transfers the number of data bytes set in the transfer data counter (AT1TRC) in one continuous operation. Memory Pointer 0 Set the source address in 18-bit memory pointer 1 (AT1MAP1H, M, L), and set the destination address in 18-bit memory pointer 0 (AT1MAP0H, M, L).
Page 472: Setup Example
Chapter 14 Automatic Transfer Controller 14-4 Setup Example An example setup procedure, with a description of each step is as follows ; Setup Procedure (1) Set the data transfer mode. AT1CNT0 (x'3FD0') :FMODE :AT1ACT bp5-2 :AT1MD3-0 :AT1EN (2) Set memory pointer 0. AT1MAP0L (x'3FD3') AT1MAP0M (x'3FD4') AT1MAP0H (x'3FD5')
Page 473 Chapter 14 Automatic Transfer Controller To activate ATC1 in the software, first complete steps (1) to (6), then set the AT1ACT flag in the AT1CNT0 register. After the AT1ACT flag is set, ATC1 is started and data transfer is started. The hardware automatically clears AT1ACT flag when ATC1 is activated. On the standard transfer mode, set a program that sets flags as much as the data transfer needs.
Page 475: Chapter 15 A/D Converter
Chapter 15 A/D Converter...
Page 476: Overview
Chapter 15 A/D Converter 15-1 Overview This LSI has an A/D converter with 10 bits resolution. That has a built-in sample hold circuit, and software can switch channel 0 to 6 (AN0 to AN6) to analog input. As A/D converter is stopped, the power consump- tion can be reduced by a built-in ladder resistance.
Page 477: Block Diagram
15-1-2 Block Diagram ANCTR1 ANCTR0 ANCHS0 ANCHS1 ANCHS2 ANLADE ANCK0 ANCK1 ANSH0 ANSH1 fs/2 fs/4 fs/8 Figure 15-1-1 ANCTR2 interrupt control ANSTSEL A/D conversion ANST Sample and 10 bits A/D hold comparator A/D Converter Block Diagram Chapter 15 IRQ3(P23) ANBUF0 ANBUF1 External ANBUF10...
Page 478: Control Registers
Chapter 15 A/D Converter 15-2 Control Registers A/D converter consists of the control register (ANCTRn) and the data storage buffer (ANBUFn). 15-2-1 Registers Table 15-2-1 shows the registers used to control A/D converter. Table 15-2-1 A/D Converter Control Registers Register Address ANCTR0 x'03FB0'...
Page 479 15-2-2 Control Registers A/D Converter Control Register 0 (ANCTR0) ANSH1 ANSH0 ANCK1 ANCK0 ANCTR0 Figure 15-2-1 A/D Converter Control Register 0 (ANCTR0 : x'03FB0', R/W) ANLADE Chapter 15 (At reset : 0 0 0 0 - - - ) ANLADE A/D ladder resistance control A/D ladder resistance OFF A/D ladder resistance ON...
Page 480 Chapter 15 A/D Converter A/D Converter Control Register 1 (ANCTR1) ANCTR1 Figure 15-2-2 A/D Converter Control Register 1 (ANCTR1 : x'03FB1', R/W) A/D Converter Control Register 2 (ANCTR2) ANST ANSTSEL ANCTR2 Figure 15-2-3 A/D Converter Control Register 2 (ANCTR2 : x'03FB2', R/W) XV - 6 Control Registers RESERVED...
Page 481: Data Buffers
15-2-3 Data Buffers A/D Conversion Data Storage Buffer 0 (ANBUF0) The lower 2 bits from the result of A/D conversion are stored to this register. ANBUF0 ANBUF07 ANBUF06 Figure 15-2-4 A/D Conversion Data Buffer 0 (ANBUF0 : x'03FB3', R) A/D Conversion Data Storage Buffer 1 (ANBUF1) The upper 8 bits from the result of A/D conversion are stored to this register.
Page 482: Operation
Chapter 15 A/D Converter 15-3 Operation Here is a description of A/D converter circuit setup procedure. Set the analog pins. Set the analog input pin, set in (2), to "special function pin" by the port A input mode register (PAIMD). * Setup for the port A input mode register should be done before analog voltage is put to pins.
Page 483 A/D conversion clock ANST flag A/D conversion start A/D interrupt (ADIRQ) Figure 15-3-1 Operation of A/D Conversion To read the value of the A/D conversion, A/D conversion should be done several times to prevent noise error by confirming the match of level by program, or by using the average value.
Page 484: Setup
Chapter 15 A/D Converter 15-3-1 Setup Input Pins of A/D Converter Setup Input pins for A/D converter is selected by the ANCH2 to 0 flag of the ANCTR1 register. Table 15-3-1 Clock of A/D Converter Setup The A/D converter clock is set by the ANCK1 to 0 flag of the ANCTR0 register. Set the A/D converter clock (T ) more than 800 ns and less than 15.26 s.
Page 485 Built-in Ladder Resistor Control The ANLADE flag of the ANCTR0 register is set to "1" to send a current to the ladder resistance for A/ D conversion. As A/D converter is stopped, the ANLADE flag of the ANCTR0 register is set to "0" to save the power consumption.
Page 486: 15-3-2 Setup Example
Chapter 15 A/D Converter 15-3-2 Setup Example A/D Converter Setup Example by Registers A/D conversion is started by setting registers. The analog input pins are set to AN0, the converter clock is set to fs/4, and the sampling hold time is set to TAD x 6. Then, A/D conversion complete interrupt is generated.
Page 487 Setup Procedure Set the A/D ladder resistance. ANCTR0 (x'3FB0') bp3 : ANLADE = 1 Start the A/D conversion. ANCTR2 (x'3FB2') bp6 : ANSTSEL = 0 (9) Start the A/D conversion operation. ANCTR2 (x'3FB2') bp7 : ANST = 1 (10) Complete the A/D conversion. ANBUF0 (x'3FB3') ANBUF1 (x'3FB4') Note : The above (3) to (4) can be set at once.
Page 488 Chapter 15 A/D Converter A/D Conversion Setup Example by External Interrupt 3 The A/D conversion is started by the external interrupt 3. The analog input pin is set to AN0, the con- verter clock is set to fs/4, and the sample hold time is set to TAD x 6. Then, the A/D conversion complete interrupt is generated.
Page 489 Setup Procedure Enable the interrupt. ADICR (x'3FFA') bp1 : ADIE = 1 Set the A/D ladder resistance. ANCTR0 (x'3FB0') bp3 : ANLADE = 1 (9) Select the A/D converter activation factor. ANCTR2 (x'3FB2') bp6 : ANSTSEL = 1 (10) Start the A/D conversion. ANCTR2 (x'3FB2') bp7 : ANST = 1 (11) Complete the A/D conversion.
Page 490: Cautions
Chapter 15 A/D Converter 15-3-3 Cautions A/D conversion can be damaged by noise easily, therefore, anti-noise measures should be taken ad- equately . Anti-noise measures To A/D input (analog input pin), add condenser near the V Figure 15-3-2 Figure 15-3-3 XV - 16 Operation REF+...
Page 491 To maintain high precision of A/D conversion, following instructions on use of A/D con- verter should be strictly kept. Input impedance R of A/D input pin should be under 500 k external capacitor C (over 1000 pF, under 1 F) pin.
Page 493: Chapter 16 D/A Converter
Chapter 16 D/A Converter...
Page 494: Overview
Chapter 16 D/A Converter 16-1 Overview This LSI has a built-in D/A converter with 8 bits solution. There are 2 output channels and 8-bit data registers for each channel. When the D/A converter is not used, the built-in ladder resistance can be set to OFF to save the power consumption.
Page 495: Operation
16-2 Operation The D/A converter circuit setup procedure is as follows: Set the analog pins. Set the analog input pin, set in (2), to "special function pin" by the port A input mode register (PAIMD). * Setup for the port A input mode register should be done before analog voltage is put to pins. Select the analog output pin.
Page 496: Control Registers
Chapter 16 D/A Converter 16-3 Control Registers 16-3-1 Overview Table 16-3-1 shows the registers to control the D/A converter in MN101C77C. Table 16-3-1 D/A Converter Control Registers Register Address DACTR x'03FBE' DADR01 x'03FBF' PADIR x'03F3A' PAPLUD x'03F4A' PAIMD x'03F3C' R/W : Readable/Writable XVI - 4 Control Registers Function...
Page 497 16-3-2 Control Register (DACTR) This is the 8-bit readable/writable register that controls the D/A conversion. D/A Converter Control Register (DACTR) DACTR Figure 16-3-1 D/A Converter Control Register (DACTR : x'03FBE' R/W) DABUSY DACH1 DACH0 DACH0 DACH1 DABUSY Chapter 16 (At reset : - - - - - 0 X X ) PA0 pin control General port D/A output...
Page 498: Input Data Register
Chapter 16 D/A Converter 16-3-3 Input Data Registers These readable/writable registers store the A/D converter data. D/A Converter Input Data Register 01 (DADR01) This register stores the D/A conversion data (for DA01 channel). ( At reset : X X X X X X X X ) DADR1 DA01BUF7 DA01BUF6 DA01BUF5 DA01BUF4 DA01BUF3 DA01BUF2 DA01BUF1 DA01BUF0 Figure 16-3-2 D/A Converter Input Data Register 01 (DADR01 : x'03FBF' R/W)
Page 499: Setup Example
16-4 Setup Example Channel fixed D/A Converter Setup Example Conversion channel should be set to DA0. An example setup procedure, with a description of each step is shown below. Setup Procedure Set the port A pin. PAIMD (x'3F3C') bp0 : PAIMD0 = 1 PADIR (x'3F3A') bp0 : PADIR0 = 0 PAPLUD (x'3F4A')
Page 501: Chapter 17 Appendices
Chapter 17 Appendices...
Page 502: 17-1 Probe Switches
Chapter 17 Appendices 17-1 Probe Switches 17-1-1 PRB-MBB101C77-M - This probe must be used with the following boards. Connector board: PX-CN101-M MBB board: PRB-MBB101C77-M Adapter board: PRB-ADP101-64-M Dummy target: PRB-DMY101C77-M The dummy target should be connected when ICE is operated independently, the adapter board should be connected at connection to the target.
Page 503: 17-1-2 Px-Cn101-M
17-1-2 PX-CN101-M This board can be used for any MBB models (product No. PRB-MBB101∗∗∗-M) of MN101 series. (Please visit our website for the latest information on the product.) Figure1: PX-CN101-M Layout < How to connect > MBB board (PRB-MBB101∗∗∗-M) Figure2: PX-CN101-M connection [Caution1] Connect CNC of PX-CN101-M to CNC of PRB-MBB101∗∗∗-M, and CND of PX-CN101-M to CND of PRB-MBB101∗∗∗-M.
Page 504 Chapter 17 Appendices 17-1-3 PRB-ADP101-64-M When connected to the target, use this board with MBB board. This board can be used with the following boards. (The product type is subject to change without prior notice. The latest information should be confirmed on our web site.) PRB-MBB101C52-M PRB-MBB101C58-M Improper matching may cause any damage to the ICE.
Page 505: 17-1-4 Prb-Dmy101C77-M
17-1-4 PRB-DMY101C77-M Dummy target boards differ depending upon the models. This board can be used for only 101C77 64PIN. When unconnected to the target, use this board with the PRB-MBB101C77-M. Improper matching may cause any damage to the ICE. < How to connect > Dummy target: PRB-DMY101C77-M [Caution1] Connect CNE of PRB-MBB101C77-M to CNE of PRB-DMY101C77-M, and CNF of...
Page 506: Special Function Registers List
Chapter 17 Appendices 17-2 Special Function Registers List Address Register Bit 7 SOSCDBL X'3F00' CPUM IOW1 X'3F01' MEMCTR I/O Wait Setup X'3F02' WDCTR CS8EXT X'3F03' AREACTR CS1MD X'3F05' CSMD01 Bus mode selection CS3MD X'3F06' CSMD23 Bus mode selection CS5MD X'3F07' CSMD45 Bus mode selection...
Page 507 Address Register Bit 7 Bit 6 PAOUT6 X'3F1A' PAOUT P8LED7 P8LED6 X'3F1D' P8LED P6SYO7 P6SYO6 X'3F1E' P6SYO P0IN6 X'3F20' P0IN X'3F21' P1IN P2IN7 X'3F22' P2IN X'3F25' P5IN P6IN7 P6IN6 X'3F26' P6IN P7IN7 P7IN6 X'3F27' P7IN P8IN7 P8IN6 X'3F28' P8IN PAIN6 X'3F2A' PAIN X'3F2B'...
Page 508 Chapter 17 Appendices Address Register Bit 7 P6DIR7 X'3F36' P6DIR P7DIR7 X'3F37' P7DIR P8DIR7 X'3F38' P8DIR X'3F3A' PADIR X'3F3C' PAIMD IRQ4SEL X'3F3E' P6IMD IRQ4 Interrupt Source Selection X'3F40' P0PLU X'3F41' P1PLU X'3F42' P2PLU X'3F45' P5PLU P6PLU7 X'3F46' P6PLU P7PLUD7 X'3F47' P7PLUD P8PLU7 X'3F48'...
Page 509: Time Base Timer
Address Register Bit 7 Bit 6 TM1OC7 TM1OC6 X'3F53' TM1OC X'3F54' TM0MD X'3F55' TM1MD X'3F56' CK0MD X'3F57' CK1MD TM4BC7 TM4BC6 X'3F60' TM4BC TM5BC7 TM5BC6 X'3F61' TM5BC TM4OC7 TM4OC6 X'3F62' TM4OC TM5OC7 TM5OC6 X'3F63' TM5OC X'3F64' TM4MD X'3F65' TM5MD X'3F66' CK4MD X'3F67' CK5MD TM6BC7...
Page 510 Chapter 17 Appendices Address Register Bit 7 TM7BCL7 TM7BCL X'3F70' TM7BCH7 X'3F71' TM7BCH TM7OC1L7 X'3F72' TM7OC1L TM7OC1H7 X'3F73' TM7OC1H TM7PR1L7 X'3F74' TM7PR1L TM7PR1H7 X'3F75' TM7PR1H TM7ICL7 X'3F76' TM7ICL TM7ICH7 X'3F77' TM7ICH Reserved Set Always X'3F78' TM7MD1 to "0" T7ICEDG X'3F79' TM7MD2 Capture Trigger Edge Selection...
Page 511 Address Register Bit 7 Bit 6 TXBUF07 TXBUF06 X'3F91' TXBUF0 SC0CE1 SC0REN X'3F92' SC0MD0 Transmission/ Reception data Reception Data Polarity Change Edge Selection SC0IOM SC0SBTS X'3F93' SC0MD1 Data Input SBT Pin Function Pin Selection Selection SC0FM1 SC0FM0 X'3F94' SC0MD2 Specify Flame Mode SC0TBSY SC0RBSY X'3F95'...
Page 512 Chapter 17 Appendices Address Register Bit 7 X'3FAE' SC3ODC X'3FAF' SC3CKS ANSH1 X'3FB0' ANCTR0 A/D Sample Hold Timer Setup X'3FB1' ANCTR1 ANST ANCTR2 X'3FB2' A/D Conversion Status ANBUF07 X'3FB3' ANBUF0 A/D Conversion Data Storage Register (Lower 2 bits) ANBUF17 X'3FB4' ANBUF1 DACTR X'3FBE'...
Page 513 Bit Symbol /Initial Value /Description Address Register Bit 7 Bit 6 Bit 5 Bit 4 BTSTP X'3FD1' ATCNT1 Burst Transfer Enable flag AT1TRC7 AT1TRC6 AT1TRC5 AT1TRC4 X'3FD2' AT1TRC ATC1 Transfer Count Setting AT1MAP0L7 AT1MAP0L6 AT1MAP0L5 AT1MAP0L4 AT1MAP0L3 AT1MAP0L2 AT1MAP0L1 AT1MAP0L0 X'3FD3' AT1MAP0L ATC1 Memory Pointer 0 Lower 8 bits...
Page 514 Chapter 17 Appendices Address Register Bit 7 TBLV1 X'3FF0' TBICR Specify TB Interrupt Level TM7LV1 X'3FF1' TM7ICR Specify TM7 Interrupt Level T7OC2LV1 X'3FF2' T7OC2ICR Specify T7OC2 Interrupt Level SC0RLV1 X'3FF4' SC0RICR Specify SC0 Reception Interrupt Level SC0TLV1 X'3FF5' SC0TICR Specify SC0 Transmission Interrupt Level SC1RLV1 X'3FF6'...
Page 515 Address Register Bit 7 Bit 6 I2CAD7 I2CAD6 X'3FA3' SC4AD0 SELI2C Reserved X'3FA4' Communication SC4AD1 Enable I2CTXB7 I2CTXB6 X'3FA5' SC4TXB I2CRXB7 I2CRXB6 X'3FAD' SC4RXB I2CINT Transfer X'3FAC' Interrupt SC4STR Direction Detection Determination X'3F3F' SC4ODC0 X'3F3D' SC4ODC1 SC4LV1 SC4LV0 X'3FF3' SC4ICR SC4 Interrupt Level Setup Bit Symbol / Initial Value / Description Bit 5...
Page 516: Instruction Set
Chapter 17 Appendices 17-3 Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Data Move Instructions MOV Dn,Dm Dn Dm MOV imm8,Dm imm8 Dm MOV Dn,PSW Dn PSW MOV PSW,Dm PSW Dm MOV (An),Dm mem8(An) Dm MOV (d8,An),Dm mem8(d8+An) Dm MOV (d16,An),Dm mem8(d16+An) Dm MOV (d4,SP),Dm...
Page 517 MN101C SERIES INSTRUCTION SET Flag Group Mnemonic Operation Code Cycle Re- Size peat VF NF CF ZF -- -- -- -- 6 MOVW imm16,Am imm16 Am -- -- -- -- 3 MOVW SP,Am SP Am -- -- -- -- 3 MOVW An,SP An SP -- -- -- -- 3...
Page 518 Chapter 17 Appendices MN101C SERIES INSTRUCTION SET Group Mnemonic Operation NOT Dn Dn Dn= ASR Dn Dn.msb temp,Dn.lsb CF Dn>>1 Dn,temp Dn.msb LSR Dn Dn.lsb CF,Dn>>1 Dn 0 Dn.msb ROR Dn Dn.Isb temp,Dn>>1 Dn CF Dn.msb,temp CF Bit manipulation instructions BSET BSET (io8)bp mem8(IOTOP+io8)&bpdata...PSW 0...
Page 519 MN101C SERIES INSTRUCTION SET Group Mnemonic Operation BGT label if((VF^NF)|ZF=0),PC+6+d11(label)+H PC -- -- -- -- if((VF^NF)|ZF=1),PC+6 PC BHI label if(CFIZF=0),PC+5+d7(label)+H PC -- -- -- -- if(CFIZF=1), PC+5 PC BHI label if(CFIZF=0),PC+6+d11(label)+H PC -- -- -- -- if(CFIZF=1), PC+6 PC BLS label if(CFIZF=1),PC+5+d7(label)+H PC -- -- -- -- if(CFIZF=0), PC+5 PC BLS label...
Page 520 Chapter 17 Appendices MN101C SERIES INSTRUCTION SET Group Mnemonic TBZ (io8)bp,label TBZ (io8)bp,label TBZ (abs16)bp,label TBZ (abs16)bp,label TBNZ TBNZ (abs8)bp,label TBNZ (abs8)bp,label TBNZ (io8)bp,label TBNZ (io8)bp,label TBNZ (abs16)bp,label TBNZ (abs16)bp,label JMP (An) JMP label JSR (An) JSR label JSR label JSR label JSRV (tbl4) XVII - 20...
Page 521 MN101C SERIES INSTRUCTION SET Group Mnemonic Operation mem8(SP) (PC).bp7-0 mem8(SP+1) (PC).bp15-8 mem8(SP+2).bp7 (PC).H mem8(SP+2).bp1-0 (PC).bp17-16 SP+3 SP mem8(SP) PSW mem8(SP+1) (PC).bp7-0 mem8(SP+2) (PC).bp15-8 mem8(SP+3).bp7 (PC).H mem8(SP+3).bp1-0 (PC).bp17-16 mem8(SP+4) HA-l mem8(SP+5) HA-h SP+6 SP Contorl instructions REP imm3 imm3-1 RPC Other than the instruction of MN101C Series,the assembler of this Series has the following instructions as macro instructions.
Page 522: Instruction Map
Chapter 17 Appendices 17-4 Instruction Map MN101C SERIES INSTRUCTION MAP 1st nibble\2nd nibble MOV #8,(io8) RTI JSR d12(label) JSR d16(label) MOV #8,(abs8)/(abs12) PUSH An When the exension code is b'oo10' When the extension code is b'0011' MOV (abs12),Dm MOV Dn,(abs12) MOV (io8),Dm MOV Dn,(io8) ADD #4,Dm...
Page 523 Extension code: b'0011' 2nd nibble\ 3rd nibble TBZ (abs8)bp,d7 TBNZ (abs8)bp,d7 CMP Dn,Dm ADD Dn,Dm TBZ (io8)bp,d7 TBNZ (io8)bp,d7 OR Dn,Dm AND Dn,Dm BSET (io8)bp JMP abs18(label) XOR Dn,Dm / XOR #8,Dm ADDC Dn,Dm C BSET (abs16)bp D BTST (abs16)bp TBZ (abs16)bp,d7 TBNZ (abs16)bp,d7 TBZ (abs8)bp,d11...
Page 525: Chapter 18 Flash Eeprom
Chapter 18 Flash EEPROM...
Page 526: Overview
Chapter 18 Flash EEPROM 18-1 Overview 18-1-1 Overview The MN101CF77G is equivalent to MN101C77C except its Mask ROM is substituted with 128 KB of flash EEPROM. Operating voltage of MN101CF77G is as follows. MN101CF77G Operating voltage: V Normal operation is guaranteed with up to ten programmings. *1 The MN101CF77G is programmed in one of two modes;...
Page 527 If serial interface communication pins (P53, P54, P05 and P03) are in floating state, this Flash EEPROM version may enter the onboard programming mode even when the serial writer is not connected to it (on-board programming mode is not selected). To avoid this, set the pull-up resistors on the target board, or design the circuit in such a way that the pins are "H"...
Page 528: Differences Between Mask Rom Version And Eprom Version
Chapter 18 Flash EEPROM 18-1-2 Differences between Mask ROM version and EPROM version Table 18-1-1 shows differences between 8-bit microcontroller MN101C77C (Mask ROM version), MN101CF77G (EPROM version) . Table 18-1-1 Differences between Mask ROM version and EPROM version Operating temperature Operating Voltage Current consumption Oscillation characteristics...
Page 529: Pin Descriptions
18-2 Pin Descriptions AN3/PA3 AN4/PA4 AN5/PA5 AN6/PA6 VREF+ OSC2 OSC1 MMOD NRST/P27 TXD1A/SBO1A/P00 SDA4B/RXD1A/SBI1A/P01 Figure18-2-1 Pin Configuration ( LQFP064-P-1414 ) MN101CF77G (TOP VIEW) Chapter 18 Flash EEPROM P73/SBO1B/TXD1B P72/SBT0B P71/SBI0B/RXD0B P70/SBO0B/TXD0B P67/SDO7/KEY7 P66/SDO6/KEY6 P65/SDO5/KEY5 P64/SDO4/KEY4 P63/SDO3/KEY3 P62/SDO2/KEY2 P61/SDO1/KEY1 P60/SDO0/KEY0 P54/SCL4A P53/SDA4A P52/SBT3/SCL3 P51/SB03/SDA3...
Page 530 Chapter 18 Flash EEPROM 18-3 Electrical Characteristics Contents Structure Application 18-3-1 Absolute Maximum Ratings Parameter Power supply voltage Input clamp current (SENS) Input pin voltage Output pin voltage I/O pin voltage Peak output current Average output current *1 Power dissipation Operating temperature Storage temperature Applied to any 100 ms period.
Page 531 18-3-2 Operating Conditions Parameter Symbol Power supply voltage *1 Power supply voltage Voltage to maintain RAM data Operation speed *1 Minimum instruction execution time Parameter Symbol Programming voltage *2 Flash EEPROM DDEW program/erase voltage PPEW exept during Flash EEPROM program/erase. Operating tempreture during programming should be within 0 °C to +50 °C .
Page 532: Electrical Characteristics
Chapter 18 Flash EEPROM 18-3-3 DC Characteristics Param eter Pow er s upply current (no load at output pin) *1 Pow er s upply current Supplu current during H ALT1 m ode Supply current during STOP m ode - Measured under conditions of no load, or power down on analog blocks. (Pull-up resistance should be unconnected.) - The supply current during operation, I tions :...
Page 533: Reprogramming Flow
18-4 Reprogramming Flow Figure 18-4-1 shows the flow for reprogramming (erasing and programming) the flash EEPROM. As the figure shows, the User Data Program starts after the memory is erased. Figure 18-4-1 Start write routine (User Data Program) only after erase routine is completely finished. How- ever, you can program our product which is already erased without this process.
Page 534: Prom Writer Mode
Chapter 18 Flash EEPROM 18-5 PROM writer mode In PROM writer mode, the CPU is halted for Internal flash EEPROM to be programed. The microcontroller is inserted into a dedicated adaptor socket, which connects to a PROM writer. When the microcontroller connects to the adaptor socket, it automatically enters PROM writer mode.
Page 535 Pin Configuration for Socket Adaptor <Open> VREF+ OSC2 <Open> OSC1 MMOD MMOD ERASE Figure 18-5-2 Pin Configuration for Socket Adaptor MN101CF77G (TOP VIEW) Chapter 18 Flash EEPROM <Open> <Open> XVIII - 11 PROM writer mode...
Page 536: Onboard Serial Programming Mode
Chapter 18 Flash EEPROM 18-6 Onboard Serial Programming Mode 18-6-1 Overview The onboard serial programming mode is primarily used to program the flash EEPROM in devices that are already installed on a PCB board with internal serial interface. Hardware and software requirements Hardware and software products required for onboard serial programming are as follows.
Page 537: Circuit Requirements For The Target Board
18-6-2 Circuit Requirements for the Target Board (in Clock Synchronous Communication using the YDC Serial Writer) This section describes the circuit requirements for the target board for onboard serial programming with the serial interface 0 using YDC serial writer. NRST Serial Writer Figure 18-6-1...
Page 538 Chapter 18 Flash EEPROM This section describes each memory space of Flash EEPROM. X'04000' X'040C0+n' X'06000' X'06008' Branch Instruction for branching to Reset Start Routine X'0600C' Branch Instruction for branching to Interrupt Service Routine X'06088' X'23FFF' *1 Security code can be set to any 8-bit area between x'06000' to x'07FFF'. Serial writer load program area This KB of ROM at address x'04000' to n KB holds the load program for the serial writer.
Page 539 Use of YDC serial writer You must write the load program to this LSI before installed in the target board. The load program usually comes with onboard serial writer. Erase block 0 (load program) is write/erase-protected in the hardware during onboard programming mode.
Page 540: Communication Using The Panax Serial Writer)
Chapter 18 Flash EEPROM 18-6-3 Circuit Requirements for the Target Board (in Clock Synchronous Communication using the PanaX Se- rial Writer) In programming Flash EEPROM using the PanaX serial writer, you need not to write load program in advance and also be able to use all space of the Flash EEPROM as user program area. Use P53, P54 for communication with serial writer.
Page 541 Use of PanaX serial writer (DWIRE programming) You need not to write load program in advance and also be able to use all space of the Flash EEPROM as user program area. pin must supply 5.0 V from external power source. P53 and P54 pins should be reserved as dedicated pins for serial writer to prevent other user circuits on the target board from communicating with the device.
Page 542 Chapter 18 Flash EEPROM To connect resistors in series with communication pins (NRST, P53, P54) When resistors are connected in series with communication pins, signal spectrum speed drops affected by the load capacity. To ensure effecting reliable communication, the required time in which the operating voltage reaches to 63% of the time constant must be shorter than 1/8 of communication cycle.
Page 543 MN101C77C/F77G LSI User's Manual February, 2004 1st Edition Issued by Matsushita Electric Industrial Co., Ltd. © Matsushita Electric Industrial Co., Ltd.
Page 544 [PANABRAS] — Shum Yip Centre Office: 25F, Shum Yip Centre, #5045, East Shennan Road, Shenzhen, China Tel:86-755-8211-0888 Panasonic Shun Hing Industrial Sales (Hong Kong) Co., Ltd. [PSI(HK)] 11th Floor, Great Eagle Center 23 Harbour Road, Wanchai, Hong Kong [PIE] Tel:852-2529-7322 ˜...

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Panaxseries mn101c77c Panaxseries mn101f77g

Panasonic F77G User Manual

Chapter 1 Overview

Chapter 3 Interrupts

Chapter 4 I/O Ports

Chapter 5 Prescaler

Chapter 6 8-Bit Timers

Chapter 7 16-Bit Timer

Chapter 8 Time Base Timer / 8-Bit Free-Running Timer

Chapter 9 Watchdog Timer

Chapter 10 Buzzer

Chapter 11 Serial Interface

Chapter 2 CPU Basics

Chapter 12 Serial Interface 3

Chapter 13 Serial Interface

Chapter 14 Automatic Transfer Controller

Chapter 15 A/D Converter

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