Page 1 MICROCOMPUTER MN102H75K/F75K/85K/F85K LSI User’s Manual MN102H Pub.No.22385-011E...
Page 3 Request for your special attention and precautions in using the technical information and semiconductors described in this book...
Page 4: Table Of Contents
Contents Contents About This Manual ............16 Using This Manual.
Page 5 4.5.1 Setting Up an Event Counter Using Timer 0 ......... . . 82 4.5.2 Setting Up an Interval Timer Using Timers 1 and 2 .
Page 6 Contents 6.4.2 Single Channel/Single Conversion Timing ......... . . 145 6.4.3 Multiple Channel/Single Conversion Timing .
Page 7 7.13.3 Controlling Shuttering Effects ........... . . 198 7.13.4 Controlling Line Shuttering .
Page 8 Contents I/O Ports..............251 11.1 Description.
Page 9 B.4.2 Circuit Requirements for the Target Board ......... . . 321 B.4.3 Microcontroller Hardware Used in Onboard Serial Programming .
Page 10 List of Tables List of Tables General Specifications ..............26 Block Diagram Explanation .
Page 11 IR Remote Signal Receiver Registers ........... . . 223 HEAMA and 5-/6-Bit Data Pulse Widths .
Page 12 List of Figures List of Figures Conventional vs. MN102H Series Code Assignments ......... 19 Three-Stage Pipeline .
Page 13 4-20 One-Shot Pulse Output Timing (16-Bit Timers) ..........91 4-21 External Count Direction Control Timing (16-Bit Timers) .
Page 14 List of Figures 5-12 Serial Interface Clock Timing ............136 5-13 Master Transmitter Timing in I 5-14...
Page 15 7-31 Shuttered Area Setup Examples ............195 7-32 Shutter Movement Setup Examples.
Page 16 List of Figures 11-16 P30/CLH and P33/CLL (Port 3) ............267 11-17 P34/VREF (Port 3) .
Page 17: About This Manual
About This Manual This manual is intended for assembly-language programming engineers. It describes the internal configuration and hardware functions of the MN102H75K and MN102H85K microcontrollers. Except when discusssiing differing specifi- cations,this manual refers to the two microcontrollers as a single device : MN102H75K/85K.
Page 18: Related Documents
About This Manual Related Documents Related Documents MN102H75K/F75K/85K/F85K LSI User Manual MN102H Series LSI User Manual (Describes the core hardware.) MN102H Series Instruction Manual (Describes the instruction set.) MN102H Series C Compiler User Manual: Usage Guide (Describes the installation, commands, and options for the C compiler.) MN102H Series C Compiler User Manual: Language Description (Describes the syntax for the C compiler.) MN102H Series C Compiler User Manual: Library Reference...
Page 19: General Description
General Description The 16-bit MN102H series is the high-speed linear addressing version of the MN10200 series. The new architecture in this series is designed for C-language programming and is based on a detailed analysis of the requirements for embedded applications. From miniaturization to power savings, it provides for a wide range of needs in user systems, surpassing all previous architectures in speed and functionality.
Page 20: Conventional Vs. Mn102H Series Code Assignments
General Description MN102H Series Features MN102H75K/F75K/85K/F85K LSI User Manual Single-byte basic instruction length The MN102H series has replaced general registers with eight internal CPU registers divided functionally into four address registers (A0 - A3) and four data registers (D0 - D3). The program can address a register pair in four or less bits, and basic instructions such as register-to-register operations and load/store operations occupy only one byte.
Page 21: Mn102H Series Interrupt Servicing
Panasonic Semiconductor Development Company Fast interrupt response MN102H series devices can stop executing instructions, even those with long execution cycles, to service interrupts immediately. After an interrupt occurs, the program branches to the interrupt service routine within six cycles or less. The architecture also includes a programmable interrupt handler, which allows you to adjust interrupt servicing speed within the software when necessary, improving real-time control performance.
Page 22: Mn102H Series Description
General Description MN102H Series Description The MN102H series is the flagship product for Panasonic’s new high-per- formance architecture. Panasonic will expand the series as it strives to improve the CPU core’s performance and speed, and as it develops devices incorporating ASSPs, ASICs, internal EPROM, and other products to meet the needs of a wide array of embedded designs.
Page 23 NX: Extension negative flag ZX: Extension zero flag VF: Overflow flag CF: Carry flag NF: Negative flag ZF: Zero flag Panasonic Semiconductor Development Company If the most significant bit of the result of an operation has the value 1, this flag is set;...
Page 24: Internal Registers, Memory, And Special Function Registers
General Description MN102H Series Description Internal registers, memory, and special function registers Program Counter Address Registers Data Registers Multiplication/Division Register Processor Status Word Memory, SFRs, and I/O Ports CPUM, EFCR, IAGR NMICR, xxICR SCCTRn, TRXBUFn, SCSTRn ANCTR, ANnBUF TMn, BCn, BRn, ... MEMMD PnOUT, PnIN, PnDIR Note:...
Page 25: Address Space
Address space The memory in the MN102H series is configured as linear address space. The instruction and data areas are not separated, so the basic segments are internal ROM, internal RAM, and special function registers. Figure 1-5 shows the address space for the MN102H75K/85K.The internal ROM contains the instructions and the font data for the on-screen display (OSD), in any location.
Page 26: Interrupt Controller Configuration
General Description MN102H Series Description Interrupt controller An interrupt controller external to the core controls all nonmaskable and maskable interrupts except reset. There are a maximum of sixteen interrupt classes (class 0 to 15). Each class can have up to four interrupt factors and any of seven priority levels.
Page 27: General Specifications
Table 1-1 General Specifications Panasonic Semiconductor Development Company General Specifications Parameter Structure Internal multiplier (16-bit × 16-bit = 32-bit) and saturate calculator Load/store architecture Eight registers: Four 24-bit data registers Four 24-bit address registers Other: 24-bit program counter 16-bit processor status word 16-bit multiply/divide register Instruction set 41 instructions...
Page 28 General Description General Specifications Table 1-1 General Specifications MN102H75K/F75K/85K/F85K LSI User Manual Parameter Timer/counters Four 8-bit timers: Cascading function (forming 16- or 32-bit timers) Timer output Selectable clock source (internal or external) Serial interface clock generation Start timing generation for analog-to-digital converter Two 16-bit timers: Compare/capture registers Selectable clock source (internal or external)
Page 29: Block Diagram
Address registers Multiplier Program Counter Incrementer Program address ROM bus Internal ROM Internal RAM Panasonic Semiconductor Development Company Block Diagram Data registers Multiplication/Division Register Operand address B u s c o n t r o l l e r RAM bus External interface External extension bus Figure 1-8 Functional Block Diagram...
Page 30: Block Diagram Explanation
General Description Block Diagram Table 1-2 Block Diagram Explanation MN102H75K/F75K/85K/F85K LSI User Manual Block Clock generator An oscillation circuit connected to an external crystal supplies the clock to all blocks within the CPU. Program counter The program counter generates addresses for queued instruc- tions.
Page 31: Pin Descriptions
1.6.1 Notes: Panasonic Semiconductor Development Company Pin Descriptions MN102H85K Pin Description P00, RMIN, IRQ0 * P01, SDA1 * P02, SCL1 P03, ADIN0 P04, ADIN1 P05, ADIN2 P06, ADIN3 P07, ADIN4 P10, ADIN5, IRQ1 P11, ADIN6, IRQ2 64-Pin SDIP P12, ADIN7, IRQ3 Top View P13, ADIN8, WDOUT P14, ADIN9, STOP...
Page 32: Mn102H75K Pin Description
General Description Pin Descriptions 1.6.2 P55, SBO0 P54, IRQ5, VSYNC P53, RST P52, IRQ4, VI0 TEST P51, YS P50, SYSCLK P47, HSYNC P46, OSDXI P45, OSDXO * P44, TM5IC, HI1 * P43, TM5IOB, HI0 * P42, TM5IOA * P41, TM1IO VCOI Notes: 1.
Page 33: Pin Functions
Table 1-3 Pin Functions Block Pin Name Power SYSCLK OSC1 Clocks OSC2 OSDXI OSDXO Reset Interrupts (external) IRQ0–IRQ5 HSYNC VSYNC TMnIOA (n=4,5) 16-bit (2) TMnIOB (n=4,5) Timers TMnIC (n=4,5) 8-bit (4) TMnIO (n=0,1) SBI0/SBI1 SBD0/SBD1 Serial interfaces (2) SBO0/SBO1 SBT0/SBT1 SDA0/SDA1 C interfaces (2) SCL0/SCL1...
Page 34 General Description Pin Descriptions Table 1-3 Pin Functions (Continued) Block Pin Name P00–P07 P10–P17 I/O ports P20–P27 MN102H75K/HF75K: total 66 pins P30–P37 MN102H85K/HF85K: P40–P47 total 50 pins P50–P57 P60–P61 I/O ports only in P70–P77 MN102H75K/F75K P80–P87 CVBS0/CBVS1 Closed-caption decoders (2) VREFHS VREFLS A/D converter (12-channel)
Page 35: Power Supply Wiring
Considerations for power supply, clock, and reset pins Note: If the circuit uses the same power supply for digital and analog supplies, connect Note: The capacitance values vary depending on the oscillator. Note: The capacitance values vary depending on the oscillator. Connection the PLL circuit The MN102H75K/85K contains an internal PLL circuit.
Page 36: Bus Interface
General Description Bus Interface 1.7.1 The bus interface operates in external extension mode. Figure 1-15 provides the memory space for the MCU in this mode. MN102H75K/F75K/85K/F85K LSI User Manual Bus Interface Description External Expansion Mode x'000000' External devices x'008000' Internal RAM (*3) (8192 bytes (*4)
Page 37: Bus Interface Control Registers
1.7.2 The external memory wait register (EXWMD) and memory mode register 1 (MEMMD1) control the bus interface. EXWMD: External Memory Wait Register Bi t : 15 EW 33 EW 32 EW 31 EW 30 EW 23 EW 22 EW 21 EW 20 EW 13 EW 12 EW 11 EW 10 EW 03 EW 02 EW 01 EW 00 Res et : R/ W : R/ W EW[33:30], EW[23:20], EW[13:10], EW[03:00]...
Page 38: Interrupts
Interrupts Description Interrupts The most important factor in real-time control is an MCU’s speed in servicing interrupts. The MN102H75K/85K has an extremely fast interrupt response time due to its ability to abort instructions, such as multiply or divide, that require multiple clock cycles.
Page 39: Interrupt Vector Group And Class Assignments
Panasonic Semiconductor Development Company Group Interrupt Vector Group 0 NMIs Group 1 Watchdog timer MN102H CPU Core Group 2 Undefined instruction Group 3 Error interrupt Group 4 External interrupt 0 Levels 0 6 Group 5 External interrupt 1 Group 6 Group 7 Group 8 External interrupt 2...
Page 40: Handler Preprocessing
Interrupts Description Table 2-2 Handler Preprocessing Table 2-3 Handler Postprocessing MN102H75K/F75K/85K/F85K LSI User Manual Program Address 80008 Interrupt Handler (preprocessing) Max. 6 cycles Handler (postprocessing) Registers popped Figure 2-3 Interrupt Servicing Time Sequence Assembler Push registers -8,A3 A0,(A3) movx D0,(4,A3) Interrupt ACK (FC0E),D0 Generate header address...
Page 41: Interrupt Setup Examples
2.2.1 In this example, an interrupt occurs on a falling-edge signal from the IRQ0 (P00) external interrupt pin, and the interrupt priority level is 5. On reset, the external edge setting in the EXTMD register is low (b’00’ = active- low interrupt), and the IQ0IR bit of the IQ0ICL register is 0.
Page 42: Timing For External Pin Interrupt Setup (Example)
Interrupts Interrupt Setup Examples Servicing the interrupt The main program normally gen- erates and branches to the inter- rupt start address. During the interrupt service rou- tine, prevent the CPU from accepting any other maskable interrupts by setting the IM[2:0] and IE bits of the PSW to 0.
Page 43: Setting Up A Watchdog Timer Interrupt
2.2.2 In this example, a watchdog timer reset occurs. The watchdog timer starts running after a reset, when the NWDEN flag in the CPU mode register (CPUM) is enabled (set to 0). When the watchdog timer overflows, a nonmaskable interrupt occurs. This means that the watchdog timer must be cleared in the main The watchdog timer interrupt is provided for detecting and handling program.
Page 44: Timing For Watchdog Timer Interrupt Setup (Example)
Interrupts Interrupt Setup Examples The main program normally gen- If the CPU accepts an interrupt, the program branches to address x’080008’. erates and branches to the inter- rupt start address. The oscillator delay timer shares the counter for the watchdog timer. The oscillator delay timer is activated when the circuit exits the STOP mode, so the program must clear the WDID flag to 0 prior to entering the STOP mode.
Page 45: Interrupt Control Registers
A control register is assigned to each interrupt vector group. Except for the class 0 registers (WDICR, PIICR, and EIICR), the control registers allow you to enable and set the priority level for interrupt groups. Below is the general format of the registers in class 0 and classes 1 to 11. Class 0 (X): XICR (System Interrupt) Bit:...
Page 46 Interrupts Interrupt Control Registers XnICL (System Interrupt) Bit: IR: Interrupt request flag ID: Interrupt detect flag The following is an example program setting an interrupt group’s priority level (LV field) and enabling the interrupt group (IE) in the interrupt control register (XnICH).
Page 47: Panasonic
Table 2-4 Interrupt Control Registers Panasonic Semiconductor Development Company Register Address IAGR x’00FC0E’ Accepted interrupt group number register WDICR x’00FC42’ Watchdog interrupt control register PIICR x’00FC44’ Undefined instruction interrupt control register EIICR x’00FC46’ Interrupt error interrupt control register EXTMD x’00FCF8’ External interrupt mode register IQ0ICL x’00FC48’...
Page 48 Interrupts Interrupt Control Registers Table 2-4 Interrupt Control Registers MN102H75K/F75K/85K/F85K LSI User Manual Register Address ADM3ICL x’00FC78’ Address 3 match interrupt control register (low) ADM3ICH x’00FC79’ Address 3 match interrupt control register (high) ADM2ICL x’00FC7A’ Address 2 match interrupt control register (low) ADM2ICH x’00FC7B’...
Page 49 IAGR: Accepted Interrupt Group Number Register Bit: Reset: R/W: GN[5:0]: Group Number EXTMD: External Interrupt Mode Register Bit: Reset: R/W: WDICR: Watchdog Interrupt Control Register Bit: The watchdog timer interrupt is Reset: provided for detecting and handling R/W: racing. Normal operation is not guaranteed if the program returns after a watchdog interrupt.
Page 50 Interrupts Interrupt Control Registers PIICR: Undefined Instruction Interrupt Control Register Bit: Reset: R/W: PIID: Undefined instruction interrupt detect flag EIICR: Interrupt error Interrupt Control Register Bit: Reset: R/W: IQ0ICL: External Interrupt 0 Interrupt Control Register (Low) Bit: Reset: R/W: IQ0IR: External interrupt 0 interrupt request flag IQ0ID: External interrupt 0 interrupt detect flag MN102H75K/F75K/85K/F85K LSI User Manual —...
Page 51 IQ0ICH: External Interrupt 0 Interrupt Control Register (High) Bit: Reset: R/W: IQ0LV[2:0]: External interrupt 0 interrupt priority level IQ0IE: External interrupt 0 interrupt enable flag IQ1ICL: External Interrupt 1 Interrupt Control Register (Low) Bit: Reset: R/W: IQ1IR: External interrupt 1 interrupt request flag IQ1ID: External interrupt 1 interrupt detect flag IQ1ICH: External Interrupt 1 Interrupt Control Register (High) Bit:...
Page 52 Interrupts Interrupt Control Registers IQ2ICL: External Interrupt 2 Interrupt Control Register (Low) Bit: Reset: R/W: IQ2IR: External interrupt 2 interrupt request flag IQ2ID: External interrupt 2 interrupt detect flag IQ2ICH: External Interrupt 2 Interrupt Control Register (High) Bit: Reset: R/W: IQ2LV[2:0]: External interrupt 2 interrupt priority level IQ2IE: External interrupt 2 interrupt enable flag IQ3ICL: External Interrupt 3 Interrupt Control Register (Low)
Page 53 IQ3ICH: External Interrupt 3 Interrupt Control Register (High) Bit: Reset: R/W: IQ3IE: External interrupt 3 interrupt enable flag IQ4ICL: External Interrupt 4 Interrupt Control Register (Low) Bit: Reset: R/W: IQ4IR: External interrupt 4 interrupt request flag IQ4ID: External interrupt 4 interrupt detect flag IQ4ICH: External Interrupt 4 Interrupt Control Register (High) Bit: Reset:...
Page 54 Interrupts Interrupt Control Registers IQ5ICL: External Interrupt 5 Interrupt Control Register (Low) Bit: Reset: R/W: IQ5IR: External interrupt 5 interrupt request flag IQ5ID: External interrupt 5 interrupt detect flag IQ5ICH: External Interrupt 5 Interrupt Control Register (High) Bit: Reset: R/W: IQ5IE: External interrupt 5 interrupt enable flag TM4CBICL: Timer 4 Compare/Capture B Interrupt Control Register (Low) x’00FC60’...
Page 55 TM4CBICH: Timer 4 Compare/Capture B Interrupt Control Register (High)x’00FC61’ Bit: Reset: R/W: TM4CBLV[2:0]: Timer 4 compare/capture B interrupt priority level TM4CBIE: Timer 4 compare/capture B interrupt enable flag TM4CAICL: Timer 4 Compare/Capture A Interrupt Control Register (Low) x’00FC62’ Bit: Reset: R/W: TM4CAIR: Timer 4 compare/capture A interrupt request flag TM4CAID: Timer 4 compare/capture A interrupt detect flag...
Page 56 Interrupts Interrupt Control Registers TM4UDICL: Timer 4 Underflow Interrupt Control Register (Low) Bit: Reset: R/W: TM4UDIR: Timer 4 underflow interrupt request flag TM4UDID: Timer 4 underflow interrupt detect flag TM4UDICH: Timer 4 Underflow Interrupt Control Register (High) Bit: Reset: R/W: TM4UDIE: Timer 4 underflow interrupt enable flag VBIICL: VBI (1) Interrupt Control Register (Low) Bit:...
Page 57 VBIICH: VBI (1) Interrupt Control Register (High) Bit: Reset: R/W: VBIIE: VBI (1) interrupt enable flag TM5CBICL: Timer 5 Compare/Capture B Interrupt Control Register (Low) x’00FC68’ Bit: Reset: R/W: TM5CBIR: Timer 5 compare/capture B interrupt request flag TM5CBID: Timer 5 compare/capture B interrupt detect flag TM5CBICH: Timer 5 Compare/Capture B Interrupt Control Register (High)x’00FC69’...
Page 58 Interrupts Interrupt Control Registers TM5CAICL: Timer 5 Compare/Capture A Interrupt Control Register (Low) x’00FC6A’ Bit: Reset: R/W: TM5CAIR: Timer 5 compare/capture A interrupt request flag TM5CAID: Timer 5 compare/capture A interrupt detect flag TM5CAICH: Timer 5 Compare/Capture A Interrupt Control Register (High) x’00FC6B’ Bit: Reset: R/W:...
Page 59 TM5UDICH: Timer 5 Underflow Interrupt Control Register (High) Bit: Reset: R/W: TM5UDIE: Timer 5 underflow interrupt enable flag VBIWICL: VBI (2) Interrupt Control Register (Low) Bit: Reset: R/W: VBIWIR: VBI (2) interrupt request flag VBIWID: VBI (2) interrupt detect flag VBIWICH: VBI (2) Interrupt Control Register (High) Bit: Reset:...
Page 60 Interrupts Interrupt Control Registers TM2UDICL: Timer 2 Underflow Interrupt Control Register (Low) Bit: Reset: R/W: TM2UDIR: Timer 2 underflow interrupt request flag TM2UDID: Timer 2 underflow interrupt detect flag TM2UDICH: Timer 2 Underflow Interrupt Control Register (High) Bit: Reset: R/W: TM2UDLV[2:0]: Timer 2 underflow interrupt priority level TM2UDIE: Timer 2 underflow interrupt enable flag TM1UDICL: Timer 1 Underflow Interrupt Control Register (Low)
Page 61 TM1UDICH: Timer 1 Underflow Interrupt Control Register (High) Bit: Reset: R/W: TM1UDIE: Timer 1 underflow interrupt enable flag TM0UDICL: Timer 0 Underflow Interrupt Control Register (Low) Bit: Reset: R/W: TM0UDIR: Timer 0 underflow interrupt request flag TM0UDID: Timer 0 underflow interrupt detect flag TM0UDICH: Timer 0 Underflow Interrupt Control Register (High) Bit: Reset:...
Page 62 Interrupts Interrupt Control Registers RMCICL: Remote Signal Receive Interrupt Control Register (Low) Bit: Reset: R/W: RMCIR: Remote signal receive interrupt request flag RMCID: Remote signal receive interrupt detect flag RMCICH: Remote Signal Receive Interrupt Control Register (High) Bit: Reset: R/W: RMCIE: Remote signal receive interrupt enable flag ADM3ICL: Address 3 Match Interrupt Control Register (Low) Bit:...
Page 63 ADM3ICH: Address 3 Match Interrupt Control Register (High) Bit: Reset: R/W: ADM3LV[2:0]: Address match 3 interrupt priority level ADM3IE: Address match 3 interrupt enable flag ADM2ICL: Address 2 Match Interrupt Control Register (Low) Bit: Reset: R/W: ADM2IR: Address match 2 interrupt request flag ADM2ID: Address match 2 interrupt detect flag ADM2ICH: Address 2 Match Interrupt Control Register (High) Bit:...
Page 64 Interrupts Interrupt Control Registers ADM1ICL: Address 1 Match Interrupt Control Register (Low) Bit: Reset: R/W: ADM1IR: Address match 1 interrupt request flag ADM1ID: Address match 1 interrupt detect flag ADM1ICH: Address 1 Match Interrupt Control Register (High) Bit: Reset: R/W: ADM1IE: Address match 1 interrupt enable flag ADM0ICL: Address 0 Match Interrupt Control Register (Low) Bit:...
Page 65 ADM0ICH: Address 0 Match Interrupt Control Register (High) Bit: Reset: R/W: ADM0IE: Address match 0 interrupt enable flag ANICL: A/D Conversion End Interrupt Control Register (Low) Bit: Reset: R/W: ANIR: A/D conversion end interrupt request flag ANID: A/D conversion end interrupt detect flag ANICH: A/D Conversion End Interrupt Control Register (High) Bit: Reset:...
Page 66 Interrupts Interrupt Control Registers SCT0ICL: Serial 0 Transmission End Interrupt Control Register (Low) x’00FC82’ Bit: Reset: R/W: SCT0IR: Serial 0 transmission end interrupt request flag SCT0ID: Serial 0 transmission end interrupt detect flag SCT0ICH: Serial 0 Transmission End Interrupt Control Register (High) x’00FC83’ Bit: Reset: R/W:...
Page 67 SCR0ICH: Serial 0 Reception End Interrupt Control Register (High) Bit: Reset: R/W: SCR0IE: Serial 0 reception end interrupt enable flag VBIVICL: VBIVSYNC (1) Interrupt Control Register (Low) Bit: Reset: R/W: VBIVIR: VBIVSYNC (1) interrupt request flag VBIVID: VBIVSYNC (1) interrupt detect flag VBIVICH: VBIVSYNC (1) Interrupt Control Register (High) Bit: Reset:...
Page 68 Interrupts Interrupt Control Registers VBIVWICL: VBIVSYNC (2) Interrupt Control Register (Low) Bit: Reset: R/W: VBIVWIR: VBIVSYNC (2) interrupt request flag VBIVWID: VBIVSYNC (2) interrupt detect flag VBIVWICH: VBIVSYNC (2) Interrupt Control Register (High) Bit: Reset: R/W: VBIVWIE: VBIVSYNC (2) interrupt enable flag TM3UDICL: Timer 3 Underflow Interrupt Control Register (Low) Bit: Reset:...
Page 69 TM3UDICH: Timer 3 Underflow Interrupt Control Register (High) Bit: Reset: R/W: TM3UDIE: Timer 3 underflow interrupt enable flag OSDGICL: OSD (Graphics) Interrupt Control Register (Low) Bit: Reset: R/W: OSDGIR: OSD (graphics) interrupt request flag OSDGID: OSD (graphics) interrupt detect flag OSDGICH: OSD (Graphics) Interrupt Control Register (High) Bit: Reset:...
Page 70 Interrupts Interrupt Control Registers OSDCICL: OSD (Text) Interrupt Control Register (Low) Bit: Reset: R/W: OSDCIR: OSD (text) interrupt request flag OSDCID: OSD (text) interrupt detect flag OSDCICH: OSD (Text) Interrupt Control Register (High) Bit: Reset: R/W: OSDCIE: OSD (text) interrupt enable flag SCT1ICL: Serial 1 Transmission End Interrupt Control Register (Low) x’00FC98’...
Page 71 SCT1ICH: Serial 1 Transmission End Interrupt Control Register (High) x’00FC99’ Bit: Reset: R/W: SCT1LV[2:0]: Serial 1 transmission end interrupt priority level SCT1IE: Serial 1 transmission end interrupt enable flag SCR1ICL: Serial 1 Reception End Interrupt Control Register (Low) Bit: Reset: R/W: SCT1IR: Serial 1 reception end interrupt request flag SCT1ID: Serial 1 reception end interrupt detect flag...
Page 72 Interrupts Interrupt Control Registers I2CICL: I Bit: Reset: R/W: I2CIR: I I2CID: I I2CICH: I Bit: Reset: R/W: I2CIE: I MN102H75K/F75K/85K/F85K LSI User Manual C Interrupt Control Register (Low) — — — — — I2CICL detects and requests I C interrupts. It is an 8-bit access register. Use the MOVB instruction to access it.
Page 73: Low-Power Modes
Low-Power Modes The MN102H75K/85K provides two ways to reduce power consumption, con- trolling CPU operating and standby modes to cut overall consumption and shutting down unused functions by stopping the system clock supplied to them. 3.1.1 The MN102H75K/85K has two CPU operating modes, NORMAL and SLOW, and two CPU standby modes, HALT and STOP.
Page 74: Exiting From Slow Mode To Normal Mode
Low-Power Modes CPU Modes 3.1.2 The MN102H75K/85K contains a PLL circuit that, in NORMAL mode, mul- tiplies the clock input through the OSC1 and OSC2 pins by 12, divides the signal by 2, then sends the resulting clock to the CPU. (See figure 3-2.) The MCU starts in SLOW mode on power up and on recovery from a reset.
Page 75: Notes On Invoking And Exiting Stop And Halt Modes
3.1.3 When invoking STOP and HALT modes... To reduce power consumption before invoking the STOP or HALT mode, stop current flow from output pins and stabilize the input level of input pins. For output pins, either match the output level to the external level or set the pin to input.
Page 76: Turning Individual Functions On And Off
Low-Power Modes Turning Individual Functions On and Off The MN102H75K/85K allows you to turn each peripheral function on or off through writing to the registers. You can significantly reduce power consumption by turning off unused functions. Table 3-1 shows the register bits controlling on and off for each function block.
Page 77: Cpu Control Register
CPUM: CPU Mode Control Register Bit: Reset: R/W: NWDEN: Watchdog timer reset OSCID: Oscillator select STOP: STOP mode request HALT: HALT mode request OSC[1:0]: Oscillator control Table 3-2 CPU Mode Bit Settings Panasonic Semiconductor Development Company CPU Control Register — —...
Page 78: Timers
Timers 8-Bit Timer Description Timers The MN102H75K/85K contains four 8-bit timers that can serve as interval timers, event timer/counters, clock generators (divide-by-2 output of the underflow), reference clocks for the serial interfaces, or start timers for A/D con- versions. The clock source can be the internal clock (oscillator frequency divided by 2) or the external clock (1/4 or less the oscillator frequency input).
Page 79: 8-Bit Timer Features
Table 4-1 8-Bit Timer Functions and Features Function/Feature Interrupt request flag(s) TM0UDICL register (TM0UDIR bit) Interrupt source(s) Timer 0 underflow Interval timer function Event counter function Clock source for 16-bit timer Timer output function Serial interface transfer clock source A/D conversion trigger function Clock sources TM0I signal Cascade connection...
Page 80: 8-Bit Timer Block Diagrams
Timers 8-Bit Timer Block Diagrams Cascade from timer 0 MN102H75K/F75K/85K/F85K LSI User Manual 8-Bit Timer Block Diagrams Data bus Timer 0 base register TM0BR Load (FE20) Timer 0 binary counter TM0BC TM0MD Count Reset /412 TM0I pin Multiplexer Figure 4-3 Timer 0 Block Diagram Data bus Timer 1 base register TM1BR...
Page 81: Timer 2 Block Diagram
Cascade from timer 1 Cascade from timer 2 Panasonic Semiconductor Development Company Data bus Timer 2 base register TM2BR Load (FE22) Timer 2 binary counter TM2BC TM2MD Count /256 /512 Multiplexer Figure 4-5 Timer 2 Block Diagram Data bus Timer 3 base register TM3BR Load (FE23)
Page 82: 8-Bit Timer Timing
Timers 8-Bit Timer Timing MN102H75K/F75K/85K/F85K LSI User Manual 8-Bit Timer Timing BC value Load value TMnIO input Figure 4-7 Event Timer Input Timing (8-Bit Timers) BC value Load value Interrupt TMnIO input 1 TMnIO output 2 Figure 4-8 Clock Output and Interval Timer Timing (8-Bit Timers) Panasonic Semiconductor Development Company Panasonic Time...
Page 83: 8-Bit Timer Setup Examples
4.5.1 In this example, timer 0 generates an underflow interrupt on the fourth rising edge of the TM0IO signal. The event counter continues to operate during STOP mode. In all modes but STOP, the TMnIO signal input is synchronized to B timer counts TMnIO signal directly.
Page 84: Event Counter Timing (Timer 0)
Timers 8-Bit Timer Setup Examples TM0UDICL (example) Bit: Setting: TM0UDICH (example) Bit: Setting: TM0BR (example) Bit: Setting: Do not change the clock source TM0MD (example) once you select it. Selecting the clock source while you set up Bit: the count operation control will corrupt the value in the binary counter.
Page 85: Setting Up An Interval Timer Using Timers 1 And 2
4.5.2 In this example, timers 1 and 2 are cascaded to divide B generate an underflow interrupt. (24 MHz) TM1MD (example) Bit: Setting: TM2MD (example) Bit: Setting: Panasonic Semiconductor Development Company Setting Up an Interval Timer Using Timers 1 and 2 16-bit timer Timer 1 (Divide by 4)
Page 86 Timers 8-Bit Timer Setup Examples TM2UDICH (example) Bit: Setting: TM2UDICL (example) Bit: Setting: TM1UDICH (example) Bit: Setting: TM1UDICL (example) Bit: Setting: TM1BR (example) Bit: Setting: TM2BR (example) Bit: Setting: Do not change the clock source once you select it. Selecting the clock source while you set up TM1MD (example) the count operation control will...
Page 87: Interval Timer Timing (Timers 1 And 2)
TM2MD (example) Bit: Setting: In the bank and linear address- ing versions of the MN102 series, it was necessary to set TM0EN and TM0LD to 0 between steps 4 and 5, to ensure stable operation. This is unnecessary in the high-speed linear addressing version.
Page 88: 8-Bit Timer Control Registers
Timers 8-Bit Timer Control Registers Table 4-2 shows the registers used to control the 8-bit timers. A binary counter (TMnBC), a time base counter (TMnBR), and a timer mode register (TMnMD) is associated with each 8-bit timer. Table 4-2 8-Bit Timer Control Registers TM0BC–TM3BC: Timer n Binary Counter Bit: Reset:...
Page 89: 16-Bit Timer Description
The MN102H75K/85K contains two 16-bit up/down timers, timers 5 and 6. Associated with each timer are two compare/capture registers that can capture and compare the up/down counter values, generate PWM signals, and generate interrupts. The PWM function has a double buffering mode that causes cycle and transition changes to occur at the beginning of the next clock cycle.
Page 90: 16-Bit Timer Features
Timers 16-Bit Timer Features Table 4-3 16-Bit Timer Functions and Features Interrupt request flag(s) Interrupt sources Clock sources Count direction Interval timer function Event counter function PWM function One-shot pulse output Single-phase capture input Two-phase capture input Two-phase encoding (4x) Two-phase encoding (1x) External count direction control MN102H75K/F75K/85K/F85K LSI User Manual...
Page 91: 16-Bit Timer Block Diagrams
Timer 0 underflow Timer 1 underflow Timer 0 underflow Timer 1 underflow 4.10 16-Bit Timer Timing Panasonic Semiconductor Development Company 16-Bit Timer Block Diagrams TM4IC pin TM4IB pin TM4BC [EN] U/D control LOAD [UD] TM4CA Capture TM4CAX TM4IB pin TM4CB Capture TM4CBX TM4IA pin...
Page 92: Single-Phase Pwm Output Timing With Data Change (16-Bit Timers)
Timers 16-Bit Timer Timing Figure 4-18 Single-Phase PWM Output Timing with Data Change (16-Bit Timers) MN102H75K/F75K/85K/F85K LSI User Manual BC value New value written to CCRB TMnIOA TMnOA BC value TMnOA TMnOB Figure 4-19 Two-Phase PWM Output Timing (16-Bit Timers) BC value TMnIB TMnOA...
Page 93: External Count Direction Control Timing (16-Bit Timers)
TMnIB TMnIA TMnIB Panasonic Semiconductor Development Company BC value Figure 4-21 External Count Direction Control Timing (16-Bit Timers) BC value Figure 4-22 Event Timer Input Timing (16-Bit Timers) BC value FFFF TMnIB TMnIA TMnCA TMnCB Figure 4-23 Single-Phase Capture Input Timing (16-Bit Timers) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Timers...
Page 94: Two-Phase Capture Input Timing (16-Bit Timers)
Timers 16-Bit Timer Timing MN102H75K/F75K/85K/F85K LSI User Manual BC value FFFF TMnIB TMnIA TMnCA TMnCB Figure 4-24 Two-Phase Capture Input Timing (16-Bit Timers) BC value TMnIA TMnIB Figure 4-25 Two-Phase 4x Encoder Timing (16-Bit Timers) BC value TMnIA TMnIB Figure 4-26 Two-Phase 1x Encoder Timing (16-Bit Timers) Panasonic Semiconductor Development Company Panasonic Time...
Page 95: 16-Bit Timer Setup Examples
4.11 16-Bit Timer Setup Examples 4.11.1 Setting Up an Event Counter Using Timer 4 In this example, timer 4 counts the TM4IB input signal (B and generates an interrupt on the second and fifth cycles. To set up timer 4: Use the MOV instruction for this TM4MD (example) setup and only use 16-bit write...
Page 96: Event Counter Timing (Timer 4)
Timers 16-Bit Timer Setup Examples TM4CA (example) Bit: Setting: TM4CB (example) Bit: Setting: To enable timer 4 capture interrupts: Cancel all existing interrupt requests. Next, set the interrupt priority level in the TM4CBLV[2:0] bits of the TM4CBICH register (levels 0 to 6), set the TM4CBIE bit to 1, set the TM4CBIR bit of TM4CBICL to 0, set the TM4CAIE bit of TM4CAICH to 1, and set the TM4CAIR bit of TM4CAICL to 0.
Page 97: Setting Up A Single-Phase Pwm Output Signal Using Timer 4
4.11.2 Setting Up a Single-Phase PWM Output Signal Using In this example, timer 4 is used to divide B single-phase PWM signal. The duty of this signal is 2:3. To accomplish this, the program must load the divide-by ratio of 5 (actual setting: 4) into compare/ capture register A and a cycle count of 2 (actual setting: 1) into compare/capture register B.
Page 98 Timers 16-Bit Timer Setup Examples P2DIR (example) Bit: Setting: To set up timer 4: Use the MOV instruction for this TM4MD (example) setup and only use 16-bit write operations. Bit: This step stops the TM4BC Setting: count and clears both TM4BC and the S-R flip-flop to 0.
Page 99 Timer 4 can output a single-phase PWM signal at any duty. You must select up counting. Timer 4 does not operate in STOP mode, when B an external clock, it must be synchronized to B In this procedure, you set the cycle (x’0001’ to x’FFFE’) in the TM4CA register and the duty in the TM4CB register.
Page 100: Single-Phase Pwm Output Timing (Timer 4)
Timers 16-Bit Timer Setup Examples Figure 4-30 below shows the output waveforms for TM4OA. Both A and B interrupts can occur, but B interrupts can only occur if the TM4CB setting is from 0 to less than TM4CA. This is because when TM4CB matches TM4CB.
Page 101: Single-Phase Pwm Output Timing With Dynamic Duty Changes (Timer 4)
Two potential types of errors are inherent with PWM output. First, because of the circuit configuration, direction errors can occur. The output circuit is configured with T flip-flops, so that even if one transition is missed, the 1s and 0s can reverse direction.
Page 102: Setting Up A Two-Phase Pwm Output Signal Using Timer 4
Timers 16-Bit Timer Setup Examples 4.11.3 Setting Up a Two-Phase PWM Output Signal Using In this example, timer 4 is used to divide timer 0 underflow by 5 and generate a five-cycle, two-phase PWM signal. The phase difference of this signal is 2 cycles.
Page 103 P2DIR (example) Bit: Setting: To set up timer 0: TM0MD (example) Bit: Setting: TM0BR (example) Bit: Setting: Do not change the clock source TM0MD (example) once you select it. Selecting the clock source while you set up Bit: the count operation control will corrupt the value in the binary counter.
Page 104 Timers 16-Bit Timer Setup Examples To set up timer 4: Use the MOV instruction for this TM4MD (example) setup and only use 16-bit write operations. Bit: This step stops the TM4BC Setting: count and clears both TM4BC and the S-R flip-flop to 0. TM4CA (example) Bit: Setting:...
Page 105: Two-Phase Pwm Output Timing (Timer 4)
Timer 4 can output a two-phase PWM signal with any phase difference. You must select up counting. Timer 4 does not operate in STOP mode, when B you use an external clock, it must be synchronized to B In this procedure, you set the cycle (x’0001’ to x’FFFE’) in the TM4CA register and the phase difference in the TM4CB register.
Page 106: Two-Phase Pwm Output Timing With Dynamic Duty Changes (Timer 4)
Timers 16-Bit Timer Setup Examples With PWM output, the duty cycle can change dynamically, which can cause the PWM waveform to skip a pulse (see the single buffering section of figure 4-34 below). To prevent these misses, timers 4 and 5 provide a double-buffer mode. In this mode, no matter what the timing of a TMnCB change, the duty change does not occur until the beginning of the next cycle, and no signals are lost.
Page 107: Setting Up A Single-Phase Capture Input Using Timer 4
4.11.4 Setting Up a Single-Phase Capture Input Using Timer 4 In this example, timer 4 is used to divide B long the TM4IA input signal stays high. An interrupt occurs on capture B and the software calculates the number of cycles by subtracting the contents of TMnCA from the contents of TMnCB.
Page 108: Single-Phase Capture Input Timing (Timer 4)
Timers 16-Bit Timer Setup Examples When TM4MD[1:0] = b’10’ (dur- ing capture), TM4CA and TM4CB become read-only regis- ters. To write to TM4CA or To enable timer 4 capture B interrupts: TM4CB, you must first set Cancel all existing interrupt requests. Next, set the interrupt priority level in the TM4MD[1:0] = b’00’.
Page 109: Setting Up A Two-Phase Capture Input Using Timer 4
4.11.5 Setting Up a Two-Phase Capture Input Using Timer 4 In this example, timer 4 is used to divide the timer 0 underflow by 65,536 and measure the number of cycles from the rising edge of the TM4IA input signal to the rising edge of the TM4IB input signal.
Page 110 Timers 16-Bit Timer Setup Examples TM0BR (example) Bit: Setting: Do not change the clock source TM0MD (example) once you select it. Selecting the clock source while you set up Bit: the count operation control will corrupt the value in the binary counter.
Page 111: Two-Phase Capture Input Timing (Timer 4)
To service the interrupts and calculate the signal width: Ignore the flags when calculat- ing the signal width, even when TM3CA is the larger value. Timer 4 can input a two-phase capture signal. You must select up counting. Timer 4 does not operate in STOP mode, when B must be synchronized to B TM4CA captures the count on the rising edge of TM4IA, and TM4CB captures...
Page 112: Setting Up A 4X Two-Phase Encoder Input Using Timer 5
Timers 16-Bit Timer Setup Examples 4.11.6 Setting Up a 4x Two-Phase Encoder Input Using Timer 5 In this example, timer 5 inputs a 4x two-phase encoded signal that makes it count up and down. An interrupt occurs when the counter reaches a preset value. As figure 4-41 shows, you can set different values for A and B interrupts.
Page 113 To set up timer 5: Use the MOV instruction for this setup and only use 16-bit write operations. TM5MD (example) Bit: This step stops the TM5BC count and clears both TM5BC and the S-R flip-flop to 0. Setting: TM5CA (example) Bit: Setting: TM5CB (example)
Page 114: Count Direction For 4X Two-Phase Encoder Timing Example
Timers 16-Bit Timer Setup Examples To service the interrupts: Run the interrupt service routine. The routine must determine the interrupt group, then clear the interrupt request flag. Timer 5 can input a two-phase encoder signal. Timer 5 does not operate in STOP mode, when B Table 4-4 shows the count direction for the timing diagram in figure 4-42.
Page 115: Setting Up A 1X Two-Phase Encoder Input Using Timer 5
4.11.7 Setting Up a 1x Two-Phase Encoder Input Using Timer 5 In this example, timer 5 inputs a 1x two-phase encoded signal that makes it count up and down. An interrupt occurs when the counter reaches a preset value. As figure 4-45 shows, you can set different values for A and B interrupts. (TM5LP must be 0.) Panasonic Semiconductor Development Company CORE...
Page 116 Timers 16-Bit Timer Setup Examples To set up timer 5: Use the MOV instruction for this setup and only use 16-bit write operations. TM5MD (example) Bit: This step stops the TM5BC count and clears both TM5BC and the S-R flip-flop to 0. Setting: TM5CA (example) Bit:...
Page 117: Count Direction For 1X Two-Phase Encoder Timing Example
To service the interrupts: Run the interrupt service routine. The routine must determine the interrupt group, then clear the interrupt request flag. Timer 5 can input a two-phase encoder signal. Timer 5 does not operate in STOP mode, when B Table 4-5 shows the count direction for the timing diagram in figure 4-46.
Page 118: Setting Up A One-Shot Pulse Output Using Timer 5
Timers 16-Bit Timer Setup Examples 4.11.8 Setting Up a One-Shot Pulse Output Using Timer 5 In this example, timer 5 outputs a one-shot pulse. The pulse width is two clock cycles. To set up the output port: Set the P4MD2 bit of the port 4 output mode register (P4MD) to 1 (selecting the TM5IOA pin) and set the P4DIR2 bit of the port 4 I/O control register (P4DIR) to 1 (selecting output direction).
Page 119 To set up timer 5: Use the MOV instruction for this TM5MD (example) setup and only use 16-bit write operations. Bit: This step stops the TM5BC Setting: count and clears both TM5BC and the S-R flip-flop to 0. TM5CA (example) Bit: Setting: TM5CB (example)
Page 120: One-Shot Pulse Output Timing (Timer 5)
Timers 16-Bit Timer Setup Examples Timer 5 can output a one-shot pulse. Timer 5 does not operate in STOP mode, when B Figure 4-48 shows an example timing diagram for one-shot pulse output. On the falling edge of TM5IB, the TM5EN flag is set, and counting begins at the start of the next cycle.
Page 121: Setting Up An External Count Direction Controller Using Timer 5
4.11.9 Setting Up an External Count Direction Controller In this example, timer 5 counts B direction (up or down). An interrupt occurs when the counter reaches a preset value. Figure 4-49 Block Diagram of External Count Direction Control Using Timer 5 Panasonic Semiconductor Development Company Using Timer 5 /4 and the TM5IA pin controls the count...
Page 122 Timers 16-Bit Timer Setup Examples To set up timer 5: Use the MOV instruction for this setup and only use 16-bit write operations. TM5MD (example) Bit: This step stops the TM5BC count and clears both TM5BC and the S-R flip-flop to 0. Setting: TM5CA (example) Bit:...
Page 123: External Count Direction Control Timing (Timer 5)
To service the interrupts: Run the interrupt service routine. The routine must determine the interrupt group, then clear the interrupt request flag. Either the TM5IA or TM5IB signal can control the timer 5 count direction. The count direction is determined at the opposite edge from the count edge (at the source clock transition occurring in the middle of the count cycle.).
Page 124: Setting Up External Reset Control Using Timer 5
Timers 16-Bit Timer Setup Examples 4.11.10 Setting Up External Reset Control Using Timer 5 In this example, timer 5 is reset by an external signal while counting up. To set up timer 5: Use the MOV instruction to set this data and only use 16-bit write operations.
Page 125: External Reset Control Timing (Timer 5)
TM5CA (example) Bit: Setting: From this point on, whenever the TM5IC signal is high, timer 5 will be reset asynchronously. This is an easy way to synchronize the microcontroller operation with an external event. You can use it to adjust motor speed or to initialize the timers through the hardware.
Page 126: 16-Bit Timer Control Registers
Timers 16-Bit Timer Control Registers 4.12 16-Bit Timer Control Registers Table 4-6 shows the registers used to control the 16-bit timers. A binary counter (TMnBC), a compare/capture register A (TMnCA), a compare/capture register B (TMnCB), and a timer mode register (TMnMD) is associated with each 16-bit timer.
Page 127 TM4MD/TM5MD: Timer n Mode Register Bit: Reset: R/W: TMnEN: TMnBC count TMnNLD: TMnBC, T flip-flop, and S-R flip-flop operation select TMnUD[1:0]: Timer n up/down counter mode select TMnTGE: External trigger enable for start count TMnONE: Counter operating mode select TMnMD[1:0]: TMnCA and TMnCB operating mode select TMnECLR: Timer n BC external clear TMnLP: Timer n BC loop select TMnASEL: TMnIOA output select...
Page 128: Serial Interfaces
Serial Interfaces Description Serial Interfaces The MN102H75K/85K contains two general-purpose serial interfaces with syn- chronous serial, UART, and I serial mode is 12 Mbps. In UART mode, the maximum baud rate is 375,000 bps, when B Table 5-1 Serial Interface Functions and Features Function/Feature Synchronous Serial Mode Parity...
Page 129: Connecting The Serial Interfaces
Figures 5-2, 5-3, and 5-4 illustrate six different methods of connecting the serial interface. 5.3.1 See section 11, “I/O Ports,” for Figure 5-2 shows serial port connections for either simplex or full-duplex syn- details on setting up the SBT chronous serial transfers. port.
Page 130: Uart Mode Baud Rates
Serial Interfaces UART Mode Baud Rates In UART mode, the serial interface transfer clock is set to 16 times the baud rate clock. The expression below is the formula for calculating the baud rate for the UART mode. Table 5-2 shows the baud rate settings when B Table 5-2 Example Baud Rate Settings for the UART Mode 5.5.1 In these timing charts, the character length is 8 bits and there is parity.
Page 131: Uart Mode Timing
(1 when Rx data in) 5.5.2 In these timing charts, the character length is 8 bits, the parity is none, and the stop bit is 2-bit. (1 when Rx data in) Panasonic Semiconductor Development Company b0 b1 b2 b3 b4 b5 b6 b7 PTY RXBUSY Rx interrupt Data read...
Page 132: Serial Interface Setup Examples
Serial Interfaces Serial Interface Setup Examples 5.6.1 This example illustrates serial transmission in the UART mode with the fol- lowing settings: You must use an 8-bit timer to set the transfer clock. See sec- tion 5.6.3, “Setting Up the Serial Interface Clock,”...
Page 133 To set up serial interface 0: SC0CTR (example) Bit: Setting: To enable serial 0 transmission end interrupts: Cancel all existing interrupt requests. Next, set the interrupt priority level of 5 in the ANLV[2:0] bits of the ANICH register, set the SCT0IE bit of SCT0ICH to 1, and set the SCT0IR bit of SCT0ICL to 0.
Page 134: Uart Transmission Timing (Serial Interface 0)
Serial Interfaces Serial Interface Setup Examples Transmission sequence: Figure 5-10 shows an example timing chart. TC0 underflow (1/8) MN102H75K/F75K/85K/F85K LSI User Manual Write the first data byte to SC0TRB. Once this data is in the register, trans- mission begins, synchronized to timer 0. When an interrupt occurs, the program branches to the interrupt service rou- tine.
Page 135: Setting Up Synchronous Serial Reception Using Serial Interface 0
5.6.2 This example illustrates serial reception in the synchronous serial mode with the following settings: When a reception end interrupt occurs, the CPU reads the data byte. To set up the input port: Set the P5DIR7 bit of the port 5 I/O control register (P5DIR) to 0. This sets the SBT0 pin to input.
Page 136: Setting Up The Serial Interface Clock
Serial Interfaces Serial Interface Setup Examples 5.6.3 This example demonstrates how to set up a 19,200 bps transfer clock for the UART interface by using timer 1 to divide B following settings: The serial interface determines the baud rate from the 8-bit underflow. Set up the transfer clock by making the timer 1 underflow either two or eight times the desired baud rate.
Page 137: Serial Interface Clock Timing
Do not change the clock source TM1MD (example) once you select it. Selecting the clock source while you set up Bit: the count operation control will corrupt the value in the binary counter. Setting: In the bank and linear address- ing versions of the MN102 series, it was necessary to set TM1EN and TM1LD to 0...
Page 138: Setting Up I 2 C Transmission Using Serial Interface 0
Serial Interfaces Serial Interface Setup Examples 5.6.4 This example illustrates the microcontroller as a master transmitter in the I mode, using the SBO0 and SBT0 pins. To set up the output ports: C mode requires open-drain Set the P5MD7 and P5MD5 bits of the port 5 output mode register (P5MD) to 1. pins.
Page 139: Master Transmitter Timing In I
Reception must be enabled for the circuit to detect a stop sequence. Figure 5-13 shows an example timing chart. SBO0 output Panasonic Semiconductor Development Company When you perform step 1, the SBT0 output signal goes high. One cycle later, the SBO0 output signal also goes high, signalling the stop sequence. The SC0ISP flag of SC0STR becomes 1.
Page 140: Setting Up I 2 C Reception Using Serial Interface 0
Serial Interfaces Serial Interface Setup Examples 5.6.5 This example illustrates the microcontroller as a master receiver in the I using the SBO0 and SBT0 pins. When initiating master receiver mode, your program must always first transmit a byte of data. The master reception occurs during the interrupt service routine that runs after the data is transmitted.
Page 141: Serial Interface Control Registers
Three registers control each of the serial interfaces: the serial port control register (SCnCTR), the serial transmit/receive buffer (SCnTRB), and the serial port status register (SCnSTR). Table 5-3 Serial Interface Control Registers SC0CTR/SC1CTR: Serial Port n Control Register Bit: Reset: R/W: SCnTEN: Serial port n transmit enable SCnREN: Serial port n receive enable...
Page 142 Serial Interfaces Serial Interface Control Registers SCnICM: Serial port n I SCnLN: Serial port n character length SCnPTY[2:0]: Serial port n parity bit select SCnSB: Serial port n stop bit select (UART mode only) SCnS[1:0]: Serial port n clock source select SC0TRB/SC1TRB: Serial Port n Transmit/Receive Buffer Bit: Reset:...
Page 143 SC0STR/SC1STR: Serial Port n Status Register Bit: Reset: R/W: SCnTBY: Serial port n transmission busy flag SCnRBY: Serial port n reception busy flag SCnISP: Serial port n I SCnRXA: Serial port n received data flag SCnIST: Serial port n I SCnFE: Serial port n framing error SCnPE: Serial port n parity error SCnOE: Serial port n overrun error...
Page 144: Analog-To-Digital Converter
Analog-to-Digital Converter Description Analog-to-Digital Converter The MN102H75K/85K contains an 8-bit charge redistribution A/D converter (ADC) that can process up to 12 channels. The reference clock is selectable to Table 6-1 ADC Functions and Features Function/Feature Sample and hold Embedded Conversion time 4 µs per channel (when B Clock sources Programmable to B...
Page 145: Block Diagram
ADIN10 ADIN11 6.4.1 Calculate the A/D conversion time as follows: For example, if you set the clock source to B Reference Panasonic Semiconductor Development Company Block Diagram ADIN0 ADIN1 ADIN2 128 64 ADIN3 ADIN4 ADIN5 ADIN6 ADIN7 ADIN8 ADIN9 Storage of converted data Shift register for state information ANNCH AN1CH...
Page 146: Single Channel/Single Conversion Timing
Analog-to-Digital Converter A/D Conversion Timing 6.4.2 When ANMD[1:0] = b’00’, the ADC converts one ADIN input signal a single time. An interrupt occurs when the conversion ends. Load the number of the channel to be converted to the AN1CH[3:0] field of the ADC control register (ANCTR).
Page 147: Single Channel/Continuous Conversion Timing
6.4.4 When ANMD[1:0] = b’10’, the ADC converts one ADIN input signal contin- uously. An interrupt occurs each time the conversion ends. Load the number of the channel to be converted in the AN1CH[3:0] field of the ADC control register (ANCTR).
Page 148: Adc Setup Examples
Analog-to-Digital Converter ADC Setup Examples 6.5.1 This example illustrates single-channel conversion controlled by the software. The ADIN6 pin inputs an analog voltage signal (0.0 V–3.3 V) and the ADC converts it to 8-bit digital values. To set up the input port: Set the P1MD2 bit of the port 1 output mode register (P1MD) to 1.
Page 149: Setting Up Hardware-Controlled Intermittent Three-Channel A/D Conversion
AN6BUF (example) Bit: Reference 6.5.2 This example illustrates multiple-channel conversion controlled by the hardware. The ADIN2, ADIN1, and ADIN0 pins input analog voltage signals ( 0.0 V– 3.3 V) and the ADC converts the voltages to 8-bit digital values. It writes the results to the registers periodically, each time timer 1 underflows.
Page 150 Analog-to-Digital Converter ADC Setup Examples To set up the input port: Set the P0DIR[5:3] bits of the port 0 I/O control register (P0DIR) to 0. This sets the ADIN2 (P05), ADIN1 (P04), and ADIN0 (P03) pins (P11) to general-purpose input. To set up the ADC: Set the operating conditions in the ADC control register (ANCTR).
Page 151: Adc Control Registers
Conversion The ADC contains thirteen registers—one control register (ANCTR) and twelve data buffers (each associated with one of the ADIN pins). ANCTR controls the operating conditions, and the read-only data buffers hold the results of the A/D conversions. Table 6-2 ADC Control Registers AN0BUF–AN11BUF: ADIN0–ADIN11 Conversion Data Buffers x’00FF00’–x’00FF1C’...
Page 152 Analog-to-Digital Converter ADC Control Registers ANCTR: ADC Control Register Bit: NCH3 Reset: R/W: ANNCH[3:0]: Channel select for multiple-channel conversion AN1CH[3:0]: Channel select for single-channel conversion ANEN: Conversion start/busy flag ANTC: Conversion start at timer 1 underflow ANCTR5 ANCK[1:0]: Clock source select ANMD[1:0]: Operating mode select MN102H75K/F75K/85K/F85K LSI User Manual NCH2...
Page 153: Caution About Analog-To-Digital Converter
The type of this Analog-to-Digital Converter is a sample-hold one, and so the current temporarily flows in conversion to charge the condenser of the sample- hold circuit. For this reasons, the following settings are needed to get the accurancy of convension: Panasonic Semiconductor Development Company Cautions about Analog-to-Digital Converter Cautions about Analog-to-Digital Converter...
Page 154: On-Screen Display
On-Screen Display Description On-Screen Display The MN102H75K/85K contains an on-screen display (OSD) function composed of three layers: a text layer, a graphics layer, and a cursor layer. You can control each layer individually, which gives you great freedom in positioning displays. If you use the OSD function, the DMA function executes for both You can also modify the ROM space that contains the text characters and the...
Page 155: Block Diagram
On-Screen Display Block Diagram Block Diagram select Clock switch Polarity Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual Panasonic...
Page 156: Power-Saving Considerations In The Osd Block
On-Screen Display Power-Saving Considerations in the OSD Block Table 7-2 shows bits that can decrease the power consumption of the OSD block. This section explains how to use these bits. Table 7-2 Power-Saving Control Bits for the OSD OSDPOFF resets to 0. To operate the OSD, you must first set this bit to 1.
Page 157: Osd Operation
This section describes the basic operation of the OSD block. The remainder of section 7 provides more detailed specifications. 7.5.1 The OSD clock source is programmable to either the microcontroller system clock (OSC1, OSC2 pins) or a dedicated OSD clock (OSDXI, OSDXO pins). OSC clock source See section 7.11, “Selecting the An internal phase-locked loop (PLL) multiplies the external 4-MHz frequency to...
Page 158: Output Pin Setup
On-Screen Display OSD Operation Graphics layer The graphics layer contains tiled images. In the 16-color mode, each 4-bit dot on a tile can display one of 16 colors. Each tile can use either of two available color palettes, allowing a total of 32 colors in one display. The graphics layer also supports 2-, 4-, and 8-color modes.
Page 159: Conditions For Vram Writes
7.5.7 Text layer Set CHP , CVP , GHP, and GVP for every line in the VRAM. If you do not, a software processing error may occur. Graphics layer Panasonic Semiconductor Development Company Conditions for VRAM Writes The lead data for each line must be the color control code (COL) or the char- acter code (CC).
Page 160: Standard And Extended Display Modes
On-Screen Display Standard and Extended Display Modes Two modes are available for the graphics and cursor layers, standard and extended. In extended mode, the cursor layer can display four grouped graphic tiles rather than one. The graphics layer can display tiles that are two pixels taller than those used in standard mode, giving the graphic tiles the same dimensions as the characters in the text layer.
Page 161: Graphics Layer Display Modes
Table 7-4 Associated Tiles for Cursor Tile Code Registers In standard mode, STC0 is the only cursor tile code register that is enabled. Use the cursor horizontal position register (SHP, x’00F12’) and the cursor vertical position register (SVP, x’007F14’) in both modes to program the display start position.
Page 162: Display Setup Examples
On-Screen Display Display Setup Examples 7.7.1 This section shows how to set up the graphics display data in the VRAM. Register settings RAMEND (x’007F04’) = x’80FF’ (Graphics RAM end address: x’980F’) GIHP (x’007F16’) = x’0822’ GIVP (x’007F18’) = x’1803’ OSD2 (x’007F08’) = x’0047’ Table 7-5 Example Graphics VRAM Settings Line No.
Page 163: Graphics Display Example
HP = x'22' VP = x'40' Line 2 HSZ = 0 (1x) HP = x'4' Palette 1 Palette 1 Palette 1 Palette 1 VSZ = 0 (1x) VP = x'58' Line 3 HP = x'10' GTC = x'181' Palette 1 VSZ = 1 (2x) Panasonic Semiconductor Development Company...
Page 164: Setting Up The Text Layer
On-Screen Display Display Setup Examples 7.7.2 This section shows how to set up the text display data in the VRAM. Register settings RAMEND (x’007F04’) = x’80FF’ (Text RAM end address: x’9FFF’) CIHP (x’007F1A’) = x’1020’ CIVP (x’007F1C’) = x’1803’ OSD3 (x’007F0A’) = x’0000’ Table 7-6 Example Text VRAM Settings Line No.
Page 165: Text Display Example
The text display starts one dot to the right of the HP setting. HP = x'20' VP = x'40' Line 2 HSZ=0 (1x) CC=006 CC=007 CC=007 CC=007 HP = x'4' Box shad.1 Box shad.1 Box shad.1 Same as Char. shad Char.
Page 166: Vram
On-Screen Display VRAM 7.8.1 Table 7-7 VRAM Bit Allocation in Internal RAM Text layer Character code ID code COL (normal mode) Color control code ID code COL (closed-caption mode) Color control code ID code Repeat character/blank code ID code Character H position control ID code CLAST CVSZ1 CVSZ0 Character V position control...
Page 167 BLINK BCOL[3:0] CCOL[3:0] COL: Color Control Code (Closed-Caption Mode) CUNDL ITALIC FRAME BLINK BCOL[3:0] CCOL[3:0] CCB: Repeat Blank/Character Code CCBF CCB[3:0] Panasonic Semiconductor Development Company Specifies character blinking. 0: Disable 1: Enable Specifies the background color (1 of 16 colors). Specifies the foreground (character) color (1 of 16 colors).
Page 168 On-Screen Display VRAM CHP: Character Horizontal Position Control Code CHSZ[1:0] CSHT CHP[9:0] CVP: Character Vertical Position Control Code CLAST CVSZ[1:0] In closed-caption mode, only the b’00’, b’01’, and b’11’ settings are available for CVSZ[1:0]. The b’10’ setting is reserved. CINT CVP[9:0] Graphics Layer GTC: Graphic Tile Code...
Page 169 GCB[3:0] GPRT GTC[8:0] GHP: Graphics Horizontal Position Control Code GHSZ[1:0] GSHT GHP[9:0] GVP: Graphics Vertical Position Control Code GLAST GVSZ[1:0] GINT GVP[9:0] Panasonic Semiconductor Development Company Specifies the number of times (up to 16) a blank or graphic tile is repeated. Specifies graphics color palette 1 or 2.
Page 170: Vram Organization
On-Screen Display VRAM 7.8.2 GRAMEND 40 N 5 GRAMEND 40 (N 1) x'008000' Program Data GRAMEND 40 n 5 GRAMEND 40 (n 1) Stack Area GRAMEND 40 N 5 Graphics VRAM GRAMEND CRAMEND 50 M 1 CRAMEND 50 M 1 Text CRAMEND 50 (M 1) VRAM...
Page 171: Graphics Vram Organization For Two Modes
GRAMEND 40 N 5 Line N data GRAMEND 40 (N 1) GRAMEND 40 n 5 Line n data GRAMEND 40 (n 1) GRAMEND 7B Line 2 data GRAMEND 40 GRAMEND 3B Line 1 data GRAMEND GRAMEND 28 N 1 Line N data GRAMEND 28 (N 1) GRAMEND 28 n 1 Line n data...
Page 172: Cautions About The Number Of Display Code Set To Vram
On-Screen Display VRAM 7.8.3 When the display lines are adjoined or overlapped, and the number of the above display code is extremely fewer than that of the below one, first line of the display line may not be output correctly. In OSD circuit, font data to display are read from ROM and stored to the buffer.
Page 173: Rom
7.9.1 x’080000’ CROMEND 24 (M 1) 1 CROMEND 24 M Program CROMEND 24 (m 1) 1 Data CROMEND 24 m Area CROMEND 47 CROMEND 24 CROMEND 23 CROMEND 24 (M 1) 1 Text CROMEND GROMEND 80 (N 1) 1 Graphics GROMEND 80 (N 1) 1 GROMEND 80 N GROMEND...
Page 174: Graphics Rom Organization In Different Color Modes
On-Screen Display 7.9.2 The graphics layer supports up to sixteen colors, in the 16-color mode, but also supports 2-, 4-, and 8-color modes. The smaller the number of colors, the less ROM area required per tile. The figures in this section illustrate the ROM organi- zation for each color mode.
Page 175: Graphics Rom In The Four Color Modes (16W X 16H Tiles)
Required bytes Panasonic Semiconductor Development Company Graphic Tile Codes 2 colors 4 colors ROMEND 80 N 1 ROMEND 180 ROMEND 160 ROMEND 140 ROMEND 120 ROMEND 100 ROMEND E0 ROMEND C0 ROMEND A0 ROMEND 80 ROMEND 60 ROMEND 40 ROMEND 20 ROMEND 32 bytes 64 bytes...
Page 176: Graphics Rom In The Four Color Modes (16W X 18H Tiles)
On-Screen Display Required bytes MN102H75K/F75K/85K/F85K LSI User Manual Graphic Tile Codes 2 colors 4 colors ROMEND 90 N 1 ROMEND 1B0 ROMEND 18C ROMEND 168 ROMEND 144 ROMEND 120 ROMEND FC ROMEND D8 ROMEND B4 ROMEND 90 ROMEND 6C ROMEND 48 ROMEND 24 ROMEND 72 bytes...
Page 177: Graphics Rom Organization In 16-Color Mode (16W X 16H Tiles)
Figure 7-13 Graphics ROM Organization in 16-Color Mode (16W x 16H Tiles) Panasonic Semiconductor Development Company ROMEND 7F Line 1 data ROMEND 78 ROMEND 77 Line 2 data ROMEND 70 ROMEND 6F Line 3 data ROMEND 68 Sheet 1 bits 7 to 0 ROMEND 7 ROMEND 67 Sheet 1 bits 15 to 8...
Page 178: Graphics Rom Organization In 16-Color Mode (16W X 18H Tiles)
On-Screen Display Figure 7-17 Graphics ROM Organization in 16-Color Mode (16W x 18H Tiles) MN102H75K/F75K/85K/F85K LSI User Manual ROMEND 8F Line 1 data ROMEND 88 ROMEND 87 Line 2 data ROMEND 80 ROMEND 7F Line 3 data ROMEND 78 Sheet 1 bits 7 to 0 ROMEND 7 ROMEND 77 Sheet 1 bits 15 to 8...
Page 179: Setting Up The Osd
7.10 Setting Up the OSD 7.10.1 Setting Up the OSD Display Colors This section describes how to set up the display colors for the OSD. To set up the color palettes: Write your settings to the color palette registers shown in table 7-8. Table 7-8 Color Palette Registers To set up the cursor display colors: Write to the fields described below.
Page 180 On-Screen Display Setting Up the OSD To set up the text display colors: Write to the fields described below. To set up functions applying to all layers: Write to the fields described below. Color background function The color background function allows you to fill the television screen areas that are uncovered by the OSD display (text, graphics, or cursor layers) with any color.
Page 181 Translucency The TRPTF bit allows you to make the color 15 translucent in all the palettes (CPTF, GPT1F, and GPT2F). RGB and YS are output at low levels for that color, and YM is output at the level specified for the palette. This dims the color on the display. See figure 7-21.
Page 182: Rgb, Ym, And Ys Output Control Settings
On-Screen Display Setting Up the OSD Table 7-9 RGB, YM, and YS Output Control Settings YSPLT PRYM TPRT TRPTF Color palette 0 output low Color palette F output low Color palette 0 output low Color palette F output low MN102H75K/F75K/85K/F85K LSI User Manual Color palettes 0 and F Color palettes 0 and F output low...
Page 183: Osd Signal Waveform
Panasonic Semiconductor Development Company Graphics layer Color palette 2 (YM3 = 0, YM2 = 0, YM1 = 0, YM0 = 0) Color palette 0 (YM3 = 0, YM2 = 0, YM1 = 0, YM0 = 1) Color palette 1 (YM3 = 1, YM2 = 0, YM1 = 0, YM0 = 1) RGB, YM, and YS signals are displayed at this line.
Page 184: Osd Signal Output Switches
On-Screen Display Setting Up the OSD Figure 7-22 OSD Signal Output Switches MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company Panasonic...
Page 185: Text Layer Functions
7.10.2 Text Layer Functions This section describes the character enhancement functions available in the text layer. Outlining In both normal and closed-caption modes, writing a 1 to bit 9 (FRAME) of the COL setting in the VRAM causes an outline to appear around all characters fol- lowing that COL.
Page 186: Box Shadowing Example
On-Screen Display Setting Up the OSD Box shadowing In normal mode, writing a 1 to bit 12 (BSHAD1) of the COL setting in the VRAM causes a box shadow to appear around all characters following that COL. If COL bit 11 (BSHAD0) is 0, the color specified in the WBSHD register (x’007FA6’) appears on the top and left sides of the box and the color specified in the BBSHD register (x’007FA4’) appears on the bottom and right sides of the box.
Page 187: Italicizing And Underlining Example
On-Screen Display Setting Up the OSD Italicizing In closed-caption mode, writing a 1 to bit 10 (ITALIC) of the COL setting in the VRAM italicizes all characters following that COL. Figure 7-26 shows an example of an italicized character. Underlining In closed-caption mode, writing a 1 to bit 11 (CUNDL) of the COL setting in the VRAM underlines all characters following that COL.
Page 188: Display Sizes
On-Screen Display Setting Up the OSD 7.10.3 Display Sizes Graphic tile sizes b'00' b'01' b'00' b'01' b'10' b'11' GVSZ[1:0] The settings shown are for interlaced displays. In progressive displays, the vertical size settings (GVSZ[1:0]) are as follows: 01 = 1x, 10 = 2x, and 11 = 3x. The 00 setting is reserved. Figure 7-27 Graphic Tile Size Combinations MN102H75K/F75K/85K/F85K LSI User Manual b'10'...
Page 189: Character Size Combinations
Character sizes b'00' b'01' b'00' b'01' b'10' b'11' CVSZ[1:0] The settings shown are for interlaced displays. In progressive displays, the vertical size settings (CVSZ[1:0]) are as follows: 01 = 1x, 10 = 2x, and 11 = 3x. The 00 setting is reserved. In addition, in closed-caption mode, only the b’00’, b’01’, and b’11’ settings are available for CVSZ[1:0].
Page 190: Setting Up The Osd Display Position
On-Screen Display Setting Up the OSD 7.10.4 Setting Up the OSD Display Position This section describes how to control the positioning of the OSD. To set up the horizontal position: Cursor Graphics Text To set up HP of characters in the line including repeated characters and blank spaces, T the dot clock cycle, and H there is at least 0.8 µs between the end of a line and the leading edge of HSYNC.
Page 191 To set up the vertical position: Cursor Graphics When you write new values to the GIVP and CIVP fields, the settings take effect on the next VSYNC pulse. This means that changes are reflected in the next display screen rather than the current one.
Page 192: Dma And Interrupt Timing
On-Screen Display DMA and Interrupt Timing 7.11 DMA and Interrupt Timing This section describes how the MN102H75K/85K handles the timing of direct memory access (DMA) transfers of OSD data and OSD interrupts. On both the text and graphics layers, the microcontroller reads the line 1 data from the RAM as it scans line 1 onto the display.
Page 193: Dma And Interrupt Timing For The Osd
12Ts 4nTs Scan line 1 Text DMA Text interrupt Graphics interrupt Graphics interrupt Line G1 Graphics DMA Line C1 Text DMA Text interrupt Line C2 Line G2 Figure 7-30 DMA and Interrupt Timing for the OSD Panasonic Semiconductor Development Company Television Screen 4nTs Graphics DMA...
Page 194: Selecting The Osd Dot Clock
On-Screen Display Selecting the OSD Dot Clock 7.12 Selecting the OSD Dot Clock This section describes how to set up the OSD dot clock. Selecting the clock source The source for the OSD dot clock is programmable to either the 4-MHz clock supplied through the OSC1 and OSC2 pins, then multiplied by the PLL circuit to 48 MHz, or a dedicated clock supplied through the OSDXI and OSDXO pins.
Page 195: Controlling The Shuttering Effect
7.13 Controlling the Shuttering Effect The MN102H75K/85K OSD achieves a shuttering effect using four pro- grammable shutters—two vertical and two horizontal. With this feature, you can shutter any portion of the OSD display, or you can combine shuttering with a wipe-out effect to create a smooth appearing and disappearing effect.
Page 196: Shuttered Area Setup Examples
On-Screen Display Controlling the Shuttering Effect MN102H75K/F75K/85K/F85K LSI User Manual HSHT0 HSHT1 VSON0 = VSON1 = 1: V shutters 0 and 1 on HSON0 = HSON1 = 1: H shutters 0 and 1 on VSP0 = 0: V shutter 0 shutters below VSHT0 VSP1 = 1: V shutter 1 shutters above HSP0 = 0: H shutter 0 shutters to the right...
Page 197: Controlling Shutter Movement
7.13.2 Controlling Shutter Movement Enabling the shutter movement function in the registers allows the shuttered area to expand or contract over time, producing a wipe-in or wipe-out effect. This allows the OSD display to appear or disappear without an abrupt transition. Table 7-13 shows the register settings required for this function, and figure 7-32 shows four setup examples.
Page 198: Shutter Movement Setup Examples
On-Screen Display Controlling the Shuttering Effect This example shows V shutter 0 moving downward. It shutters both the text and the background color in the text layer. MN102H75K/F75K/85K/F85K LSI User Manual HSHT0 HSHT1 VSON0 = VSON1 = 1: V shutters 0 and 1 on HSON0 = HSON1 = 1: H shutters 0 and 1 on VSP0 = 1: V shutter 0 shutters above VSHT0...
Page 199: Controlling Shuttering Effects
7.13.3 Controlling Shuttering Effects Through register settings, you can independently control shuttering for text, text background, graphics, and color background. You can also output blanks to the shuttered area. You cannot shutter the cursor layer. Table 7-13 shows the register settings required for these effects. There are three types of shuttering—shuttering of text, text background, and graphics, shuttering of the color background, and shutter blanking.
Page 200: Text-Layer Shuttering Setup Examples
On-Screen Display Controlling the Shuttering Effect To shutter the color background: Set the color background shutter control bit, COLBSHT, of the shutter control register, SHTC (x’007F28’) to 1. This function exists only when the program enables a color background. It allows you to limit the area covered by the color background.
Page 201: Controlling Line Shuttering
7.13.4 Controlling Line Shuttering It is possible to cancel shuttering of individual lines on the text and graphics layers so that they will be displayed on both shuttered and non-shuttered regions. To disable shuttering on the next line: Set the GSHT bit (bit 10 of GHP in the RAM data) and/or the CSHT bit (bit 10 of CHP in the RAM data) to 1.
Page 202: Field Detection Circuit
On-Screen Display Field Detection Circuit 7.14 Field Detection Circuit 7.14.1 Block Diagram System clock VSYNC leading edge detection 7.14.2 Description The 7-bit field counter in this block resets every HSYNC interval to count the system clock. At each VSYNC interval, the 4 MSBs of the 7-bit counter are alter- nately loaded (made readable) to bits 7 to 4 (N2) and 3 to 0 (N1) of the EVOD register (x’007F0E’).
Page 203: Considerations For Interlaced Displays
Table 7-15 EOMON Output Criteria 7.14.3 Considerations for Interlaced Displays Switching the display start field The OSD is constructed so the display start position is the field (field 1) where the EOMON bit is 1. However, interlaced displays may require that the start position be a field (field 2) where the EOMON bit is 0.
Page 204: Osd Registers
On-Screen Display OSD Registers 7.15 OSD Registers All registers in OSD block cannot be written by byte (by word only). Read by byte is possible. CROMEND: Text ROM End Address Register Bit: Reset: R/W: GROMEND: Graphics ROM End Address Register Bit: Reset: R/W:...
Page 205 STC0: Cursor Tile Code Register 0 Bit: Reset: R/W: SPRT0: Cursor 0 color palette select STC0[8:0]: Cursor 0 Tile Code STC1: Cursor Tile Code Register 1 Bit: Reset: R/W: SPRT1: Cursor 1 color palette select STC1[8:0]: Cursor 1 Tile Code STC2: Cursor Tile Code Register 2 Bit: Reset:...
Page 206: Cursor Vertical Size Settings
On-Screen Display OSD Registers STC3: Cursor Tile Code Register 3 Bit: Reset: R/W: SPRT3: Cursor 3 color palette select STC3[8:0]: Cursor 3 Tile Code SHP: Cursor Horizontal Position Register Bit: Reset: R/W: SHSZ[1:0]: Cursor horizontal size SHP[9:0]: Cursor horizontal position SVP: Cursor Vertical Position Register Bit: Reset:...
Page 207: Graphics Vertical Size Settings
GISHT: Graphics initial shutter control GIHP[9:0]: Graphics initial horizontal position GIVP: Graphics Initial Vertical Position Register Bit: Reset: R/W: GIVSZ[1:0]: Graphics initial vertical size Table 7-17 Graphics Vertical Size Settings GIVP[9:0]: Graphics initial vertical position CIHP: Text Initial Horizontal Position Register Bit: Reset: R/W:...
Page 208: Text Vertical Size Settings
On-Screen Display OSD Registers CIVSZ[1:0]: Text initial vertical size Table 7-18 Text Vertical Size Settings CIVP[9:0]: Text initial vertical position EVOD: Display Start Field Control Register Bit: Reset: R/W: EOSEL: Even/odd field select FRMON: Field register monitor EOMON: Even/odd field monitor FREG[23:20]: Field register FREG[13:10]: Field register HCOUNT: HSYNC count...
Page 209 OSD1: OSD Register 1 Bit: Reset: R/W: OSCSEL[1:0]: Oscillator select A write to the OSD bit of OSD1 takes effect on the next leading edge of VSYNC. If you are turning the OSD on, the OSD starts operating on the next VSYNC after the program writes XIO: OSDX frequency select a 1 to the OSD bit.
Page 210 On-Screen Display OSD Registers OSD2: OSD Register 2 Bit: Reset: R/W: SPEXT: Cursor extended mode select GTHT: Graphic tile height select GEXTE: Graphics maximum tiles per line select PRYM: Translucent color control (YM, YS) TRPTF: Translucency control (all layers) Setting the YSPLT bit of OSD1 to 1 disables the PRYM bit.
Page 211 OSD3: OSD Register 3 Bit: Reset: R/W: BLINK: CANH: Vertical position control for closed captions EONL and BFLD: Closed-caption scrolling control UNDF: Underline blinking control CAPM: Closed-caption mode setting VSHT0: Vertical Shutter 0 Register Bit: Reset: R/W: VSON0: Vertical shutter 0 on/off VSP0: Vertical shutter 0 shuttering direction VSMP0: Vertical shutter 0 movement direction VSM0: Vertical shutter 0 movement control...
Page 212 On-Screen Display OSD Registers VSHT1: Vertical Shutter 1 Register Bit: Reset: R/W: VSON1: Vertical shutter 1 on/off VSP1: Vertical shutter 1 shuttering direction VSMP1: Vertical shutter 1 movement direction VSM1: Vertical shutter 1 movement control VST1[9:0]: Vertical shutter 1 position HSHT0: Horizontal Shutter 0 Register Bit: Reset:...
Page 213 HSHT1: Horizontal Shutter 1 Register Bit: Reset: R/W: HSON: Horizontal shutter 1 on/off HSP1: Horizontal shutter 1 shuttering direction HSMP1: Horizontal shutter 1 movement direction HSM1: Horizontal shutter 1 movement control HST1[9:0]: Horizontal shutter 1 position SHTC: Shutter Control Register Bit: The shuttering function does not Reset:...
Page 214 On-Screen Display OSD Registers CPT0–CPTF: Text Palette Colors 0–15 Registers Bit: Reset: R/W: CPTnYM[3:0]: YM color code CPTnB[3:0]: Blue color code CPTnG[3:0]: Green color code CPTnR[3:0]: Red color code COLB: Color Background Register Bit: COLB Reset: R/W: COLBYM[3:0]: YM color code COLBB[3:0]: Blue color code COLBG[3:0]: Green color code COLBR[3:0]: Red color code...
Page 215 BBSHD: Black Box Shadowing Register Bit: Reset: R/W: BBSHDYM[3:0]: YM color code BBSHDB[3:0]: Blue color code BBSHDG[3:0]: Green color code BBSHDR[3:0]: Red color code WBSHD: White Box Shadowing Register Bit: Reset: R/W: WBSHDYM[3:0]: YM color code WBSHDB[3:0]: Blue color code WBSHDG[3:0]: Green color code WBSHDR[3:0]: Red color code GPT10–GPT1F: Graphics Palette 1 Colors 0–15 Registers x’007FC0’–x’007FDE’...
Page 216 On-Screen Display OSD Registers GPT20–GPT2F: Graphics Palette 2 Colors 0–15 Registers x’007FE0’–x’007FFE’ Bit: GPT2n Reset: R/W: GPT2nYM[3:0]: YM color code GPT2nB[3:0]: Blue color code GPT2nG[3:0]: Green color code GPT2nR[3:0]: Red color code MN102H75K/F75K/85K/F85K LSI User Manual GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n GPT2n...
Page 217: Ir Remote Signal Receiver
IR Remote Signal Receiver The MN102H75K/85K contains a remote signal receiver that processes signals in two formats: Household Electrical Appliance Manufacturers Association (HEAMA) format and 5-/6-bit format. This chapter provides an overview of each block in the circuit and describes the operation of the receiver. fSYSCLK = 12 MHz in all of the The remote signal is input through the RMIN pin.
Page 218: Mn102H75K/F75K/85K/F85K Lsi User Manual Panasonic Semiconductor Development Company
IR Remote Signal Receiver Block Diagram Block Diagram x’007EA6’ RMCS: MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company Panasonic...
Page 219: Ir Remote Signal Receiver Operation
8.3.1 The IR remote signal receiver has three operating modes: HEAMA, 5-/6-bit, and HEAMA–5-/6-bit automatic detect. Set the mode in the MODAUTO and MODSEL bits of the interrupt control register, RMIR. The FMTMON bit of the interrupt status register, RMIS, monitors the operating mode. In automatic detect mode, the microcontroller checks the interval between remote signal edges.
Page 220: 8-Bit Data Reception
IR Remote Signal Receiver IR Remote Signal Receiver Operation 8.3.3 Resetting the 8-bit data reception counter allows the microcontroller to receive 8- bit data, either with or without a leader. The software can reset the counter using the BCRSTE and BCEDGS bits of the interrupt status register, RMIS. The counter can also be reset by an external reset or a hardware reset at leader detection.
Page 221: Identifying The Data Format
8.3.4 The microcontroller determines the logic levels of the data by testing the interval between remote signal edges. Table 8-1 shows the intervals that the microcon- troller interprets as 0 and 1 for both HEAMA and 5-/6-bit formats. Table 8-2 shows the conditions for identifying long and short data.
Page 222: Generating Interrupts
IR Remote Signal Receiver IR Remote Signal Receiver Operation 8.3.5 The IR remote signal receiver has four interrupt vectors: leader detection, trailer detection, 8-bit data reception detection, and pin edge detection. This section describes the operation for each of them. 8.3.5.1 Leader Detection An interrupt occurs when the circuit detects a data leader.
Page 223: Controlling The Slow Mode
8.3.6 Use bit 7 (SP) in the RMLD reg- The MN102H series microcontrollers have two operating modes: NORMAL and ister to toggle the noise filter SLOW. (See section 3.1, “CPU Modes,” on page 72.) In SLOW mode, f sampling frequency between = 2 MHz, which affects the frequencies of the PWM3 clock and noise filter PWM6/PWM8 and PWM3/ sampling (PWM6/PWM8).
Page 224: Ir Remote Signal Receiver Control Registers
IR Remote Signal Receiver IR Remote Signal Receiver Control Registers All registers in RMC block cannot be written by byte (by word only). Read by byte is possible. Table 8-5 IR Remote Signal Receiver Registers RMTC: Remote Signal Frequency Division Control Register Bit: RMTC7 RMTC6 RMTC5 RMTC4 RMTC3 RMTC2 RMTC1 RMTC0 Reset:...
Page 225 All registers in RMC block cannot be written by byte (by word only). Read by byte is possible. RMIR: Remote Signal Interrupt Control Register Bit: Reset: R/W: MODAUTO: Automatic operating mode detection on/off MODSEL: Operating mode select FILTRE: Noise filter input multiplexer on/off POLSEL: Input polarity LEADERE: Interrupt enable for leader detection TRAILRE: Interrupt enable for trailer detection...
Page 226 IR Remote Signal Receiver IR Remote Signal Receiver Control Registers RMIS: Remote Signal Interrupt Status Register Bit: Reset: R/W: BCRSTE: 8-bit data reception binary counter reset enable BCEDGS: 8-bit data reception binary counter reset edge select FMTMON: Format monitor DOMESD: Interrupt request on HEAMA leader detection M56BITD: Interrupt request on 5-/6-bit leader detection TRAILRD: Interrupt request on trailer detection DAT8D: Interrupt request on 8-bit reception detection...
Page 227 RMLD: Remote Signal Leader Value Set Register Bit: Reset: R/W: SP and SPSLW: Switch clock frequencies fPWM1 = fSYSCLK/23, fPWM3 = fSYSCLK/25, fPWM5 = fSYSCLK/27, LD[3:0]: HEAMA data leader value fPWM6 = fSYSCLK/28, and fPWM8 = fSYSCLK/210. RMCS: Remote Signal Clock Status Register Bit: Do not set the leader value too small.
Page 228: Closed-Caption Decoder
Closed-Caption Decoder Description Closed-Caption Decoder The MN102H75K/85K contains two identical closed-caption decoder circuits, CCD0 and CCD1. The decoders extract encoded captions from composite video signals. Figure 9-1 provides a block diagram of the decoders, and section 9.3, “Functional Description,” on page 228, describes the circuit’s main blocks: the analog-to-digital converter, clamping circuit, sync separator circuit, data slicer, controller, and sampling circuit.
Page 229: Functional Description
9.3.1 The analog-to-digital converter (ADC) converts the clamped video signal to 8-bit digital data using a 12-MHz sampling clock. Figure 9-2 shows an example con- figuration using the recommended external pin connections. In this example, both caption decoders are used. Figure 9-3 shows the recommended connection when The constants shown in figures 9-2 neither decoder is used, and figure 9-4 shows that when only CCD0 is used.
Page 230: Clamping Circuit
Closed-Caption Decoder Functional Description Table 9-2 Caption decoder register setting Use two cap- caption 0 ON(PCNT0.bp0=0) tion decoders caption 1 ON(PCNT0.bp1=0) Use one cap- caption 0 ON(PCNT0.bp0=0) tion decoder no caption 1 OFF(PCNT0.bp1=1) No use caption no caption 0 OFF(PCNT0.bp0=1) decoder no caption 1 OFF(PCNT0.bp1=1)
Page 231: Sync Separator Circuit
Table 9-4 Current Level Control Table 9-5 provides the registers used to control and monitor the clamping circuit. See the page number indicated for register and bit descriptions. Table 9-5 Control Registers for Clamping Circuit 9.3.3 A low-pass filter and a sync separator comprise this block. The sync separator extracts HSYNC and VSYNC from the composite video signal.
Page 232 Closed-Caption Decoder Functional Description MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company Panasonic...
Page 233: Hsync Separator
Table 9-6 Control Registers for Sync Separator Circuit 9.3.3.1 HSYNC Separator The HSYNC separator extracts the HSYNC signal from the composite sync signal using the sampling clock generated by the sync separator clock pulse gen- erator. This circuit also secures and interpolates the HSYNC signal. and interpolating HSYNC As shown in figure 9-7, noise can cause the HSYNC detection circuit to both miss HSYNC pulses and add erroneous ones.
Page 234: Vsync Separator
Closed-Caption Decoder Functional Description 9.3.3.2 VSYNC Separator The VSYNC separator extracts the VSYNC signal from the composite signal. Like the HSYNC separator, it contains programmable methods for eliminating noise. The VCNT register contains these settings. Masking the 0H to 127H range (by setting the VSEPSEL bit of VCNT to 0) prevents VSYNC errors due to noise.
Page 235: Controller And Sampling Circuit
Table 9-7 provides the registers used to control and monitor the data slicer. See the page number indicated for register and bit descriptions. Table 9-7 Control Registers for Data Slicer 9.3.5 The control circuit contains the CRI window generator and the caption data window generator.
Page 236: Cri Detection For Sampling Clock Generation
Closed-Caption Decoder Functional Description 9.3.5.1 CRI Detection for Sampling Clock Generation The decoder captures the caption data on the rising edge of the CRI pulse. To achieve this, it contains a circuit to accurately detect the CRI pulse rises and to generate a data sampling clock.
Page 237: Closed-Caption Decoder Registers
All registers in Closed-caption Decoder block cannot be written by byte (by word only). Read by byte is possible. Table 9-9 Closed-Caption Decoder Register Panasonic Semiconductor Development Company Closed-Caption Decoder Registers CCD0 CCD1 Register Address Address R/W FCCNT x’007E00’ x’007E20’ MAXMIN x’007E02’...
Page 238 Closed-Caption Decoder Closed-Caption Decoder Registers FCCNT: VBI Decoding Format Select Register (FCCNTW Bit: For designs using the closed-cap- tion decoder, always tie the FCCNT Reset: register to x’0008’. R/W: FCPSEL: Hard/soft sampling start position select SYNCSEL: Sync signal select (HSYNC/VSYNC) HCNTSEL[1:0]: HSYNC count value select SLICESEL: Hard/soft slice level select SLICELD[2:0]: Slice level load timing select...
Page 239: Slsf And Slhd Multiplexing
MAXMIN: CRI Interval Maximum and Minimum Register (MAXMINW Bit: MAX7 MAX6 MAX5 MAX4 MAX3 MAX2 MAX1 MAX0 MIN7 MIN6 MIN5 MIN4 MIN3 MIN2 MIN1 MIN0 Reset: R/W: MAX[7:0]: Maximum value during the CRI interval MIN[7:0]: Minimum value during the CRI interval SLICE: VBI Data Slice Level Register (SLICEW Bit:...
Page 240 Closed-Caption Decoder Closed-Caption Decoder Registers HNUM: HSYNC Count Register (HNUMW Bit: Reset: R/W: VBIIRQ[4:0]: VBI interrupt timing control SBFLAG: Start bit detection flag HNUM[4:0]: HSYNC count during the VBI interval ACQ1: ACQ Capture Timing Control Register 1 (ACQ1W Bit: For designs using the closed-cap- tion decoder, always tie the ACQ1 Reset: register to x’1312’.
Page 241 CRIFA: CRI Frequency Width Register A (CRIFAW Bit: FQW7 Reset: R/W: CRI2FQW[7:0]: CRI frequency width 2 CRI1FQW[7:0]: CRI frequency width 1 CRIFB: CRI Frequency Width Register B (CRIFBW Bit: FQW7 Reset: R/W: CRI4FQW[7:0]: CRI frequency width 4 CRI3FQW[7:0]: CRI frequency width 3 CRI1S: CRI Capture Start Timing Control Register 1 (CRI1SW Bit:...
Page 242 Closed-Caption Decoder Closed-Caption Decoder Registers CRI1E: CRI Capture Stop Timing Control Register 1 (CRI1EW Bit: Reset: R/W: CRI1E[10:0]: Stop position for CRI capture 1 CRI2S: CRI Capture Start Timing Control Register 2 (CRI2SW Bit: Reset: R/W: CRI2S[10:0]: Start position for CRI capture 2 CRI2E: CRI Capture Stop Timing Control Register 2 (CRI2EW Bit:...
Page 243 DATAE: Data Capture Stop Timing Control Register (DATAEW Bit: Reset: R/W: DATAE[10:0]: Stop position for data capture STAP: Sampling Start Position Register (Software Setting) (STAPW Bit: Reset: R/W: SFTSTAP[10:0]: Software setting for sampling start position (in clock units) FCPNUM: Sampling Start Position Register (Hardware Calculation) (FCPNUMW Bit: Reset:...
Page 244 Closed-Caption Decoder Closed-Caption Decoder Registers FQSEL: Frequency Select Register (FQSELW Bit: Reset: R/W: VFQDIV[5:0]: Sampling frequency setting for VSYNC separator FQDIV[3:0]: Sampling frequency setting for HSYNC separator SCMING: Minimum Sync Level Detection Interval Set Register (SCMINGW Bit: Reset: R/W: SCMING[9:0]: Interval setting for the minimum sync level detection BPPST: Backporch Position Register (BPPSTW Bit:...
Page 245: Backporch Position Setting
SYNCMIN: Sync and Pedestal Level Register (SYNCMINW Bit: Reset: R/W: BPLV[6:0]: Pedestal level SYNCMIN[6:0]: Minimum sync level SPLV: Sync Separator Level Set Register (SPLVW Bit: Reset: R/W: Panasonic Semiconductor Development Company Use this register to specify the position for capturing the pedestal level value used during pedestal clamping.
Page 246: Bsp And Psp Multiplexing
Closed-Caption Decoder Closed-Caption Decoder Registers BSP[5:0]: Sync separator level for pedestal clamping PSP[5:0]: Sync separator level for sync tip clamping CLAMP: Clamping Control Register (CLAMPW Bit: Reset: R/W: PCLV[6:0]: Pedestal clamping level setting VBION: VBI setting SAFE: Clamping current source select CLMODE[1:0]: Clamping mode setting MN102H75K/F75K/85K/F85K LSI User Manual Composite signal...
Page 247 HSEP1: HSYNC Separator Control Register 1 (HSEP1W Bit: Reset: R/W: HSFREQ[10:0]: Correction HSYNC frequency HSEP2: HSYNC Separator Control Register 2 (HSEP2E Bit: Reset: R/W: HCLOSEE[9:0]: Start position for HSYNC detection FIELD: Field Detection Control Register (FIELDW Bit: EVEN Reset: R/W: ODDEVEN: Field detection signal VPHASE[9:0]: Phase difference setting for VSYNC and HSYNC HLOCKLV: Sync Separator Detection Control Register 1...
Page 248 Closed-Caption Decoder Closed-Caption Decoder Registers HDISTW: Sync Separator Detection Control Register 2 HDISTWW Bit: Reset: R/W: HDISTW[8:0]: HSYNC count setting the interval for sync separation detection VCNT: VSYNC Separator Control Register (VCNTW Bit: Reset: R/W: VSEPSEL: VSYNC signal select VSEPLMT[2:0]: VSYNC separation detection threshold HVCOND: Sync Separator Status Register (HVCONDW Bit:...
Page 249 CLPCND1: Clamping Control Signal Status Register 1 (CLPCNDW Bit: Reset: R/W: SAFEP: Low clamping control pulse for high current source (P-channel) SAFEN: Low clamping control pulse for high current source (N-channel) CLPP: High clamping control pulse for high current source (P-channel) CLPN: High clamping control pulse for high current source (N-channel) XPEDUP: Clamping control pulse for medium current source (P-channel) XPEDOWN: Clamping control pulse for medium current source (N-channel)
Page 250: Pulse Width Modulator
Pulse Width Modulator Description 10 Pulse Width Modulator 10.1 Description The MN102H75K/85K contains seven 8-bit pulse width modulators (PWMs) with a minimum pulse width of 16/f For information on the SLOW mode) and 2 mode, see section 3.1, “CPU Modes.” The PWM ports are 3.3-volt, open-drain outputs.
Page 251: Block Diagram
10.2 Block Diagram Note: With a 4-MHz oscillator: Not using internal pullup func- tion,Figuer10-2 connect the external pullup registance 10.3 PWM Data Registers All registers in PWM function cannot be written by byte (be word only). Read by byte is possible. Bits 7 to 0 of each of the seven PWM data registers (PWM0 to PWM6) hold the 8-bit pulsewidth modulated data to be written to the PWMs.
Page 252: I/O Ports
I/O Ports Description 11 I/O Por ts 11.1 Description The MN102H75K/85K contains 50 pins that form general-purpose I/O ports. Ports 0, 1, 2, 3, 4, and 5 are 8-bit ports, and port 6 is a 2-bit port. All of these pins have alternate functions.
Page 253: I/O Port Circuit Diagrams
11.2 I/O Port Circuit Diagrams 0: P00/IRQ0 1: RMIN/IRQ0 0: Port input 1: Port output 0: Port low output 1: Port high output P0IN0 RMIN IRQ0 Panasonic Semiconductor Development Company 0: Pullup off 1: Pullup on P0PUP0 P0MD0 P0DIR0 P0OUT0 Figure 11-1 P00/RMIN/IRQ0 (Port 0) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic...
Page 254: P03/Adin0 To P07/Adin4 (Port 0)
I/O Ports I/O Port Circuit Diagrams 0: P03, P04, P05, P06, P07, 1: ADIN0, ADIN1, ADIN2, ADIN3, ADIN4 0: Port input 1: Port output 0: Port low output 1: Port high output P0INn ADIN0, ADIN1, ADIN2, ADIN3, ADIN4 Figure 11-2 P03/ADIN0 to P07/ADIN4 (Port 0) MN102H75K/F75K/85K/F85K LSI User Manual 0: Pullup off 1: Pullup on...
Page 255: P10/Adin5/Irq1, P11/Adin6/Irq2, And P12/Adin7/Irq3 (Port 1)
0: P10/IRQ1, P11/IRQ2, P12/IRQ3 1: ADIN5, ADIN6, ADIN7 0: Port input 1: Port output 0: Port low output 1: Port high output P1INn IRQ1, IRQ2, IRQ3 ADIN5, ADIN6, ADIN7 Figure 11-3 P10/ADIN5/IRQ1, P11/ADIN6/IRQ2, and P12/ADIN7/IRQ3 (Port 1) Panasonic Semiconductor Development Company 0: Pullup off 1: Pullup on P1PUPn...
Page 256: P13/Adin8/Wdout And P14/Adin9/Stop (Port 1)
I/O Ports I/O Port Circuit Diagrams 00: P13, P14 01: WDOUT, STOP 10: ADIN8, ADIN9 0: Port input 1: Port output 0: Port low output 1: Port high output WDOUT, STOP P1INn ADIN8, ADIN9 Figure 11-4 P13/ADIN8/WDOUT and P14/ADIN9/STOP (Port 1) MN102H75K/F75K/85K/F85K LSI User Manual 0: Pullup off 1: Pullup on...
Page 257: P15/Adin10/Pwm0 And P16/Adin11/Pwm1 (Port 1)
00: P15,P16 01: PWM0,PWM1 10: ADIN10,ADIN11 PWM0,PWM1 0: Port low output 1: Port high output P1INn ADIN10,ADIN11 Figure 11-5 P15/ADIN10/PWM0 and P16/ADIN11/PWM1 (Port 1) Panasonic Semiconductor Development Company 0: Pullup off 1: Pullup on P1PUPn P1MD(2n) P1MD(2n+1) 0: Port input 1: Port output P1DIRn P1OUTn...
Page 258: Pwm2 (Port 1), P20/Pwm3, P21/Pwm4, P22/Pwm5, And P23/Pwm6 (Port 2)
I/O Ports I/O Port Circuit Diagrams 0: P17, P20, P21, P22, P23 1: PWM2, PWM3, PWM4, PWM5, PWM6 PWM2, PWM3, PWM4, PWM5, PWM6 0: Port low output 1: Port high output Low output P1INn, P2INn Figure 11-6 /PWM2 (Port 1), P20/PWM3, P21/PWM4, P22/PWM5, and P23/PWM6 (Port 2) MN102H75K/F75K/85K/F85K LSI User Manual 0: Pullup off 1: Pullup on...
Page 259: P24/Tm4Ic/Sbt1 (Port 2)
00: P24 01: SBT1 10: TM4IC 0: Port low output 1: Port high output SBT1 output 0: Push/pull 1: Open-drain (I P2IN4 TM4IC input SBT1 input To use as SBT1,set P2MD8 and P2MD9 to 0. Panasonic Semiconductor Development Company 0: Pullup off 1: Pullup on P2PUP4 P2MD8...
Page 260: P27/Tm0Io (Port 2)
I/O Ports I/O Port Circuit Diagrams 0: Port low output 1: Port high output TM0IO output P2IN7 TM0IO input MN102H75K/F75K/85K/F85K LSI User Manual 0: Pullup off 1: Pullup on P2PUP7 0: P27 1: TM0IO P2MD14 0: Port input 1: Port output P2DIR7 P2OUT7 Figure 11-8 P27/TM0IO (Port 2)
Page 261: P35/Darout/R, P36/Dagout/G, P37/Dabout/B (Port 3), And P40/Daymout/Ym (Port 4)
0: Pullup off 1: Pullup on 0: DAC output 1: Digital output (OSD1)bp0 0: P35, P36, P37, P40 1: DAROUT/R, DAGOUT/G DABOUT/B, DAYMOUT/YM 0: Port input 1: Port output 0: Port low output 1: Port high output ROUT, GOUT, BOUT, YMOUT (Digital output) P3INn P4INn...
Page 262: P25/Tm4Iob/Sbi1/Sbd1 And P26/Tm4Ioa/Sbo1 (Port 2)
I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on 00: P25 01: SBI1,SBD1 10: TM4IOB 11: Reserved 0: Port input 1: Port output 0: 3-line (SBI1,SBD1,SBT1) (PCNT0) bit 11 1: 2-line (SBD1,SBT1) SIFSEL1 0: Port low output 1: Port high output SBO1 TM4IOB output...
Page 263: P55 And P56 (Port 5)
0: Pullup off 1: Pullup on 0: Port input 1: Port output 0: Push-pull 1: Open-drain (PCNT0) bit 12 (For I C mode) ODASCI0 SBO0 0: Port low output 1: Port high output P5IN5 SBI0 0: Pullup off 1: Pullup on 0: P56 1: SBI0/SBD0 0: Port input...
Page 264: P57/Sbt0 (Port 5)
I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on 0: P57 1: SBT0 0: Port input 1: Port output 0: Push-pull 1: Open-drain (PCNT0) bit 12 (For I C mode) ODASCI0 SBT0 output 0: Port low outut 1: Port high output P5IN7 SBT0 input...
Page 265: P02/Scl1 (Port 0) And P61/Scl0 (Port 6)
0: Pullup off 1: Pullup on 0: P02 1: SCL1 0: Port input 1: Port output 0: Port low output 1: Port high output SCL output P0IN2 SCL input I2CSEL1 I2CSEL0 0: P61 1: SCL0 0: Port input 1: Port output 0: Port low output 1: Port high output P6IN1...
Page 266: P01/Sda1 (Port 1) And P60/Sda0 (Port 6)
I/O Ports I/O Port Circuit Diagrams SDA output P0IN1 SDA input I2CSEL1 I2CSEL0 0 : P60 1 : SDA0 0: Port input 1: Port output 0: Port low output 1: Port high output P6IN0 Figure 11-14 P01/SDA1 (Port 1) and P60/SDA0 (Port 6) MN102H75K/F75K/85K/F85K LSI User Manual 0: Pullup off 1: Pullup on...
Page 267: P31/Cvbs0 And P32/Cvbs1 (Port 3)
0: P31,P32 1: CVBS0,CVBS1 0: Port input 1: Port output 0: Port low output 1: Port high output P3INn CVBS0,CVBS1 Figure 11-15 P31/CVBS0 and P32/CVBS1 (Port 3) Panasonic Semiconductor Development Company 0: Pullup off 1: Pullup on P3PUPn P3MDn P3DIRn P3OUTn MN102H75K/F75K/85K/F85K LSI User Manual Panasonic...
Page 268: P30/Clh And P33/Cll (Port 3)
I/O Ports I/O Port Circuit Diagrams 0: P30, P33 1: CLH, CLL 0: Port input 1: Port output 0: Port low output 1: Port high output P3INn CLH, CLL Figure 11-16 P30/CLH and P33/CLL (Port 3) MN102H75K/F75K/85K/F85K LSI User Manual 0: Pullup off 1: Pullup on P3PUPn...
Page 269: P34/Vref (Port 3)
I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P3PUP4 0: P34 1: VREF P3MD4 0: Port input 1: Port output P3DIR4 0: Port low output 1: Port high output P3OUT4 P34/VREF P3IN4 VREF Figure 11-17 P34/VREF (Port 3) Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual Panasonic...
Page 270: P41/Tm1Io, P42/Tm5Ioa, And P43/Tm5Iob/Hi0 (Port 4)
I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on 0: Port input 1: Port output 0: P41,P42,P43 1: TM1IO,TM5IOA,TM5IOB 0: Port low output 1: Port high output TM1IO output, TM5IOA output, TM5IOB output P4INn TM1IO input, TM5IOA input, TM5IOB output, HI0 Figure 11-18 P41/TM1IO, P42/TM5IOA, and P43/TM5IOB/HI0 (Port 4) 0: Port input...
Page 271: P45/Osdxo And P46/Osdxi (Port 4)
To internal circuit P4IN5 LCCNT is the OSDXI/O oscillation control signal from the OSD. 0: Disable 1: Enable LCCNT 0: Pullup off 1: Pullup on 0: P45/P46 1: OSDXI/OSDXO 0: Port input 1: Port output 0: Port low output 1: Port high output P4IN6 Figure 11-20 P45/OSDXO and P46/OSDXI (Port 4) Panasonic Semiconductor Development Company...
Page 272: P47/Hsync (Port 4)
I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on 0: P47 1: HSYNC 0: Port input 1: Port output 0: Port low output 1: Port high output P4IN7 HSYNC MN102H75K/F75K/85K/F85K LSI User Manual P4PUP7 P4MD7 P4DIR7 P4OUT7 Figure 11-21 P47/HSYNC (Port 4) Panasonic Semiconductor Development Company Panasonic...
Page 273: P50/Sysclk (Port 5)
0: Pullup off 1: Pullup on 0: P50 1: SYSCLK 0: Port input 1: Port output 0: Port low output 1: Port high output SYSCLK or divided SYSCLK output P5IN0 Panasonic Semiconductor Development Company P5PUP0 P5MD0 P5DIR0 P5OUT0 Figure 11-22 P50/SYSCLK (Port 5) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic I/O Ports...
Page 274: P51/Ys (Port 5)
I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on 0: P51 1: YS 0: Port input 1: Port output 0: Port low output 1: Port high output YSOUT P5IN1 MN102H75K/F75K/85K/F85K LSI User Manual P5PUP1 P5MD1 P5DIR1 P5OUT1 Figure 11-23 P51/YS (Port 5) Panasonic Semiconductor Development Company Panasonic...
Page 275: P52/Irq4/Vi0 (Port 5)
0: Pullup off 1: Pullup on 0: P52 1: IRQ4/VI0 0: Port input 1: Port output 0: Port low output 1: Port high output P5IN2 IRQ4/VI0 Panasonic Semiconductor Development Company P5PUP2 P5MD2 P5DIR2 P5OUT2 Figure 11-24 P52/IRQ4/VI0 (Port 5) MN102H75K/F75K/85K/F85K LSI User Manual Panasonic I/O Ports I/O Port Circuit Diagrams...
Page 276: P53/Rst (Port 5)
I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on 0: Port low output 1: Port high output 0: Port input 1: Port output P5IN3/ NTGTRST MN102H75K/F75K/85K/F85K LSI User Manual P5PUP3 P5OUT3 P5DIR3 Figure 11-25 P53/RST (Port 5) Panasonic Semiconductor Development Company Panasonic P53/...
Page 277: P54/Irq5/Vsync (Port 5)
I/O Ports I/O Port Circuit Diagrams 0: Pullup off 1: Pullup on P5PUP4 0: P54/IRQ5 1: IRQ5/VSYNC P5MD4 0: Port input 1: Port output P5DIR4 0: Port low output 1: Port high output P5OUT4 P54/IRQ5/VSYNC P5IN4 Schmidt trigger IRQ5 VSYNC Figure 11-26 P54/IRQ5/VSYNC (Port 5) Panasonic Semiconductor Development Company MN102H75K/F75K/85K/F85K LSI User Manual...
Page 278: I/O Port Control Registers
I/O Ports I/O Port Control Registers 11.3 I/O Port Control Registers P0PUP–P5PUP: Ports 0–5 Pullup Resistor Control Registers x’00FFB0’–x’00FFB5’ P7PUP–P8PUP: Ports 7–8 Pullup Resistor Control Registers x’00FFB8’–x’00FFBA’ Bit: Do not activate the pullup resis- PnPUP7 PnPUP6 PnPUP5 PnPUP4 PnPUP3 PnPUP2 PnPUP1 PnPUP0 tors when the pins are in output Reset: mode.
Page 279 P0IN–P5IN: Ports 0–5 Input Registers P7IN–P8IN: Ports 7–8 Input Registers Bit: Reset: R/W: P6IN: Port 6 Input Register Bit: Reset: R/W: P0DIR–P5DIR: Ports 0–5 I/O Control Registers P7DIR–P8DIR: Ports 7–8 I/O Control Registers Bit: PnDIR7 PnDIR6 PnDIR5 PnDIR4 PnDIR3 PnDIR2 PnDIR1 PnDIR0 When using P57 as a port, set SIFSEL0 (PCNT0 x’FF90’...
Page 280 I/O Ports I/O Port Control Registers P0MD: Port 0 Output Mode Register Bit: Reset: R/W: P0MD7: P07 function switch P0MD6: P06 function switch P0MD5: P05 function switch P0MD4: P04 function switch P0MD3: P03 function switch P0MD2: P02 function switch P0MD1: P01 function switch P0MD0: P00 output switch MN102H75K/F75K/85K/F85K LSI User Manual P0MD7 P0MD6 P0MD5 P0MD4 P0MD3 P0MD2 P0MD1 P0MD0...
Page 281 P1MD: Port 1 Output Mode Register Bit: Reset: R/W: P1MD14: P17 output switch P1MD[13:12]: P16 output and function switch P1MD[11:10]: P15 output and function switch P1MD[9:8]: P14 output and function switch P1MD[7:6]: P13 output switch P1MD4: P12 function switch P1MD2: P11 function switch P1MD0: P10 function switch Panasonic Semiconductor Development Company P1MD...
Page 282 I/O Ports I/O Port Control Registers P2MD: Port 2 Output Mode Register Bit: Reset: R/W: P2MD14: P27 function switch P2MD[13:12]: P26 output and function switch P2MD[11:10]: P25 output and function switch P2MD[9:8]: P24 output and function switch P2MD6: P23 output switch P2MD4: P22 output switch P2MD2: P21 output switch P2MD0: P20 output switch...
Page 283 P3MD: Port 3 Output Mode Register Bit: Reset: R/W: P3MD7: P37 output switch P3MD6: P36 output switch P3MD5: P35 output switch P3MD4: P34 function switch P3MD[3:1]: P33-P30 function switch P3MD0 Panasonic Semiconductor Development Company P3MD7 P3MD6 P3MD5 P3MD4 P3MD3 P3MD2 P3MD1 P3MD0 P3MD is an 8-bit access register.
Page 284 I/O Ports I/O Port Control Registers P4MD: Port 4 Output Mode Register Bit: Reset: R/W: P4MD7: P47 function switch P4MD6 P4MD5: P45 function switch P4MD4: P44 output switch P4MD3: P43 output switch P4MD2: P42 output switch P4MD1: P41 output switch P4MD0: P40 output switch MN102H75K/F75K/85K/F85K LSI User Manual P4MD7 P4MD6 P4MD5 P4MD4 P4MD3 P4MD2 P4MD1 P4MD0...
Page 285 P5MD: Port 5 Output Mode Register Bit: Reset: R/W: P5MD7: P57 output switch P5MD6: P56 output switch P5MD5: P55 output switch P5MD4: P54 function switch P5MD3 P5MD2: P52 output switch P5MD1: P51 output switch P5MD0: P50 output switch P6MD: Port 6 Output Mode Register Bit: Reset: R/W:...
Page 286 I/O Ports I/O Port Control Registers PCNT0: Port Control Register 0 Bit: SCLK Reset: R/W: SCLKF[1:0]: SYSCLK frequency select Enable PWM (set PCNT1 bit 1 to 1) if you are outputting f ODASCI1: Serial port 1 output switch SCLK ODASCI0: Serial port 0 output switch SIFSEL1: Serial port 1 interface select SIFSEL0: Serial port 0 interface select I2CSEL1: SDA1, SCL1 enable...
Page 287 OSDPOFF: OSD circuit enable To turn off the OSD block to save power: 1. Write a 0 to OSD (OSD1, bit 10). PLLPOFF: PLL circuit enable 2. Wait for the next VSYNC input. 3. Write a 0 to OSDPOFF (PCNT0, bit 7), turning the clock off.
Page 288 I/O Ports I/O Port Control Registers PCNT2: Port Control Register 2 Bit: Reset: R/W: P7P8CNT: Ports 7 and 8 forced pullup Always set bits 7 to 3 of PCNT2 to 0. I2COFF: I PWMOFF: PWM function enable You cannot read from or write to the registers associated with a function that is disabled.
Page 289: Rom Correction
12 ROM Correction 12.1 Description The ROM correction function can correct the program data in any address within the 256-kilobyte ROM. (It cannot correct OSD ROM data.) A maximum of sixteen addresses can be corrected. Addresses are set as address match interrupts. This function shortens time-to-market for large-scale designs, since changes can be implemented in the software after the mask ROM is complete.
Page 290: Block Diagram
ROM Correction Block Diagram 12.2 Block Diagram Figure 12-3 is a block diagram of the ROM correction circuit. A match detection circuit constantly monitors the ROM address specified by the CPU instruction pointer (IP). When the value matches a correction address, the circuit replaces the data output from the ROM with the data in the appropriate correction data register.
Page 291: Rom Correction Control Registers
12.4 ROM Correction Control Registers Table 12-1 shows the organization of the address match and data registers for ROM correction. Write a ROM address to be corrected to an AMCHIHn and AMCHILn register pair and write the corrected data to the associated CHDATn register.
Page 292 ROM Correction ROM Correction Control Registers ROMCEN12: Address 12 ROM correction enable ROMCEN11: Address 11 ROM correction enable ROMCEN10: Address 10 ROM correction enable ROMCEN9: Address 9 ROM correction enable ROMCEN8: Address 8 ROM correction enable ROMCEN7: Address 7 ROM correction enable ROMCEN6: Address 6 ROM correction enable ROMCEN5: Address 5 ROM correction enable ROMCEN4: Address 4 ROM correction enable...
Page 293 AMCHIH0–AMCHIHF: ROM Correction Address Match Register n (High) Bit: Reset: R/W: CHAD[23:16]: Correction address bits A23 to A16 (A23 = MSB) AMCHIL0–AMCHILF: ROM Correction Address Match Register n (Low) Bit: CHAD Reset: R/W: CHAD[15:0]: Correction address bits A15 to A0 CHDAT0–CHDAT15: ROM Correction Data Register n Bit: Reset:...
Page 294: C Bus Controller
C Bus Controller Description 13 I C Bus Controller 13.1 Description The MN102H75K/85K contains one I An I requires only two lines, a serial data line (SDA) and a serial clock line (SCL), it minimizes interconnections so ICs have fewer pins and there are less PCB tracks. The result is smaller and less expensive PCBs.
Page 295: Operating Modes For Devices On An I 2 C Bus
Figure 13-2 shows an example of an I trollers. Both I positive supply voltage via a pullup resistor. The open-drain output pins of the microcontrollers perform the wired-AND function on the bus. The software controls when each microcontroller operates as a transmitter or receiver, or whether is in master or slave mode.
Page 296: C Bus Interface Operation
C Bus Controller Description Figure 13-3 shows the MN102H75K/85K operation sequence in each of these modes. In all modes, the I byte transfer, then the software loads the next data byte. MN102H75K/F75K/85K/F85K LSI User Manual C bus controller generates an interrupt after each data Interrupt MN102H51K R/W = 0...
Page 297: Block Diagram
13.2 Block Diagram 13.3 Functional Description The I number indicated for register and bit descriptions. Table 13-3 Control Registers for Clamping Circuit Arbitration and bus busy control The I timing and bus arbitration completely in the hardware. Panasonic Semiconductor Development Company Digital filter Parallel-to-serial...
Page 298 C Bus Controller Functional Description Register settings conversions to I The I protocol. Transfer modes changes A write to the I2CDTRM register indicates the transfer mode (master transmitter/ receiver or slave transmitter/receiver) for a new transfer. To minimize software control, the hardware generates an interrupt each time a transfer ends. During interrupt servicing, the SCL line stays low, then clears to high on a write to I2CDTRM.
Page 299: Setting Up The I
13.4 Setting Up the I Set the I (x’00FF90’). Since the SCL0, SDA0, SCL1, and SDA1 pins also serve as general-purpose port pins, and reset to the general-purpose function, you must set these bits every time the program uses the I of the P6MD register (x’00FFFC’).
Page 300: Sda And Scl Waveform Characteristics
C Bus Controller SDA and SCL Waveform Characteristics 13.5 SDA and SCL Waveform Characteristics Figure 13-6 and table 13-5 provide the timing definitions and specifications for the for the MN102H75K/85K I ; DAT ;STA Table 13-5 SDA and SCL Waveform Characteristics MN102H75K/F75K/85K/F85K LSI User Manual C bus interface.
Page 301: I 2 C Interface Setup Examples
13.6 I 13.6.1 Setting Up a Transition from Master Transmitter to Mas- This example demonstrates how to set up a data transfer when changing from master transmitter to master receiver. Figure 13-7 shows an example waveform. 13.6.1.1 Pre-configuring To set up the I/O port: Set port control register 0 (PCNT0;...
Page 302: Setting Up The Second Interrupt
C Bus Controller C Interface Setup Examples 13.6.1.3 Setting Up the Second Interrupt When the microcontroller receives the data x’85’ from the slave device, it returns an ACK = 0 signal and the I implement the following settings: To set up the interrupt: Set the I2C0ICH and I2C0ICL register pair (x’00FC9C’) to x’0100’.
Page 303: Setting Up A Transition From Slave Receiver To Slave Transmitter
13.6.2 Setting Up a Transition from Slave Receiver to Slave This example demonstrates how to set up a data transfer when changing from slave receiver to slave transmitter. Figure 13-8 shows an example waveform. 13.6.2.1 Pre-configuring To set up the I/O port: Set port control register 0 (PCNT0;...
Page 304: Setting Up The Second Interrupt
C Bus Controller C Interface Setup Examples 13.6.2.3 Setting Up the Second Interrupt The master sends an ACK = 0 signal, so the microcontroller must send the next data byte. Set up the transmission data as follows: To set up the interrupt: Set the I2C0ICH and I2C0ICL register pair (x’00FC9C’) to x’0100’.
Page 305: I 2 C Bus Interface Registers
13.7 I All registers in I is possible. I2CDTRM: I Bit: Reset: R/W: STA: I STO: I SCL is held low during interrupt servicing, and is cleared high by a write to I2CDTRM. Table 13-6 STA and STO Settings ACK: Acknowledge signal output control DT[7:0]: Data to be transmitted Panasonic Semiconductor Development Company C Bus Interface Registers...
Page 306 C Bus Controller C Bus Interface Registers I2CDREC: I Bit: Reset: R/W: MODE[1:0]: I STS: Stop condition at slave receiver LRB: Last received bit. AAS: Addressed as slave LAB: Lost arbitration bit BB: Bus busy bit D[7:0]: Received data I2CMYAD: I Bit: Reset: R/W:...
Page 307 I2CCLK: I Bit: Reset: R/W: C[9:0]: Output clock frequency select To conform to the specification, the clock signal must be between 0 and 100 kHz. To sat- isfy this requirement, always set I2CCLK to x’032’ or higher. I2CBRST: I Bit: Reset: R/W: BRST: Bus reset...
Page 308: Counter
H Counter Description 14 H Counter 14.1 Description The MN102H75K/85K contains two H counter circuits that can be used to count the HSYNC signal. Each H counter consists of a 10-bit counter and 10-bit register. 14.2 Block Diagram waveform 341-µs signal from PWM block 14.3 H Counter Operation Figure 14-2 provides a schematic diagram of an example counter operation.
Page 309: H Counter Pins
Figure 14-3 shows the input timing for the count source and reset signals. Never input a count source signal in less than 245 ns (t Otherwise, the signal may be counted as part of the previous count cycle. Note: In this example, HI0 is active high and VSYNC is active low. The 10-bit counter counts the HSYNC signal from 0 to x’3FF’, and the 10-bit register stores the count.
Page 310 H Counter H Counter Operation The H counter counts the HSYNC signal for the interval set in the HCCNT0 (x’007EB0’) or HCCNT1 (x’007EB2’) register, latches the count value in the 10- bit register, then clears the counter. HCCNT0 and HCCNT1 provide six interval settings: If your application uses one of the fixed clocks based on divided PWM output (1024, 2048, 4098, or 8096 µs), you must also set up the PWM circuit.
Page 311: H Counter Control Registers
14.4 H Counter Control Registers All registers in H Counter block cannot be written by byte (by word only). Read by byte is possible. HCCNT0: H Counter Control Register 0 Bit: Reset: R/W: SEDG0: Polarity select for count source signal (HI0) SEDG0: Polarity select for reset signal SELR20:00]: Reset signal select HCCNT1: H Counter Control Register 1...
Page 312 H Counter H Counter Control Registers HCD0: H Counter Data Register 0 Bit: Reset: R/W: HCD[90:00]: Count from HI0 source signal HCD1: H Counter Data Register 1 Bit: Reset: R/W: HCD[91:01]: Count from HI1 source signal MN102H75K/F75K/85K/F85K LSI User Manual —...
Page 313: Appendix A Register Map
Appendix A Register Map Table A-1 Register Map: x’007E00’ to x’007FFF’ (Registers in this area cannot be written by byte only by word.) MSBs CRI4 CRI3 CRI2 CRI1 007E00 CAPDA 007E10 FCPNUM STAP DATAE CRI4 CRI3 CRI2 CRI1 007E20 CAPDAW ACQ1W 007E30 STAPW DATAEW DATASW CRI2EW CRI2SW CRI1EW CRI1SW...
Page 314: Register Map: X'00Fc00' To X'00Fdff
Register Map Table A-2 Register Map: x’00FC00’ to x’00FDFF’ MSBs 00FC00 IAGR 00FC10 00FC20 00FC30 00FC40 00FC50 VBIW VBIW TM5UD TM5UD TM5CA TM5CA 00FC60 ADM0 ADM0 ADM1 ADM1 ADM2 ADM2 00FC70 VBIV VBIV TM3UD TM3UD 00FC80 SCR1 SCR1 00FC90 00FCA0 00FCB0 00FCC0 00FCD0...
Page 315: Register Map: X'00Fe00' To X'00Ffff
Table A-3 Register Map: x’00FE00’ to x’00FFFF’ MSBs 00FE00 00FE10 00FE20 00FE30 00FE40 00FE50 00FE60 00FE70 (TM4CBX TM4TST 00FE80 (test register) (TM5CBX TM5TST 00FE90 (test register) 00FEA0 00FEB0 00FEC0 00FED0 00FEE0 00FEF0 00FF00 AN3BUF AN2BUF AN1BUF AN0BUF 00FF10 AN11BUF AN10BUF AN9BUF AN8BUF AN7BUF AN6BUF AN5BUF AN4BUF 00FF20 00FF30 00FF40...
Page 316 Register Map MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company Panasonic...
Page 317: B.1 Description
Appendix B MN102HF75K Flash EEPROM Version The MN102HF75K and MN102HF85K are electrically programmable, 256- kilobyte flash ROM versions of the MN102H75K and MN102H85K. They are programmed in one of two modes: A cycle of erasing to programing is In onboard serial programming mode, the 256-kilobyte flash memory is divided counted as one time no matter how into three main areas: many blocks are rewritten.Even...
Page 318: Benefits
MN102HF75K Flash EEPROM Version Benefits Because you can maintain and upgrade the program in the MN102HF75K/85K up to and immediately following product release, this version of the device shortens time-to-market by as much as one month. This device is ideal for appli- cations in quickly changing markets, since it allows you to revise the microcon- troller program in an existing product.
Page 319: Prom Writer Hardware
Table B-2 PROM Writer Hardware Check the following web page of our microcomputer division for the writer matching information. http://www.mec panasonic.co.jp/sc/division/micom Panasonic Semiconductor Development Company MN102HF75K Flash EEPROM Version Hardware Part MN102HF75KBF Package (external view) Installed in 84-pin QFP Adaptor Installed in Panasonic Ordering information:...
Page 320: Using The Onboard Serial Programming Mode
MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode The serial programming mode is primarily used to program the flash ROM in devices that are already installed on a PCB board. Panasonic provides the ded- icated hardware and software for this mode. This section describes the microcon- troller hardware, system configuration, software register map, and protocol for this type of programming operation.
Page 321: Configuring The System For Onboard Serial Programming
B.4.1 Configuring the System for Onboard Serial Programming The workstation containing the program data sends the program to the serial writer through an IC card. Through serial communication, the serial writer programs the flash memory inside the microcontroller on the target board. You must supply an external V the V You must provide the personal computer that holds the IC card.
Page 322: Circuit Requirements For The Target Board
MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode B.4.2 Circuit Requirements for the Target Board Table B-3 Pin Descriptions for Target Board–Serial Writer Connection MN102H75K/F75K/85K/F85K LSI User Manual = +5 V (for level detection) 10 k Serial writer Figure B-6 Target Board–Serial Writer Connection Pin Name 5-V power supply...
Page 323: Microcontroller Hardware Used In Onboard Serial Programming
B.4.3 Microcontroller Hardware Used in Onboard Serial Pro- B.4.3.1 Serial Writer Interface Description The microcontroller contains the following interface hardware for serial pro- gramming of the flash ROM: B.4.3.2 Serial Writer Interface Block Diagram When programming the memory, you need not be aware of these microcontroller hardware connections.
Page 324: Microcontroller Memory Map Used During Onboard Serial Programming
MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode B.4.4 Microcontroller Memory Map Used During Onboard B.4.4.1 Flash ROM Address Space Table B-4 Flash ROM Address Space in Serial Programming Mode Serial writer load program area This kilobyte of ROM, starting at address x’0x80000’, holds the load program for the serial writer.
Page 325: Ram Address Space
Branch instruction to interrupt service routine Normally, interrupt servicing starts at address x’0x80008’, but the soft branch instruction in the serial writer load program branches to x’0x82018’. This address must hold a JMP instruction pointing to the real start address for the interrupt service routine.
Page 326: Setting Up The Onboard Serial Programming Mode
MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode B.4.6 Setting Up the Onboard Serial Programming Mode To enter serial programming mode, the microcontroller must be in write mode. This section describes the pin setup for the serial writer interface. Normal timing waveform Timing waveform during serial programming...
Page 327: Load Program Start Flow
Start routine for the load program Conditions: If any of these conditions is not met, control returns to the user program. Panasonic Semiconductor Development Company MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode Reset start SBT pin == high &&...
Page 328: Branching To The User Program
MN102HF75K Flash EEPROM Version Using the Onboard Serial Programming Mode B.4.7 Branching to the User Program B.4.7.1 Branching to the Reset Start Routine When the reset starts, the serial writer load program initializes only if SBD is low. Otherwise, the program branches to the user program at address x’0x82010’. B.4.7.2 Branching to the Interrupt Start Routine In the interrupt start address, place a simple branch instruction pointing to address x’0x82018’.
Page 329: Reprogramming Flow
Figure B-12 shows the flow for reprogramming (erasing and programming) the flash memory. Always program after erasing is As the figure shows, the write occurs after the memory is completely erased. The completed.Erasing is sometimes not erase routine consists of three steps, first writing all zeros to the entire memory done finely,even though PROM- space, next erasing the memory, and finally reversing.
Page 331 MN102H75K/F75K/85K/F85K LSI User’s Manual Modified Points From MN102H75K/F75K To MN102H75K/F75K/85K/F85K page Before Modify This manual is intended for assembly-language programming engineers. It describes the internal configuration and hardware functions of the MN102H75K microcontrollers. Using This Manual The chapters in this manual deal with the internal blocks of the MN102H75K.
Page 332 Pin Descriptions 1.6.1 MN102H75K Pin Description P55, SBO0 P54, IRQ5, VSYNC P53, RST P52, IRQ4, VI0 TEST P51, YS P50, SYSCLK 84-Pin QFP Top View P47, HSYNC P46, OSDXI P45, OSDXO * P44, TM5IC, HI1 * P43, TM5IOB, HI0 * P42, TM5IOA * P41, TM1IO VCOI Notes: 1.
Page 333 The MN102H75K contains an internal PLL circuit. To use this circuit, you must connect it to an external (lag-lead) filter. The most important factor in real-time control is an MCU’s speed in servicing interrupts. The MN102H75K has an extremely fast interrupt response time due to its ability to abort instructions, such as multiply or divide, that require multiple clock cycles.
Page 334 The MN102H75K contains four 8-bit timers that can serve as interval timers, event timer/counters, clock generators (divide-by-2 output of the underflow), reference clocks for the serial interfaces, or start timers for A/D conversions. The clock source can be the internal clock (oscil- lator frequency divided by 2) or the external clock (1/4 or less the oscil- lator frequency input).
Page 335 P307 The MN102H75K contains two H counter circuits that can be used to count the HSYNC signal. Each H counter consists of a 10-bit counter and 10-bit register P308 Table 14-1 H Counter Pins Pin No. Alternative Functions Pin Name Description Count source pin P43/TM5IOB...
Page 337 MN102H75K/F75K/85K/F85K LSI User’s Manual October,2001 1st Edition 1st Printing Issued by Matsushita Electric Industrial Co., Ltd. Matsushita Electric Industrial Co., Ltd.
Page 338 Semiconductor Company, Matsushita Electric Industrial Co., Ltd. NORTH AMERICA U.S.A. Sales Office: Panasonic Industrial Company New Jersey Office: Two Panasonic Way Secaucus, New Jersey 07094 U.S.A. Tel: 1-201-348-5257 Fax:1-201-392-4652 Chicago Office: 1707 N. Randall Road Elgin, Illinois 60123-7847 U.S.A. Tel: 1-847-468-5720 Fax:1-847-468-5725 Milpitas Office: 1600 McCandless Drive Milpitas, California 95035 U.S.A.

This manual is also suitable for:

Mn102f75k Mn102f85k Mn102h75k Mn102h85k

Panasonic MN10285K User Manual

About this Manual

1 General Description

2 Interrupts

3 Low-Power Modes

4 Timers

5 Serial Interfaces

6 Analog-To-Digital Converter

7 On-Screen Display

8 IR Remote Signal Receiver

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