Panasonic MN101L Series User Manual page 465

DMA Control Register 1 lower side (DMCTR1L: 0x03E02)
bp 7
Bit name -
At reset 0
Access R
bp Bit name
7-1 - Always read as "0".
DMA transfer enable control
After the DMTEN is set, DMA waits for the DMA start trigger to occur.
(When the software trigger is selected in DMCTR0L.DMBG4-0, DMA transfer starts immediately after the
0 DMTEN
DMTEN is set to "1".)
When the last data is transferred, the DMTEN is cleared to "0" by hardware. Setting the DMTEN to "0"
during DMA transfer makes the transfer finished, which is called "Emergency stop".
6 5
- -
0 0
R R
4 3
- -
0 0
R R
Description
DMA Controller Control Registers
2 1
- - DMTEN
0 0
R R R/W
Chapter 14
DMA Controller
0
0
XIV - 7