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Chapter 14
DMA Controller
DMA Control Register 0 upper side (DMCTR0H: 0x03E01)
bp
Bit name
At reset
Access
bp
Bit name
7-6
5
DMUT
4
3
DMTM
2
1
DMDAM
0
XIV - 6
DMA Controller Control Registers
7
6
-
-
DMUT
0
0
R
R
R/W
-
Always read as "0".
Data transmission unit
0: 8-bit
1: 16-bit
-
Always read as "0".
Transfer mode
0: Burst transfer
1: Single transfer
-
Always read as "0".
Destination Address increment control
0: Enable (Incremented)
1: Disable (Fixed)
-
Always read as "0".
5
4
-
DMTM
0
0
R
R/W
Description
3
2
-
DMDAM
0
0
R
R/W
1
0
-
0
0
R
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