16-Bit Timer; Operation - Panasonic MN101L Series User Manual

9.3 16-bit Timer

9.3.1

Operation

16-bit Timer Operation (Timer 7, Timer 8 and Timer 9)
When the value of TMnBC matches the setting value of TMnOC1, an interrupt request (TMnIRQ) is generated at
the next count clock. The source of TMnIRQ can be selected by TMnMD2.TMnIRS1. 16-bit timer can generate
another independent interrupt request (TMnOC2IRQ) depending on the setting value of TMnOC2.
TMnMD2.TMnBCR can select the factor of which TMnBC is cleared to "0x0000".
TMnBC is cleared and restarts counting up again.
When TMnBC is cleared "0x0000", the value of timer n preset register is loaded to timer n compare register.
The value of the compare register with double-buffer structure can be changed continuously without disturbing
the cycle even during the timer operation.
When reading the value of TMnBC, use a 16-bit access instruction, MOVW or write data to
TMnIC with a software function.
When using the MOVW instruction, indeterminate data during counting may be read. So,
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read the register value several times and confirm those data are identical.
When using the capture function, writing to TMnIC can capture the count value of TMnBC to
the TMnIC to read the count value during counting precisely.
For more information, refer to [9.8.1 Operation].
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If the count clock is changed during counting, the counter can't count up correctly.
Change the count clock after the timer operation is stopped.
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Set Timer n mode register while the TMnMD1.TMnEN is set to "0" to stop counting.
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To change CPU operation mode from NORMAL to SLOW when high-speed oscillation clock
(HCLK) is selected as a clock source, stop the timer at first. After CPU operation mode has
been changed, start the timer again. In SLOW/HALT1 mode, do not select high-speed oscil-
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lation clock (HCLK) for a clock source.
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When writing data to the 16-bit preset register (TMnPR1 and TMnPR2), use a 16-bit instruc-
tion, MOVW.
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Chapter 9
16-bit Timer
16-bit Timer IX - 21