Maskable Interrupt Control Register Setup - Panasonic MN101L Series User Manual

3.1.3

Maskable Interrupt Control Register Setup

Setting xICR.IR by software
xICR.IR is set to "1" when the interrupt trigger occurs, and cleared to "0" by hardware when the interrupt is
accepted. To operate IR by software, MEMCTR.IRWE needs to be set to "1".
Interrupt Control Register Setup Procedure
Setup procedures of xICR of maskable interrupt is described below:
Setup Procedure
(1) Disable all maskable interrupts
PSW.MIE = 0
(2) Select the interrupt factor
(3) Permission settings of multiple interrupt
MEMCTR.MIESET
(4) Enable the write interrupt request bit
MEMCTR.IRWE = 1
(5) Rewrite the interrupt request bit
xICR.IR
(6) Disable the write interrupt request bit
MEMCTR.IRWE = 0
(7) Set the interrupt level
xICR.LV1-0
PSW.IM1-0
(8) Enable the interrupt
xICR.IE = 1
(9) Enable all maskable interrupts
PSW.MIE = 1
(1) Clear PSW.MIE to disable all maskable interrupts, which
is needed, especially before xICR is changed.
(2) Select the interrupt factor such as interrupt edge selection,
or timer interrupt cycle change.
(3) Set the permission of multiple interrupt. Multiple interrupt
is allowed when MIESET is set to "1".
(4) Set MEMCTR.IRWE to enable IR to be rewritten, which is
needed only when IR is changed by software.
(5) Rewrite xICR.IR. (Clear the bit with this method because it
may already be set.)
(6) Disable IR setting by software.
(7) Set the interrupt level of xICR and PSW.IM1-0.
(8) Set xICR.IE to enable the interrupt.
(9) Enable all maskable interrupts.
Description
Chapter 3
Interrupts
Overview III - 15