Panasonic MN101L Series User Manual page 355

Count Timing of Timer Operation (Timer 6)
Binary counter counts up with the selected clock source as a count clock.
Count clock
TM6CLRS
bit
Compare
M
register
Binary
01 02
counter
1.
Interrupt
request
1. When any data is written to the compare register during the TM6CLRS = 0, the binary counter is cleared to
0x00.
2. Even if any data is written to the compare register during the TM6CLRS = 1, the binary counter is not cleared.
3. When the binary counter reaches the setting value of the compare register during the TM6CLRS = 1, an inter-
rupt request is set at the next count clock.
4. When an interrupt request is set, the binary counter is cleared to 0x00 and restarts counting.
5. Even if the binary counter reaches the setting value of the compare register during the TM6CLRS = 0, no
interrupt request is set.
N
00 01 N-1
Figure:10.3.1 Count Timing of Timer Operation (Timer 6)
2.
N 00 01 02 03
4.
3.
General-Purpose Time Base/Free-Running Timer
M
M-1 M 00
5.
8-bit Free-running Timer
Chapter 10
01
X - 9