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Chapter 14
DMA Controller
14.2.3
DMA Destination Address Register
DMA Destination Address Register lower side (DMDSTL: 0x03E08)
bp
Bit name
At reset
Access
R/W
bp
Bit name
7-0
DMDA7-0
DMA Destination Address Register middle side (DMDSTM: 0x03E09)
bp
Bit name
At reset
Access
R/W
bp
Bit name
7-0
DMDA15-8
DMA Destination Address Register upper side (DMDSTH: 0x03E0A)
bp
Bit name
At reset
Access
bp
Bit name
7-1
0
DMDA16
XIV - 10
DMA Controller Control Registers
7
6
0
0
R/W
R/W
Destination address lower side (bit 0 to 7)
This register shows the address where the next data from source address is stored.
7
6
0
0
R/W
R/W
Destination address middle side (bit 8 to 15)
This register shows the address where the next data from source address is stored.
7
6
-
-
0
0
R
R
-
Always read as "0".
Destination address upper side (bit 16)
This register shows the address where the next data from source address is stored.
5
4
DMDA7-0
0
0
R/W
R/W
Description
5
4
DMDA15-8
0
0
R/W
R/W
Description
5
4
-
-
0
0
R
R
Description
3
2
0
0
R/W
R/W
3
2
0
0
R/W
R/W
3
2
-
-
0
0
R
R
1
0
0
0
R/W
1
0
0
0
R/W
1
0
-
DMDA16
0
0
R
R/W
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