Panasonic MN101L Series User Manual page 101

Determination of Maskable Interrupt Acceptance
The procedures of the interrupt acceptance is described below.
1. IR is set to "1".
2. When IE is "1", the interrupt request is sent to CPU.
3. When LV1-0 is less than PSW.IM1-0 and PSW.MIE is "1", the above interrupt request is accepted.
4. IR is cleared to "0" by hardware. (IE is not cleared by hardware.)
After IR is set to "1" by an interrupt trigger at step 1, if the same interrupt trigger occurs during
the time of above 2 - 4 steps, the latter interrupt trigger is ignored.
.. ..
7
PSW BKD MIE IM1 IM0
In the case of xICR.LV1-0 < PSW.IM1-0,
the interrupt is accepted.
7
xICR LV0
LV1
Figure:3.1.4 Determination of Interrupt Acceptance
0
VF NF CF ZF
IE IR
0
Overview
Chapter 3
Interrupts
III - 7