Overview - Panasonic MN101L Series User Manual

Chapter 5
Watchdog Timer (WDT)

5.1 Overview

The watchdog timer (WDT) generates NMI (WDIRQ) when the dedicated counter (WDT-Counter) is not cleared
during the error detect period and overflows. When two consecutive WDIRQs occur without clearing WDT-
Counter, the LSI is reset by hardware. The clock source of WDT-Counter is selected from SOSCCLK or SRC-
CLK.
Write to WDCTR
SOSCCLK
SRCCLK
WDCTR.WDCKSEL
The following table shows the relationship between CPU mode and the WDT operation when WDT is active.
WDT-Counter is initialized when the LSI is reset or is in STOP mode.
NORMAL/IDLE/SLOW/HALT
STOP
When the WDIRQ is generated, the LSI can be in unexpected state. Therefore appropriate
measures to make the LSI operate normally should be taken.
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V - 2 Overview
Reset
WDT-Counter
WDTCLK
WDCTR
Table:5.1.1 Relationship between CPU mode and WDT operation
CPU mode
Continue to count
* Count operation doesn't stop even during the mode transition.
Stop counting (The value of WDT-Counter is cleared.)
* WDIRQ is not generated in STOP mode.
R
Reset/Interrupt
control
Overflow
WDT-Counter operation
WDIRQ
LSI reset