Block Diagram - Panasonic MN101L Series User Manual

14.1.1

Block Diagram

Access size
Timing
Whole
control signal
control
Source address
Destination address
DMSRCL/M/H
Source address register
DMDSTL/M/H
Destination address register
DMCNTL/H
-1
Transfer word count register
Figure:14.1.1 Block Diagram
DMCTRnL/H (n=0,1)
DMA control register
..
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7 ( KEY interrupt )
Timer 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
Timer 4 interrupt
Timer 5 interrupt
Timer 7 interrupt
Timer 7 input capture factor
Timer 8 interrupt
Timer 8 input capture factor
Timer 9 interrupt
Timer 9 input capture factor
Serial interface 0 reception interrupt
Serial interface 0 transmission interrupt
Serial interface 0 buffer empty factor
Serial interface 1 reception interrupt
Serial interface 1 transmission interrupt
Serial interface 1 buffer empty factor
Serial interface 2 transmission complete interrupt
Serial interface 2 buffer empty factor
Serial interface 3 transmission complete interrupt
Serial interface 3 buffer empty factor
A/D conversion interrupt
Chapter 14
DMA Controller
Overview XIV - 3