Panasonic MN101L Series User Manual page 508

Chapter 17
LCD
Segment Output Latch (LCDATA0-42: 0x03E90-0x03EBA)
A 8-bit segment output latch (LCDATAn) is assigned for each segment. Each bit is read in synchronization with
the COMn timing and is output from the SEGn. LCDATAn can be read or written like RAM, and the values of
them are not valid at reset.
Figure:17.2.1 shows the relation of segment output latch and segment/common pins. these differ in each product.
Register Address
LCDATA0 0x3E90
LCDATA1 0x3E91
LCDATA2 0x3E92
LCDATA3 0x3E93
LCDATA4 0x3E94
LCDATA5 0x3E95
LCDATA6 0x3E96
LCDATA7 0x3E97
LCDATA8 0x3E98
LCDATA9 0x3E99
LCDATA10 0x3E9A
LCDATA11 0x3E9B
LCDATA12 0x3E9C
LCDATA13 0x3E9D
LCDATA14 0x3E9E
LCDATA15 0x3E9F
LCDATA16 0x3EA0
LCDATA17 0x3EA1
LCDATA18 0x3EA2
LCDATA19 0x3EA3
LCDATA20 0x3EA4
LCDATA21 0x3EA5
LCDATA22 0x3EA6
LCDATA23 0x3EA7
LCDATA24 0x3EA8
LCDATA25 0x3EA9
LCDATA26 0x3EAA
LCDATA27 0x3EAB
LCDATA28 0x3EAC
LCDATA29 0x3EAD
LCDATA30 0x3EAE
LCDATA31 0x3EAF
LCDATA32 0x3EB0
LCDATA33 0x3EB1
LCDATA34 0x3EB2
LCDATA35 0x3EB3
LCDATA36 0x3EB4
LCDATA37 0x3EB5
LCDATA38 0x3EB6
LCDATA39 0x3EB7
LCDATA40 0x3EB8
LCDATA41 0x3EB9
LCDATA42 0x3EBA
Figure:17.2.1 Correspondence of segment output latch and segment / common pins
XVII - 16 Control Registers
COM7 COM6 COM5
↓ ↓ ↓
bit7 bit6 bit5
COM4 COM3 COM2
↓ ↓ ↓
bit4 bit3 bit2
COM1 COM0
MN101L
↓ ↓
R05D
bit1 bit0
→
SEG0
→
SEG1
→
SEG2
→
SEG3
→
SEG4
→
SEG5
→
SEG6
→
SEG7
→
SEG8
→
SEG9
→
SEG10
→
SEG11
→
SEG12
→
SEG13
→
SEG14
→
SEG15
→
SEG16
→
SEG17
→
SEG18
→
SEG19
→
SEG20
→
SEG21
→
SEG22
→
SEG23
→
SEG24
→
SEG25
→
SEG26
→
SEG27
→
SEG28
→
SEG29
→
SEG30
→
SEG31
→
SEG32
→
SEG33
→
SEG34
→
SEG35
→
SEG36
→
SEG37
→
SEG38
→
SEG39
→
SEG40
→
SEG41
→
SEG42
MN101L MN101L
R04D R03D
SEG0
SEG1
SEG2
SEG3
SEG4 SEG0
SEG5 SEG1
SEG6 SEG2
SEG7 SEG3
SEG8 SEG4
SEG9 SEG5
SEG10 SEG6
SEG11
SEG12
SEG13
SEG14
SEG15 SEG7
SEG16 SEG8
SEG17 SEG9
SEG18 SEG10
SEG19 SEG11
SEG20 SEG12
SEG21 SEG13
SEG22 SEG14
SEG23 SEG15
SEG24 SEG16
SEG25 SEG17
SEG26 SEG18
SEG27 SEG19
SEG28 SEG20
SEG29
SEG30