Panasonic MN101L Series User Manual page 299

Timer 8 Mode Register 4 (TM8MD4: 0x03F9F)
bp 7
Bit name -
At reset 0
Access R
bp Bit name
7-2 -
1 T8ICT2
0 T8CAPCLR
The TM8MD4.T8CAPCLR is valid when the timer is in active. Note that the binary counter is
not cleared when capturing data while the timer is stopped.
.. ..
Set the Timer 8 mode registers while the TM8MD1.TM8EN is "0". And the TM8MD1.TM8EN
must not be changed at the same time as the other bit.
.. ..
6 5
- -
0 0
R R
Always read as 0.
Select capture trigger
0: Timer 0 interrupt
1: Timer 1 interrupt
Binary counter clear enable at capture
0: Disabled (not cleared)
1: Enabled (cleared)
4 3
- -
0 0
R R
Description
2 1
- T8ICT2 T8CAPCLR
0 0
R R/W
16-bit Timer Control Registers
Chapter 9
16-bit Timer
0
0
R/W
IX - 17