3.2.2
External Interrupt Control Register
External Interrupt 0 to 6 Control Register (IRQnICR (n = 0, 1, 2, 3, 4, 5, 6))
bp
7
Bit name
LV1
At reset
0
Access
R/W
bp
Bit name
7-6
LV1-0
5
REDG
4
-
3
Reserved
2
-
1
IE
0
IR
External Interrupt 7 Control Register (IRQ7ICR)
bp
7
Bit name
LV1
At reset
0
Access
R/W
bp
Bit name
7-6
LV1-0
5-4
-
3
Reserved
2
-
1
IE
0
IR
6
5
LV0
REDG
0
0
R/W
R/W
Interrupt level
- Set interrupt level from 0 to 3.
Interrupt trigger edge
0: Falling edge
1: Rising edge
Always read as "0".
Must be set to "0".
Always read as "0".
Interrupt enable control
0: Disable
1: Enable
Interrupt request detection
0: Not detected
1: Detected
6
5
LV0
-
0
0
R/W
R/W
Interrupt level
- Set interrupt level from 0 to 3.
Always read as "0".
Must be set to "0".
Always read as "0".
Interrupt enable control
0: Disable
1: Enable
Interrupt request detection
0: Not detected
1: Detected
4
3
-
Reserved
0
0
R
R/W
R
Description
4
3
-
Reserved
0
0
R
R/W
R
Description
2
1
0
-
IE
IR
0
0
0
R/W
R/W
2
1
0
-
IE
IR
0
0
0
R/W
R/W
Control Registers
Chapter 3
Interrupts
III - 23