10.2.4
Timer Mode Register
This is a readable/writable register that controls the timer 6 and the time base timer.
Timer 6 Mode Register (TM6MD:0x03F7A)
bp
7
Bit name
TM6CLRS
At reset
0
Access
R/W
bp
Bit name
7
TM6CLRS
6 to 4
TM6IR2 to 0
TM6CK3 to
3 to 1
1
0
TM6CK0
6
5
TM6IR2
TM6IR1
0
0
R/W
R/W
Timer 6 binary counter clear select
0: Enable the initialization of TM6BC when TM6OC is written.
1: Disable the initialization of TM6BC when TM6OC is written.
* When TM6CLRS = 0, PERI0IRQ1 is disabled. When TM6CLRS = 1, PERI0IRQ1
is enabled.
Interrupt cycle of time base timer select
000: Time base selection clock × 1/2
001: Time base selection clock × 1/2
010: Time base selection clock × 1/2
011: Time base selection clock × 1/2
100: Time base selection clock × 1/2
101: Time base selection clock × 1/2
110: Time base selection clock × 1/2
111: Time base selection clock × 1/2
Timer 6 clock source select
000: HCLK
001: SYSCLK
010: SCLK
011: Setting prohibited
100: Time base selection clock × 1/2
101: Setting prohibited
110: Time base selection clock × 1/2
111: Setting prohibited
Time base timer clock source select
0: HCLK
1: SCLK
4
3
TM6IR0
TM6CK3
TM6CK2
0
0
R/W
R/W
Description
7
8
9
10
12
13
14
15
13
7
General-Purpose Time Base/Free-Running Timer
2
1
TM6CK1
TM6ICK0
0
0
R/W
R/W
Control Registers
Chapter 10
0
0
R/W
X - 7