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Panasonic MN101L Series User Manual

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Cover
MICROCOMPUTER
MN101LR05D/04D/03D/02D
LSI User's Manual
MN101L
Pub.No. 21705-015E

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Table of Contents
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  Summary of Contents for Panasonic MN101L Series

  • Page 1 Cover MN101L MICROCOMPUTER MN101LR05D/04D/03D/02D LSI User’s Manual Pub.No. 21705-015E...
  • Page 3 (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company.
  • Page 4 A b o u t T h i s M a n u a l Objective The primary objective of this LSI manual is to describe the features of this product including an overview, CPU basic functions, interrupt, port, timer, serial interface, and other peripheral hardware functions.
  • Page 5 About Register Table How to read the register table in each chapter is shown below. Register name Register symbol Register address Chapter15 8-bit Timer Access size 15.2.3 Timer Mode Registers Values of the timer mode register contorl the operation, initialization, and clock source selection of each timer.
  • Page 6 3.The chapter number and chapter title are located at the top corner of each page, and the section titles are located at the bottom corner of each page. Related Manuals Note that the following documents related to MN101L series are available. • "MN101L Series Instruction Manual" <Describes the instruction set.>...
  • Page 7 Chapter Table Contents Chapter 1 Overview Chapter 2 CPU Basics Chapter 3 Interrupts Chapter 4 Clock/Mode/Voltage Control Chapter 5 Watchdog Timer (WDT) Chapter 6 Power Supply Voltage Detection Chapter 7 I/O Port Chapter 8 8-bit Timer Chapter 9 16-bit Timer Chapter 10 General-Purpose Time Base/Free-Running Timer Chapter 11 RTC Time Base Timer (RTC-TBT) Chapter 12 Real Time Clock (RTC)
  • Page 9 Chapter 13 Serial Interface Chapter 14 DMA Controller Chapter 15 Buzzer Chapter 16 A/D Converter (ADC) Chapter 17 LCD Chapter 18 ReRAM Chapter 19 On-Board Debugger Chapter 20 Appendix...
  • Page 11 Contents Contents...
  • Page 12: Table Of Contents

    Contents Chapter 1 Overview........................ I-1 1.1 Hardware Features..........................I-2 1.2 Comparison of Product Specification....................I-7 1.3 Pin Description ..........................I-11 1.3.1 Pin Configuration ........................ I-11 1.3.2 Pin Description........................I-15 1.4 Electrical Characteristics ........................I-20 1.4.1 Absolute Maximum Ratings ....................I-20 1.4.2 Operating Condition......................
  • Page 13 2.3.1 Overview..........................II-17 2.3.2 Extended Calculation Control Register ................II-18 2.4 Extended Calculation Instruction ..................... II-20 2.4.1 About Extended Calculation Instruction................II-20 2.4.2 MULWU 16-bit x 16-bit multiplication (unsigned) ............II-21 2.4.3 MULW 16-bit x 16-bit multiplication (signed) ..............II-22 2.4.4 DIVWU 32-bit / 16-bit division (unsigned) ..............
  • Page 14 4.2.1 NORMAL Mode....................... IV-15 4.2.2 SLOW Mode........................IV-17 4.2.3 STANDBY Mode ......................IV-19 4.2.4 Note for Transition to STANDBY Mode ................. IV-23 4.3 Voltage Control ..........................IV-26 4.3.1 Overview........................... IV-26 4.3.2 Register List ........................IV-26 4.3.3 Power Supply Control Register ..................IV-27 4.3.4 Operation ..........................
  • Page 15 7.2.6 Port n N-ch Drive Strength Selection Registers ............. VII-22 7.2.7 8-bit Timer output control Register ................VII-25 7.2.8 8-bit Timer input/output pins selection Register ............VII-26 7.2.9 16-bit Timer output control Register ................VII-27 7.2.10 16-bit Timer input/output pin selection Register............VII-28 7.2.11 Clock output / Clock output pin control Register ............
  • Page 16 8.3 8-bit Timer ........................... VIII-15 8.3.1 Operation ........................VIII-15 8.3.2 Setup Example ....................... VIII-19 8.4 8-bit Event Count ......................... VIII-20 8.4.1 Operation ........................VIII-20 8.4.2 8-bit Event Count Setup Example ................. VIII-22 8.5 8-bit Timer Pulse Output......................VIII-23 8.5.1 Operation ........................VIII-23 8.5.2 Setup Example .......................
  • Page 17 9.7.1 Operation .......................... IX-35 9.7.2 Setup Example ........................IX-38 9.8 16-bit Timer Capture Function......................IX-39 9.8.1 Operation .......................... IX-39 9.8.2 Setup Example ........................IX-46 9.9 16-bit Standard IGBT Output (with Variable Duty) ............... IX-47 9.9.1 Operation .......................... IX-47 9.9.2 Setup Example ........................IX-50 9.10 16-bit High-Precision IGBT Output (with Variable Period/Duty) ..........
  • Page 18 11.3 RTC-TBT Operation ........................XI-9 11.3.1 RTC-TBT Operation......................XI-9 11.3.2 Operation Setting Example..................... XI-10 Chapter 12 Real Time Clock (RTC) ................... XII-1 12.1 Overview ............................XII-2 12.2 Control Registers........................... XII-3 12.2.1 RTC Control Register ..................... XII-4 12.2.2 Alarm 0 Interrupt Registers .................... XII-5 12.2.3 Alarm 1 Interrupt Registers ....................
  • Page 19 13.4.2 Operation ........................XIII-48 13.4.3 Timing.......................... XIII-52 13.4.4 Setting procedure ......................XIII-54 13.5 IIC Communication........................XIII-56 13.5.1 Format.......................... XIII-56 13.5.2 Operation ........................XIII-57 13.5.3 Timing.......................... XIII-62 13.5.4 Setup Example ......................XIII-68 Chapter 14 DMA Controller ..................... XIV-1 14.1 Overview ............................XIV-2 14.1.1 Block Diagram .......................
  • Page 20 16.3 Operation............................XVI-8 16.3.1 Setup ..........................XVI-10 16.3.2 Setup Procedure ......................XVI-12 16.3.3 Cautions ........................XVI-13 Chapter 17 LCD ....................... XVII-1 17.1 Overview ............................. XVII-2 17.1.1 LCD Driver Circuit Block Diagram ................XVII-3 17.2 Control Registers......................... XVII-4 17.2.1 LCD Mode Control Registers ..................XVII-5 17.2.2 LCD Port Control Registers..................
  • Page 21 Chapter 19 On-Board Debugger ..................XIX-1 19.1 Overview ............................XIX-2 19.2 List of on-board debugging functions ..................XIX-3 Chapter 20 Appendix ......................XX-1 20.1 Symbol Definitions ........................XX-2 20.2 Instruction set ..........................XX-5 20.3 Instruction map..........................XX-11 <Contents - 10>...
  • Page 22 <Contents - 11>...
  • Page 23: Chapter 1 Overview

    Chapter 1 Overview...
  • Page 24: Hardware Features

    Chapter 1 Overview 1.1 Hardware Features MN101LR05D is described in this LSI user's manual. For MN101LR04D, MN101LR03D and MN101LR02D, refer to [1.2 Comparison of Product Specification] and [1.3.1 Pin Configuration]. Features In this document, the divided clock and the frequency of it are described as follows: Divided clock: Clock name/n (n: division ratio) Frequency clock name...
  • Page 25 Chapter 1 Overview • Interrupt Circuit - 31 internal interrupts (except for NMI) - 8 external interrupts * MN101LR02D: - 29 internal interrupts (except for NMI) - 3 external interrupts • DMA (1 channel) - Data transfer size : 8 bits/16 bits - Maximum transfer counts: 1023 - Activation trigger : external interrupts / internal interrupts / software (setting the DMA start bit)
  • Page 26 Chapter 1 Overview <Timer 6> - Function : One-minute timer can be generated in combination with a time base timer. - Clock Source : HCLK, HCLK/2 , HCLK/2 , SYSCLK, SCLK, SCLK/2 , SCLK/2 <Time Base Timer> - Function : An interrupt can be generated at a given set time. - Clock Source : HCLK and SCLK - Interrupt generation cycle: 2 (N = 7, 8, 9, 10, 12, 13, 14, 15)
  • Page 27 Chapter 1 Overview * MN101LR03D Serial Interface 3: Clock synchronous serial cannot be used 3 and 4-wire communication, and is not compatible with SPI. (Chip select pin is not assigned.) * MN101LR02D Serial Interface 1: Not implemented Serial Interface 3: Clock synchronous serial cannot be used 4-wire communication, and is not compatible with SPI.
  • Page 28 - MN101LR03D: TQFP048-P-0707 ( 7 mm square, 0.5 mm pitch, halogen free) - MN101LR02D: HQFN032-A-0505 ( 5 mm square, 0.5 mm pitch, halogen free) Panasonic "halogen free" semiconductor products refer to the products made of molding resin and interposer which conform to the following standards.
  • Page 29: Comparison Of Product Specification

    Chapter 1 Overview 1.2 Comparison of Product Specification Table:1.2.1 Functions Function Specification MN101LR05D MN101LR04D MN101LR03D MN101LR02D Port I/O port 69 pins 53 pins 37 pins 22 pins N-channel transistor 55 pins 41 pins 27 pins 19 pins drive strength Interrupt Internal interrupt External interrupt (7:IRQ0-6, 1:KEY0-7)
  • Page 30 Chapter 1 Overview Table:1.2.2 Functions of I/O Port MN101LR05D MN101LR04D MN101LR03D MN101LR02D Port Port0 √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ Port1 √ √ √ √ √ √ √...
  • Page 31 Chapter 1 Overview Table:1.2.4 Pin Functions Pin No. Power supply Port External Timer Serial Buzzer /Oscillations interrupt interface /Clock output MN101 MN101 MN101 MN101 /Reset /KEY interrupt LR05D LR04D LR03D LR03D /Mode control NATRON NRST OSC1 IRQ2A OSC2 IRQ3A TM9IOC TM4IOB TM2IOB/TM8IOC BUZB...
  • Page 32 Chapter 1 Overview Pin No. Power supply Port External Timer Serial Buzzer /Oscillations interrupt interface /Clock output MN101 MN101 MN101 MN101 /Reset /KEY interrupt LR05D LR04D LR03D LR03D /Mode control SBCS2A SBI1B/RXD1B SBO1B/TXD1B SBT1B SBCS1B SBI3B SBO3B/SDA3B SBT3B/SCL3B KEY0B SBCS3B KEY1B TM1IOA KEY2B...
  • Page 33: Pin Description

    Chapter 1 Overview 1.3 Pin Description 1.3.1 Pin Configuration P63/SEG8 /IRQ3B P62/SEG9 /IRQ2B P61/SEG10/IRQ1B NATRON P60/SEG11/IRQ0B P27/NRST P57/SEG12/TM8IOA /KEY3B/CLKOUTB IRQ2A/ OSC1/P80 P56/SEG13/TM3IOA /KEY2B P55/SEG14/TM1IOA /KEY1B IRQ3A/ OSC2/P81 TM9IOC/P00 P54/SEG15/SBCS3B/KEY0B MN101LR05D P53/SEG16/SBT3B /SCL3B TM4IOB/P01 P52/SEG17/SBO3B /SDA3B TM8IOC/TM2IOB/ BUZB/P02 80 pin P51/SEG18/SBI3B TM7IOC/TM0IOB/ NBUZB/P03 (Top View) TM7IOA/ SBO3A/ SDA3A/P04...
  • Page 34 Chapter 1 Overview P63/SEG4 /IRQ3B P62/SEG5 /IRQ2B P61/SEG6 /IRQ1B NATRON P60/SEG7 /IRQ0B P27/NRST P57/SEG8 /TM8IOA/KEY3B/CLKOUTB P56/SEG9 /TM3IOA/KEY2B IRQ2A/ OSC1/P80 IRQ3A/ OSC2/P81 P55/SEG10/TM1IOA/KEY1B MN101LR04D TM8IOC/TM2IOB/ BUZB/P02 64 pin TM7IOC/TM0IOB/ NBUZB/P03 P47/SEG12/SBT1B (Top View) TM7IOA/ SBO3A/ SDA3A/P04 P46/SEG13/SBO1B /TXD1B CLKOUTA/TM2IOA/TM0IOA/ SBT3A/ SCL3A/P05 P45/SEG14/SBI1B /RXD1B P44/SEG15/SBCS2A TM8IOB/...
  • Page 35 Chapter 1 Overview P63/SEG0 /IRQ3B P62/SEG1 /IRQ2B P61/SEG2 /IRQ1B NATRON P60/SEG3 /IRQ0B P27/NRST P57/SEG4 /TM8IOA/KEY3B/CLKOUTB MN101LR03D IRQ2A/ OSC1/P80 P56/SEG5 /TM3IOA/KEY2B 48 pin IRQ3A/ OSC2/P81 P55/SEG6 /TM1IOA/KEY1B TM7IOA/SBO3A/SDA3A/P04 P44/SEG7 /SBCS2A (Top View) CLKOUTA/TM2IOA/TM0IOA/ SBT3A/SCL3A/P05 P43/SEG8 /SBT2A /SCL2A IRQ4C/ KEY2A/ AN2/P12 P42/SEG9 /SBO2A /SDA2A IRQ5C/ KEY3A/ AN3/P13 P41/SEG10/SBI2A...
  • Page 36 Chapter 1 Overview P57/TM8IOA/KEY3B/CLKOUTB P56/TM3IOA/KEY2B NATRON P55/TM1IOA/KEY1B MN101LR02D P27/NRST P44/SBCS2A 32 pin TM7IOA/SBO3A/SDA3A/P04 P43/SBT2A /SCL2A (Top View) CLKOUTA/TM2IOA/TM0IOA/SBT3A/SCL3A/P05 P42/SBO2A /SDA2A TM8IOB/ SBI3A/P06 P41/SBI2A IRQ5C/KEY3A/ AN3/P13 P40/SBCS0B Figure:1.3.4 MN101LR02D Pin Configuration I - 14 Pin Description...
  • Page 37: Pin Description

    Chapter 1 Overview 1.3.2 Pin Description Table:1.3.1 Power Supply/Oscillation/Reset/Mode Pin Input/ Pin name Description Output VDD30 Power supply pin Connect the capacitor of 1 µF or more between VDD30 and VSS. Apply 0 V to VSS. VDD18 Internal power output pin Connect the capacitor of 1 µF between VDD18 and VSS to stable V DD18 Connect the bypass capacitor of 0.1 µF between VDD18 and VSS.
  • Page 38 Chapter 1 Overview Table:1.3.2 General-purpose Port Function Pin Output Input/ Function drive strength Description name Output selectable TM9IOC Port 0 -At each port, the I/O direction and the pull-up resistor TM4IOB connection is controlled individually. -At LSI reset, each pin is set to input mode and the pull-up TM2IOB/TM8IOC/BUZB resistor is not connected.
  • Page 39 Chapter 1 Overview Output Input/ Function drive strength Description name Output selectable SEG27/SBCS0B Port 4 -At each port, the I/O direction and the pull-up resistor SEG26/SBI2A connection is controlled individually. -At LSI reset, each pin is set to input mode and the pull-up SEG25/SBO2A/SDA2A resistor is not connected.
  • Page 40 Chapter 1 Overview Table:1.3.3 Special Function Pin Input/ Pin name Description Output SBI0A(RXD0A) Input Serial data input pins SBI0B(RXD0B) -Pull-up resistor can be added by setting PnPLUP. SBI1A(RXD1A) -Select the input mode by setting PnDIR. SBI1B(RXD1B) -Select the serial data input by setting SCnMD1.SCnSBIS. (n = 0,1,2,3) SBI2A SBI2B SBI3A...
  • Page 41 Chapter 1 Overview Input/ Pin name Description Output SEGn (n = 0 to 42) Output LCD segment output pins -Select the segment output pin with LCCTRn. BUZA/BUZB Output Buzzer output pin -Select the buzzer output pin with BUZCNT. NBUZA/NBUZB Output Inverted Buzzer output pin -Select the inverted buzzer output pin with BUZCNT.
  • Page 42: Electrical Characteristics

    Chapter 1 Overview 1.4 Electrical Characteristics 1.4.1 Absolute Maximum Ratings = 0 V A. Absolute Maximum Ratings *2 *3 Parameter Symbol Rating Unit A1 Supply voltage -0.3 to +4.6 DD30 -0.3 to V + 0.3 (up to 4.6) A2 Input pin voltage DD30 -0.3 to V + 0.3 (up to 4.6)
  • Page 43: Operating Condition

    Chapter 1 Overview 1.4.2 Operating Condition = 0 V B. Operating Condition Ta = -40 °C to +85 °C Limits Parameter Symbol Condition Unit Supply voltage *5 ≤ 10.0 MHz SYSCLK ≤ 1.0 MHz *6 Supply voltage SYSCLK ≤ 40 kHz *7 *9 SYSCLK RAM retention At STOP mode *9...
  • Page 44 Chapter 1 Overview to 3.6 V, V = 0 V DD30 RSTL = 1.1 V at auto reset function RSTL Ta = -40 °C to +85 °C Limits Parameter Symbol Condition Unit = 8/10 MHz HRCCLK -1.5 Ta = 0 °C to +50 °C Temperature/Voltage dependence = 8/10 MHz...
  • Page 45 Chapter 1 Overview = 1.8 V to 3.6 V, V = 0 V DD30 = 1.1 V at auto reset function RSTL Ta = -40 °C to +85 °C Limits Parameter Symbol Condition Unit External clock input 1 OSC1 (OSC2 is open.) (MN101LR02D is not applicable.) B18 Clock frequency 10.0 HOSCCLK...
  • Page 46: Dc Characteristics

    Chapter 1 Overview 1.4.3 DC Characteristics = 0 V C. DC Characteristics Ta = -40 °C to +85 °C Limits Parameter Symbol Condition Unit Supply current *12 = 10 MHz, HOSCCLK = 3.0 V, V = 1.8 V DD30 DD18 SYSCLK HOSCCLK = 10 MHz...
  • Page 47 Chapter 1 Overview = 0 V C. DC Characteristics Ta = -40 °C to +85 °C Limits Parameter Symbol Condition Unit HALT0 mode = 8 MHz 0.24 0.33 HRCCLK = 3.0 V, V = 1.1 V DD30 DD18 HALT2 mode = 32.768 kHz SOSCCLK = 3.0 V, V...
  • Page 48 Chapter 1 Overview to 3.6 V, V = 0 V DD30 RSTL = 1.1 V at auto reset function RSTL Ta = -40 °C to +85 °C Limits Parameter Symbol Condition Unit Input pin 1 NATRON 0.8V C15 High-level input voltage DD30 DD30 0.2V...
  • Page 49 Chapter 1 Overview to 3.6 V, V = 0 V DD30 RSTL = 1.1 V at auto reset function RSTL Ta = -40 °C to +85 °C Limits Parameter Symbol Condition Unit Display output pin 1 COM0 to COM7 (at V output) (MN101LR02D is not applicable.) = 3.0 V Potential difference of...
  • Page 50: A/D Converter Characteristics

    Chapter 1 Overview 1.4.4 A/D Converter Characteristics = 3.0 V V = 0 V DD30 D. A/D Converter characteristics *13 Ta = -40 °C to +85 °C Limits Parameter Symbol Condition Unit Resolution Bits Nonlinearity error ±4 Differential non-linearity ±3 = 3.0 V, V = 0 V DD30...
  • Page 51: Reset/Power Supply Detection Characteristics

    Chapter 1 Overview 1.4.5 Reset/Power supply Detection Characteristics to 3.6 V, V = 0 V DD30 RSTL E. Reset/Power supply Detection = 1.1 V at auto reset function RSTL Characteristics Ta = -40 °C to +85 °C Limits Parameter Symbol Condition Unit Reset...
  • Page 52: Reram Program Condition

    Chapter 1 Overview 1.4.6 ReRAM Program Condition = 1.8 V to 3.6 V, V = 0 V DD30 F. ReRAM Program Condition Ta = -40 °C to +85 °C Limits Parameter Condition Unit Symbol Supply voltage DDEW for programming Program area 1000 Guaranteed number of time...
  • Page 53: Package Dimension

    Chapter 1 Overview 1.5 Package Dimension Package code: TQFP080-P-1212 Unit: mm Figure:1.5.1 80-pin TQFP Package Dimension Package Dimension I - 31...
  • Page 54 Chapter 1 Overview Package code: TQFP064-P-1010 Unit: mm Figure:1.5.2 64-pin TQFP Package Dimension I - 32 Package Dimension...
  • Page 55 Chapter 1 Overview Package code: TQFP048-P-0707 Unit: mm Figure:1.5.3 48-pin TQFP Package Dimension Package Dimension I - 33...
  • Page 56 Chapter 1 Overview Package code: HQFN032-A-0505 Unit: mm Figure:1.5.4 32-pin HQFN Package Dimension This package dimension is subject to change. Before using this product, obtain product spec- ifications from our sales offices. I - 34 Package Dimension...
  • Page 57: Cautions For Circuit Setup

    Chapter 1 Overview 1.6 Cautions for Circuit Setup 1.6.1 Usage Notes Connection of VDD30 and VSS VDD30 and VSS pins should be connected directly to the power supply and ground respectively. Do not mount the LSI on the printed circuit board in the wrong direction in order not to destroy it because of the meltdown of wiring due to large current etc..
  • Page 58: Unused Pins

    Chapter 1 Overview 1.6.2 Unused Pins Unused Pin (only for output) Unconnect the unused output pin. Output OPEN Figure:1.6.1 Unused Pin (only for output) Unused Pin (only for input) Pull-up (or down) the unused input pins with the resistor, the value of which is typically between 10 kΩ and 100 kΩ.
  • Page 59 Chapter 1 Overview Input and Output pin When the direction of unused I/O pin is set to input, pull-up or down the pin with the resistor, the value of which is typically between 10 kΩ and 100 kΩ. When the unused I/O pin is configured as output, it should be left unconnected. Output Control Output Control Pull-up...
  • Page 60: Power Supply

    Chapter 1 Overview 1.6.3 Power Supply Relation between Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on. Failure to the sequence can cause the destruc- tion of the LSI because of the large current. Input protection resistance Input...
  • Page 61: Power Supply Circuit

    Chapter 1 Overview 1.6.4 Power Supply Circuit Cautions for Power Circuit Design The MOS logic such a microcomputer is high-speed and high-density. So, the power circuit should be designed, taking into consideration of AC line noise, ripple caused by LED driver. An example of a circuit with V (emitter follower type) is shown below.
  • Page 62 Chapter 1 Overview I - 40 Cautions for Circuit Setup...
  • Page 63: Chapter 2 Cpu

    II.. Chapter 2 CPU...
  • Page 64: Overview

    Chapter 2 2.1 Overview The AM13L core (CPU), upward compatible with MN101C/E core, has the enhanced calculation units, shortens the interrupt latency and has the 16-bit bus architecture to access instruction/data memory and peripheral circuits. The CPU executes most of instructions in one clock cycle, and achieves high performance comparable to a 16-bit microcomputers.
  • Page 65: Cpu Control Registers

    Chapter 2 2.1.1 CPU Control Registers The LSI allocates the peripheral circuit registers in memory space ("0x03000" to "0x03FFF"). CPU control registers are also allocated in the space. Table:2.1.2 CPU Control Registers Symbol Address Register name Pages CPUM 0x03F00 CPU mode control register IV-4 MEMCTR 0x03F01...
  • Page 66: Stack Pointer (Sp

    Chapter 2 2.1.4 Stack Pointer (SP) This register shows the top address of the stack. The initial value of SP is "0x0100". Stack Pointer Figure:2.1.3 Stack Pointer 2.1.5 Program Counter (PC) This register gives the address of the currently executed instruction, and the LSB shows the half-byte(4-bit) infor- mation.
  • Page 67: Processor Status Word (Psw

    Chapter 2 2.1.6 Processor Status Word (PSW) PSW is pushed onto the stack at interrupt occurrence and popped at returning from the interrupt service routine automatically. Processor Status Word (PSW) Bit name IM1-0 At reset Access Bit name Description Bank function control 0: Bank addressing is enabled.
  • Page 68 Chapter 2 Interrupt Mask Level (IM1 to IM0) Interrupt mask level (IM1, IM0) controls the accept level of maskable interrupt. Maskable Interrupt Enable (MIE) When MIE is set to '1', the maskable interrupt which is not masked with IM1, IM0 is accepted and the value of MEMCTR.MIESET is load into MIE.
  • Page 69: Address Space

    Chapter 2 2.1.7 Address Space Figure:2.1.5 shows the address space in CPU. The CPU has 12 KB of RAM area (Max.) and 112 KB of ROM area (Max.). This LSI has 4 KB of RAM and 64 KB of ROM. The instruction access can be used as linear address space except Special function register space.
  • Page 70 Chapter 2 The value of internal RAM is uncertain when power is applied to it. It needs to be initialized before using. There's no guarantee of proper operation when an access is executed to the non-imple- mented space where a memory (ROM / RAM), a special function register, or others are not arranged.
  • Page 71: Addressing Modes

    "MOVW An, (HA)". Combining handy addressing with absolute addressing reduces code size. For transfer data between memory, 8 addressing modes; register indirect, register relative indirect, stack relative indirect, absolute, RAM short, I/O short, handy can be used. Refer to [MN101L Series Instruction Manual]. Overview...
  • Page 72 Chapter 2 Higher 4-bit of data access Addressing Modes Effective address Description address when bank addre- ssing is enabled. Dn / DWn Directly specifies the register. Only internal registers can Register direct An / SP be specified. imm4 / imm8 Directly specifies the operand or mask value appended Immediate imm16...
  • Page 73: Bank Function

    Chapter 2 2.1.9 Bank Function Bank function allows the data access in the area over the address of 0x10000. Bank function can be used by setting the proper bank area to the bank register for source address (SBNKR) and the bank register for destination address (DBNKR). At reset, the two registers shows indicate bank 0. Bank func- tion is valid after setting PSW.BKD to "0".
  • Page 74 Chapter 2 Bank Register for Source Address (SBNKR: 0x03F0A) The SBNKR is used to specify bank area for loading instruction. Once this register is specified, bank control is valid for all addressing modes except I/O short instruction and stack relative indirect instruction. Refer to [2.1.8 Addressing Modes] Bit name Reserved...
  • Page 75: Special Function Register

    Chapter 2 2.1.10 Special Function Register This LSI locates the special function registers (I/O spaces) at the addresses 0x03C00 to 0x03FFF in memory space. The special function registers of this LSI are located as shown below. The addresses 0x03000 to 0x03BFF are reserved. Table:2.1.5 MN101LR05D Register Map 0x03C0X Reserved...
  • Page 76: Bus Interface

    Chapter 2 2.2 Bus Interface 2.2.1 Bus Controller The CPU provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads and thus realize faster operation. There are three buses: ROM bus, RAM bus, and peripheral extension bus (C-BUS). They connect to the internal ROM, internal RAM, internal peripheral circuits respectively.
  • Page 77: Access Cycle

    Chapter 2 2.2.2 Access Cycle Table:2.2.1 shows the wait cycle and the access cycle of ROM bus, RAM bus, peripheral extension bus (C-BUS). Table:2.2.1 Bus access cycle Type of bus Access address Wait cycle Access cycle 0x04000 to 0x040FF 0x04900 to 0x13FFF ROM bus 0x04100 to 0x048FF RAM bus...
  • Page 78: Control Registers

    Chapter 2 2.2.3 Control Registers The memory control register (MEMCTR) controls bus interface function. Memory Control Register (MEMCTR: 0x03F01) Bit name IVBM Reserved IRWE MIESET At reset Access Bit name Description Always read as 0. Base address specification for interrupt vector table IVBM 0: Interrupt vector base = 0x04000 1: Interrupt vector base = 0x00100...
  • Page 79: Extended Calculation Function

    Chapter 2 2.3 Extended Calculation Function 2.3.1 Overview The LSI contains the following calculator functions. Table:2.3.1 List of Extended Calculation Functions PSW bit Execution change Calculation Instruction Operation cycle VF NF CF ZF 16-bit × 16-bit DW0 * DW1 → {DW1, DW0} MOV 1, (0x3F07) multiplication Extended calculation...
  • Page 80: Extended Calculation Control Register

    Chapter 2 2.3.2 Extended Calculation Control Register Extended calculation can be executed by setting the extended calculation control bit. Extended Calculation Control Register (AUCTR: 0x03F07) Bit name AUBCDSUBC AUBCDSUB AUBCDADDC AUBCDADD Reserved AUDIVU AUMUL AUMULU At reset Access Bit name Description BCD subtraction with carry AUBCDSUBC...
  • Page 81 Chapter 2 Each bit is set to "0" by hardware, when calculation is finished. Do not set several bits simultaneously. Do not read AUCTR. (Do not access AUCTR by the bit manipulation instructions.) By writing the following C language, you can avoid generation of data load instructions and bit manipulation instructions.
  • Page 82: Extended Calculation Instruction

    Chapter 2 2.4 Extended Calculation Instruction 2.4.1 About Extended Calculation Instruction About this Table Changes of VF/NF/CF/ZF of PSW with change with no change in always 0 in always 1 Instruction format Operation Operation descrition Size, Cycles, Codes Size, Cycles, Codes(the shortest Bit Changes Size, Cycles, Codes...
  • Page 83: Mulwu 16-Bit X 16-Bit Multiplication (Unsigned

    3. The value of the unsigned 16-bit of DW0 register is multiplied by the unsigned 16-bit of DW1 register. Then the upper 16-bit of the result (32-bit) is stored in DW1 register and the lower 16-bit is stored in DW0 register. This extended calculation instruction is generated by the compiler for MN101L series by appointing an option (-mmuldivw).
  • Page 84: Mulw 16-Bit X 16-Bit Multiplication (Signed

    16-bit of the results (32-bit) is stored in DW1 register and the lower 16-bit register is stored in DW0 reg- ister. This extended calculation instruction is generated by the compiler for MN101L series by appointing an option (-mmuldivw). When this extended calculation instruction is executed, the handy address (HA) is updated in "0x03F07"...
  • Page 85: Divwu 32-Bit / 16-Bit Division (Unsigned

    16-bit) is divided by the value of the unsigned 16-bit of A0 register. Then the quotient 16-bit of the result is stored in DW0 register and the remainder 16-bit of the result is stored in DW1 register. This extended calculation instruction is generated by the compiler for MN101L series by appointing an option (-mmuldivw).
  • Page 86: Bcdadd Bcd Addition (Without Carry

    Chapter 2 2.4.5 BCDADD BCD addition (without carry) BCDADD (MOV 0x10, (0x03F07)) D0 (BCD) + D1 (BCD) → D0 (BCD) Operation Adds the D0 register (8-bit) and the D1 register (8-bit) as the value of each two-digit BCD, and stores the result (8-bit) after the BCD correction to the D0 register. Bit Changes Size, Cycles, Codes VF: 0...
  • Page 87: Bcdaddc Bcd Addition (With Carry

    Chapter 2 2.4.6 BCDADDC BCD addition (with carry) BCDADDC (MOV 0x20, (0x03F07)) D0 (BCD) + D1 (BCD) + PSW.CF → D0 (BCD) Operation Adds the D0 register (8-bit) and the D1 register (8-bit) as the value of each two-digit BCD and PSW.CF, and stores the result (8-bit) after the BCD correction to the D0 reg- ister.
  • Page 88: Bcdsub Bcd Subtraction (Without Carry

    Chapter 2 2.4.7 BCDSUB BCD subtraction (without carry) BCDSUB (MOV 0x40, (0x03F07)) D0 (BCD) - D1 (BCD) → D0 (BCD) Operation Subtracts the D0 register (8-bit) and the D1 register (8-bit) as the value of each two- digit BCD, and stores the result (8-bit) after the BCD correction to the D0 register. Bit Changes Size, Cycles, Codes VF: 0...
  • Page 89: Bcdsubc Bcd Subtraction (With Carry

    Chapter 2 2.4.8 BCDSUBC BCD subtraction (with carry) BCDSUBC (MOV 0x80, (0x03F07)) D0 (BCD) - D1 (BCD) - PSW.CF → D0 (BCD) Operation Subtracts the D0 register (8-bit) and the D1 register (8-bit) as the value of each two- digit BCD and subtracts the PSW.CF further, and stores the result (8-bit) after the BCD correction to the D0 register.
  • Page 90: Reset

    Chapter 2 2.5 Reset 2.5.1 Reset function This LSI has the following four types of reset factors. • Power-on reset (when the NATRON pin is tied to "Low".) • Power-down reset (when the NATRON pin is tied to "Low".) • Low level signal input to NRST pin. •...
  • Page 91: Reset Sequence

    Chapter 2 2.5.2 Reset sequence 1. When NRST pin comes to high level from low level, the internal binary counter starts counting. The time range after the counter started counting before the overflow of it occurs is called the "oscillation sta- bilization wait time".
  • Page 92: Oscillation Stabilization Wait Time

    Chapter 2 2.5.3 Oscillation Stabilization Wait Time The oscillation stabilization wait time is different in the following situations. 1. When the LSI starts up from reset, the wait time is equal to the initial value of the DLYCTR. 2. When transiting from SLOW mode to NORMAL mode, or recovering from HALT2/STOP0 mode, the wait time can be varied with the DLYCTR.The value of the DLYCTR must be determined for stabilizing the HCLK oscillation.
  • Page 93 Chapter 2 Oscillation Stabilization Wait Time Control Register (DLYCTR: 0x03F03) Bit name DLY3-0 At reset Access Bit name Description Always read as 0. Oscillation stabilization wait cycle selection × (1/f 0000: 2 OSCSTBCLK × (1/f 0001: 2 OSCSTBCLK × (1/f 0010: 2 OSCSTBCLK ×...
  • Page 94 Chapter 2 II - 32 Reset...
  • Page 95: Chapter 3 Interrupts

    III.. Chapter 3 Interrupts...
  • Page 96: Overview

    Chapter 3 Interrupts 3.1 Overview The LSI provides vectored interrupt services, consisting of LSI-reset, Non-Maskable Interrupts (NMI), and Maskable Interrupts. The transition time from the interrupt occurrence to interrupt handler is 6 SYSCLK cycles at a minimum, and the same amount of time is needed at a minimum when returning from the interrupt handler. Each interrupt has a interrupt control register (hereinafter described as "xICR", and "x"...
  • Page 97: Block Diagram

    Chapter 3 Interrupts 3.1.1 Block Diagram level Interrupt deter- mination Vector 1 IRQNMI IRQLVL NMICR Undefined WDTOVF Instruction Vector 2 LV1-0 IRQ0ICR External interrupt 0 Vector N Group-0 interrupt Vector 29 PERI0ICR LV1-0 Vector 30 Group-1 interrupt PERI1ICR LV1-0 Figure:3.1.1 Interrupt Block Diagram Overview III - 3...
  • Page 98: Operation

    Chapter 3 Interrupts 3.1.2 Operation Interrupt Processing Sequence Figure:3.1.2 shows the flow of a interrupt processing. When an interrupt occurs and is accepted, the Program Counter (PC), Processor Status Word (PSW) and Handy Address (HA) are saved onto the stack by hardware, and CPU jumps to the address specified by the corresponding interrupt vector.
  • Page 99 Chapter 3 Interrupts Interrupt Vector Table Table:3.1.1 shows the interrupt vector address and the interrupt control registers. Table:3.1.1 Interrupt Vector Table Vector Vector address Interrupt factor Interrupt control register number IVBM = 0 IVBM = 1 Name Address 0x04000 LSI Reset 0x04004 0x00104 Non-maskable interrupt...
  • Page 100 Chapter 3 Interrupts Interrupt Level and Priority The LSI provides three levels of interrupt priority, and the lower vector number has priority when several inter- rupts with the same interrupt priority level occur. (For example, when the vector 3 and the vector 4 are set to the priority of level 1 and those interrupt trigger occur simultaneously, the interrupt of the vector 3 is accepted.) Maskable interrupts are accepted when LV1-0 is less than PSW.IM1-0.
  • Page 101 Chapter 3 Interrupts Determination of Maskable Interrupt Acceptance The procedures of the interrupt acceptance is described below. 1. IR is set to "1". 2. When IE is "1", the interrupt request is sent to CPU. 3. When LV1-0 is less than PSW.IM1-0 and PSW.MIE is "1", the above interrupt request is accepted. 4.
  • Page 102 Chapter 3 Interrupts Explanation of PSW.MIE and PSW.IM1-0 PSW.MIE is set to "0" when: • MEMCTR.MIESET is "0", and NMI or a maskable interrupt is accepted. • PSW.MIE is set to "0" by software. • BE instruction is executed (BKD and MIE are set to "0".) •...
  • Page 103 Chapter 3 Interrupts Interrupt Acceptance Operation (hardware processing) When an interrupt is accepted, the LSI executes the following sequence by hardware. 1. Stack Pointer (SP) is updated. → SP-6 2. PSW.BKD is set to "1". (The bank function is disabled.) 3.
  • Page 104 Chapter 3 Interrupts Interrupt Return Operation (RTI instruction) RTI instruction makes the LSI go back to the program which had been executed before the interrupt occurred. Before RTI execution, if the data of D0/D1/D2/D3 and A0/A1 registers was saved in the interrupt handler with PUSH instruction, they are needed to be backed to each registers with POP instruction.
  • Page 105 Chapter 3 Interrupts Maskable Interrupt Processing The following figure shows the processing sequence when the lower priority level interrupt occurs while process- ing the higher priority level interrupt. (Interrupt 1: LV1-0 = "00", Interrupt 2: LV1-0 = "10", Interrupt 3: LV1-0 = "11") MIE="0"...
  • Page 106 Chapter 3 Interrupts Multiple maskable interrupt control When MEMCTR.MIESET is "0" and an interrupt is accepted, PSW.MIE is set to "0" and the multiple maskable interrupt is not occurred. To enable the multiple interrupts occurrence, set MEMCTR.MIESET to "1" by software before accepting inter- rupts, or set PSW.MIE to "1"...
  • Page 107 Chapter 3 Interrupts The following figure shows the processing sequence when the higher priority level interrupt occurs while process- ing the lower priority level interrupt. (Interrupt 1: LV1-0 = "10", Interrupt 2: LV1-0 = "00") Main Program PSW.IM1-0="11" Interrupt 1 occurs Accepted because LV1-0 <...
  • Page 108 Chapter 3 Interrupts NMI Processing Figure:3.1.8 shows the processing sequence of NMI. Main Program PSW.IM1-0="11" NMI 1 occurs IM1-0="00" Interrupt acceptance cycle NMI handler: 1 NMI 2 occurs IM1-0="11" IM1-0="00" Interrupt acceptance cycle NMI handler: 2 IM1-0="11" Parentheses () indicates hardware processing. *1 : The multiple interrupts are not accepted during NMI handler.
  • Page 109: Maskable Interrupt Control Register Setup

    Chapter 3 Interrupts 3.1.3 Maskable Interrupt Control Register Setup Setting xICR.IR by software xICR.IR is set to "1" when the interrupt trigger occurs, and cleared to "0" by hardware when the interrupt is accepted. To operate IR by software, MEMCTR.IRWE needs to be set to "1". Interrupt Control Register Setup Procedure Setup procedures of xICR of maskable interrupt is described below: Setup Procedure...
  • Page 110 Chapter 3 Interrupts xICR.IR is set when the corresponding interrupt occurs or the edge switching of the interrupt is done, regardless of the value of xICR.IE. Clear IR to "0" following the setup procedures (4) to (6). Before operating xICR, set PSW.MIE to "0". There's no guarantee of proper operation when writing to xICR while PSW.MIE is "1".
  • Page 111: Group Interrupt Control Register Setup

    Chapter 3 Interrupts 3.1.4 Group Interrupt Control Register Setup Setup PERInDT (n = 0, 1) by Software The each bit of the PERInDT is set to "1" by the hardware and software, and cleared to "0" only by software. When the interrupt occurs, the corresponding bits is set to "1", and the maskable interrupt occurs depending on the setting of the each bit of PERInEN.
  • Page 112 Chapter 3 Interrupts Group interrupt control register Setup Procedure Setup procedures of the group interrupt control register set by the software are as follow: Setup Procedure Description (1) Disable all maskable interrupts (1) Clear PSW.MIE to disable all maskable interrupts, which is needed, especially when xICRis changed.
  • Page 113 Chapter 3 Interrupts Sample program of Group interrupt service routine mov (PERInDT), Dn Load the value of PERInDT to Dn, mov Dn, (PERInDT) and clear the PERInDT. mov (PERInEN), Dm Extract the request bit that interrupt is enabled. and Dm, Dn Routine of bit0 factor btst 0x01, Dn beq bit0_end...
  • Page 114: Control Registers

    Chapter 3 Interrupts 3.2 Control Registers Interrupt Control Registers is listed in Table:3.2.1. Table:3.2.1 Interrupt Control Registers Symbol Address Register name Page NMICR 0x03FE1 Non-maskable interrupt control register III-22 IRQ0ICR 0x03FE2 External interrupt 0 control register III-23 IRQ1ICR 0x03FE3 External interrupt 1 control register III-23 IRQ2ICR 0x03FE4...
  • Page 115 Chapter 3 Interrupts Write access to xICR must be done when PSW.MIE is "0". There's no guarantee of proper operation if xICR is written with when PSW.MIE is "1". When an xICR.LV1-0 is set to "11", the interrupt (IRQ) does not occur. Control Registers III - 21...
  • Page 116: Non-Maskable Interrupt (Nmi) Control Register

    Chapter 3 Interrupts 3.2.1 Non-maskable Interrupt (NMI) Control Register Non-maskable Interrupt (NMI) Control Register (NMICR: 0x03FE1) When the undefined instruction is detected, IRQNPG is set to "1" and NMI occurs. When the WDT overflows, IRQNWDG is set to "1" and NMI occurs. Bit name IRQNPG IRQNWDG...
  • Page 117: External Interrupt Control Register

    Chapter 3 Interrupts 3.2.2 External Interrupt Control Register External Interrupt 0 to 6 Control Register (IRQnICR (n = 0, 1, 2, 3, 4, 5, 6)) Bit name REDG Reserved At reset Access Bit name Description Interrupt level LV1-0 - Set interrupt level from 0 to 3. Interrupt trigger edge REDG 0: Falling edge...
  • Page 118: Peripheral Group Interrupt Control Register

    Chapter 3 Interrupts 3.2.3 Peripheral Group Interrupt Control Register Group-0/Group-1 Interrupt Level Control Register (PERI0ICR, PERI1ICR) Bit name Reserved At reset Access Bit name Description Interrupt level bit LV1-0 Set interrupt level from 0 to 3. Always read as "0". Reserved Must be set to "0".
  • Page 119 Chapter 3 Interrupts Group-0 Interrupt Enable Register (PERI0EN) Bit name At reset Access Bit name Description Always read as "0". RTC-Alarm1 interrupt enable control 0: Disable 1: Enable RTC-Alarm0 interrupt enable control 0: Disable 1: Enable RTC interrupt enable control 0: Disable 1: Enable RTC-TBT interrupt enable control...
  • Page 120 Chapter 3 Interrupts Group-0 Interrupt Factor Register (PERI0DT) Bit name At reset Access Bit name Description Always read as "0". RTC-Alarm1 interrupt request detection 0: Not detected 1: Detected RTC-Alarm0 interrupt request detection 0: Not detected 1: Detected RTC interrupt request detection 0: Not detected 1: Detected RTC-TBT interrupt request detection...
  • Page 121 Chapter 3 Interrupts Group-1 Interrupt Enable Register (PERI1EN) Bit name At reset Access Bit name Description Always read as "0". DMA-Error interrupt enable control 0: Disable 1: Enable DMA-AddReq interrupt enable control 0: Disable 1: Enable DMA interrupt enable control 0: Disable 1: Enable A/D interrupt enable control...
  • Page 122 Chapter 3 Interrupts Group-1 Interrupt Factor Register (PERI1DT) Bit name At reset Access Bit name Description Always read as "0". DMA-Error interrupt request detection 0: Not detected 1: Detected DMA-AddReq interrupt request detection 0: Not detected 1: Detected DMA interrupt request detection 0: Not detected 1: Detected A/D interrupt request detection...
  • Page 123: Other Interrupt Control Register

    Chapter 3 Interrupts 3.2.4 Other Interrupt Control Register Other Interrupt Control Register (TMnICR (n = 0, 1, 2, 3, 4, 7, 8, 9), TMnOC2ICR (n = 7, 8, 9), SCnRICR (n = 0, 1), SCnSICR (n = 2, 3), SCnTICR (n = 0, 1, 2, 3)) Register specification of above other interrupt control registers is described below.
  • Page 124: Block Diagram Of Peripheral Function Group Interrupt

    Chapter 3 Interrupts 3.2.5 Block diagram of Peripheral function group interrupt Block diagram of Group-0/Group-1 interrupt interface PERI0DT.DT0 Timer 5 interrupt edge detection PERI0DT.DT1 Timer 6 interrupt edge detection PERI0DT.DT2 TBT interrupt edge detection Group PERI0DT.DT3 RTC-TBT interrupt Interrupt 0 edge detection PERI0DT.DT4...
  • Page 125 Chapter 3 Interrupts PERI1DT.DT0 LVD interrupt edge detection PERI1DT.DT1 A/D interrupt edge detection Group PERI1DT.DT2 DMA interrupt Interrupt 1 edge detection PERI1DT.DT3 DMA-Addreq interrupt edge detection PERI1DT.DT4 DMA-Error interrupt edge detection When the interrupt factor and set/clear by software ocurred at the same time, set/clear by software is given priority.
  • Page 126: External Interrupts

    Chapter 3 Interrupts 3.3 External Interrupts The LSI has 8 external interrupts shown in Table 3.3.1. Table:3.3.1 External Interrupt Functions Rising or Falling Both edge External Interrupt Pin name Noise filter Key interrupt edge triggered interrupt triggered interrupt √ √ √...
  • Page 127: External Interrupt Control Registers

    Chapter 3 Interrupts 3.3.1 External Interrupt Control Registers Table:3.3.2 shows the external interrupt control registers. Table:3.3.2 External Interrupt Control Register External interrupt Symbol Address Register name Page IRQ0 IRQ0ICR 0x03FE2 External interrupt 0 control register III-23 IRQIEN 0x03F4C External interrupt input control register III-35 IRQISEL0 0x03F4D...
  • Page 128 Chapter 3 Interrupts External interrupt Symbol Address Register name Page IRQ6 IRQ6ICR 0x03FE8 External interrupt 6 control register III-23 IRQIEN 0x03F4C External interrupt input control register III-35 IRQISEL0 0x03F4D External interrupt input pin selection register 0 III-36 EDGDT 0x03FD4 Both edges interrupt control register III-38 NFCTR67 0x03ED3...
  • Page 129 Chapter 3 Interrupts External Interrupt Input Control Register (IRQIEN) Bit name IRQI6EN IRQI5EN IRQI4EN IRQI3EN IRQI2EN IRQI1EN IRQI0EN At reset Access Bit name Description Always read as "0". IRQ6 input enable control IRQI6EN 0: Disable 1: Enable (IRQ6A/IRQ6B) IRQ5 input enable control IRQI5EN 0: Disable 1: Enable (IRQ5A/IRQ5B/IRQ5C)
  • Page 130 Chapter 3 Interrupts External Interrupt Input pin Selection Register 0 (IRQISEL0) Bit name IRQ6SEL IRQ5SEL IRQ4SEL IRQ3SEL IRQ2SEL IRQ1SEL IRQ0SEL At reset Access Bit name Description Always read as "0". IRQ6 pin selection IRQ6SEL 0: IRQ6A (P16) 1: IRQ6B (P70) IRQ5 pin selection IRQ5SEL 0: IRQ5A (P15)
  • Page 131 Chapter 3 Interrupts External Interrupt Input pin Selection Register 1 (IRQISEL1) IRQ5C IRQ4C Bit name At reset Access Bit name Description Always read as "0". IRQ5 pin selection IRQ5CSEL 0: IRQ5A/IRQ5B (P15/P71) 1: IRQ5C (P13) IRQ4 pin selection IRQ4CSEL 0: IRQ4A/IRQ4B (P14/P72) 1: IRQ4C (P12) Always read as "0".
  • Page 132 Chapter 3 Interrupts Both Edges Interrupt Control Register (EDGDT) Bit name EDGSEL6 EDGSEL5 EDGSEL4 EDGSEL3 EDGSEL2 EDGSEL1 EDGSEL0 At reset Access Bit name Description Always read as "0". IRQ6 trigger selection EDGSEL6 0: Rising edge or falling edge 1: Both edges (Rising and falling edges) IRQ5 trigger selection EDGSEL5 0: Rising edge or falling edge...
  • Page 133 Chapter 3 Interrupts Noise Filter 01 Control Register (NFCTR01) Bit name NF1SCK2 NF1SCK1 NF1SCK0 NF1EN NF0SCK2 NF0SCK1 NF0SCK0 NF0EN At reset Access Bit name Description IRQ1 noise sampling frequency 000: f HCLK 001: f HCLK 010: f HCLK NF1SCK2 011: f NF1SCK1 HCLK NF1SCK0...
  • Page 134 Chapter 3 Interrupts Noise Filter 23 Control Register (NFCTR23) Bit name NF3SCK2 NF3SCK1 NF3SCK0 NF3EN NF2SCK2 NF2SCK1 NF2SCK0 NF2EN At reset Access Bit name Description IRQ3 noise sampling frequency 000: f HCLK 001: f HCLK 010: f HCLK NF3SCK2 011: f NF3SCK1 HCLK NF3SCK0...
  • Page 135 Chapter 3 Interrupts Noise Filter 45 Control Register (NFCTR45) Bit name NF5SCK2 NF5SCK1 NF5SCK0 NF5EN NF4SCK2 NF4SCK1 NF4SCK0 NF4EN At reset Access Bit name Description IRQ5 noise sampling frequency 000: f HCLK 001: f HCLK 010: f HCLK NF5SCK2 011: f NF5SCK1 HCLK NF5SCK0...
  • Page 136 Chapter 3 Interrupts Noise Filter 67 Control Register (NRCTR67) Bit name NF7SCK2 NF7SCK1 NF7SCK0 NF7EN NF6SCK2 NF6SCK1 NF6SCK0 NF6EN At reset Access Bit name Description IRQ7 noise sampling frequency 000: f HCLK 001: f HCLK 010: f HCLK NF7SCK2 011: f NF7SCK1 HCLK NF7SCK0...
  • Page 137 Chapter 3 Interrupts KEY Interrupt Input pin Selection Register (KEYSEL) Bit name KEYSEL7 KEYSEL6 KEYSEL5 KEYSEL4 KEYSEL3 KEYSEL2 KEYSEL1 KEYSEL0 At reset Access Bit name Description KEY7 pin selection KEYSEL7 0: KEY7A(P17) 1: KEY7B(P67) KEY6 pin selection KEYSEL6 0: KEY6A(P16) 1: KEY6B(P66) KEY5 pin selection KEYSEL5...
  • Page 138 Chapter 3 Interrupts KEY Interrupt Input Control Register (KEYIEN) Bit name KEY7EN KEY6EN KEY5EN KEY4EN KEY3EN KEY2EN KEY1EN KEY0EN At reset Access Bit name Description KEY7 input enable control KEY7EN 0: Disable 1: Enable (KEY7A/KEY7B) KEY6 input enable control KEY6EN 0: Disable 1: Enable (KEY6A/KEY6B) KEY5 input enable control...
  • Page 139: Rising (Falling) Edge Triggered Interrupt

    Chapter 3 Interrupts 3.3.2 Rising (Falling) edge triggered interrupt Rising or falling edge interrupt can be selected with IRQ0ICR, IRQ1ICR, IRQ2ICR, IRQ3ICR, IRQ4ICR, IRQ5ICR and IRQ6ICR. Setting example of rising edge triggered interrupt The following example shows how to enable the rising edge triggered IRQ4 at P72. Step Settings Register...
  • Page 140: Both Edges Triggered Interrupt

    Chapter 3 Interrupts 3.3.3 Both edges triggered Interrupt Both edges (rising edge and falling edge) interrupt can be specified with the EDGDT. Setting example of both edges interrupt The following example shows how to select the both edges triggered IRQ0 at P10. Step Settings Register...
  • Page 141: Key Interrupt

    Chapter 3 Interrupts 3.3.4 Key Interrupt Key interrupt (KEYIRQn) pin can be selected with the KEYIEN and KEYSEL. KEYIRQn is generated when one of the KEYIRQ pins goes from "High" to "Low". Setting example of KEYIRQ The following example shows how to use P10, P11, P12 and P13 as KEYIRQ pins and generate IRQ7. Step Settings Register...
  • Page 142 Chapter 3 Interrupts Setting example of NF The following example shows how to select the positive edge triggered IRQ0 at P10 and enable NF of IRQ0. Step Settings Register Description Set P10 as IRQ0 pin IRQIEN Set IRQIEN.IRQ0EN to "1". IRQISEL0 Set IRQISEL0.IRQ0SEL to "0".
  • Page 143: Chapter 4 Clock/ Mode/ Voltage Control

    IV.. Chapter 4 Clock/ Mode/ Voltage Control...
  • Page 144: Clock Control

    Chapter 4 Clock/ Mode/ Voltage Control 4.1 Clock Control The LSI has 4 types of clock oscillation circuits. Table:4.1.1 Clock Oscillation Circuits Internal high-speed oscillation circuit Max. 10 MHz clock (HRCCLK) can be generated. High-speed clock is generated by connecting crystal or ceramic oscillator External high-speed oscillation circuit to OSC1/OSC2 pins.
  • Page 145: Control Registers

    Chapter 4 Clock/ Mode/ Voltage Control 4.1.1 Control Registers Table:4.1.2 shows control registers of clock control functions. Table:4.1.2 Clock Control Registers Symbol Address Register name Page CPUM 0x03F00 CPU mode control register IV-4 CKCTR 0x03F04 System clock control register IV-6 HCLKCNT 0x03F05 High-speed oscillation clock control register...
  • Page 146 Chapter 4 Clock/ Mode/ Voltage Control CPU Mode Control Register (CPUM: 0x03F00) Bit name STOP HALT HALTMOD XIMOD OSCMOD CLKSEL Initial value Access Bit name Description Always read as "00". STOP mode request STOP 0: not STOP mode 1: STOP mode HALT mode request HALT 0: not HALT mode...
  • Page 147 Chapter 4 Clock/ Mode/ Voltage Control Table:4.1.3 Operating Mode Control and Clock Oscillation Status CPUM Clock and CPU Status Operation mode System STOP HALT HALTMOD XIMOD OSCMOD CLKSEL HCLK SCLK clock Stop / NORMAL Active HCLK Active Active IDLE Active Active SCLK Active...
  • Page 148 Chapter 4 Clock/ Mode/ Voltage Control System Clock Control Register (CKCTR: 0x03F04) Bit name OSCSEL2-0 Initial value Access Bit name Description Always read as "00000" The frequency of SYSCLK 000: f HSCLK 001: f HSCLK 010: f HSCLK OSCSEL2-0 011: f HSCLK 100: f HSCLK...
  • Page 149 Chapter 4 Clock/ Mode/ Voltage Control High-speed Oscillation Clock Control Register (HCLKCNT: 0x03F05) Bit name HCLKSEL FCNT1-0 Reserved Reserved HOSCCNT HRCCNT Initial value Access Bit name Description High-speed oscillation clock select 0: Internal high-speed oscillation HCLKSEL 1: External high-speed oscillation Select internal high-speed oscillation (set the bit from 1 to 0) when HRC- CNT = 1.
  • Page 150 Chapter 4 Clock/ Mode/ Voltage Control Low-speed Oscillation Clock Control Register (SCLKCNT: 0x03F06) Bit name SCLKSEL Reserved SOSCCNT SRCCNT Initial value Access Bit name Description Low-speed oscillation clock select SCLKSEL 0: Internal low-speed oscillation 1: External low-speed oscillation Always read as "0000". Reserved Always set to "1".
  • Page 151 Chapter 4 Clock/ Mode/ Voltage Control Clock Supply Control Register 0 (PRICKCNT0: 0x03E10) Clock supply control register 0 controls clock supply to peripheral functions. PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT Bit name Initial value Access Bit name Description Clock control for RTC function PRICKCNT07 0: disabled...
  • Page 152 Chapter 4 Clock/ Mode/ Voltage Control Clock Supply Control Register 1 (PRICKCNT1: 0x03E11) Clock supply control register 1 controls clock supply to peripheral functions. PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT Bit name Initial value Access Bit name Description Clock control for DMA function PRICKCNT17 0: disabled...
  • Page 153 Chapter 4 Clock/ Mode/ Voltage Control Clock Supply Control Register 2 (PRICKCNT2: 0x03E12) Clock supply control register 2 controls clock supply to peripheral functions. PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT PRICKCNT Bit name Initial value Access Bit name Description Always read as "0". Clock control for RTC time base timer function PRICKCNT25 0: disabled...
  • Page 154: Change Of The External Low-Speed Oscillation Capability

    Chapter 4 Clock/ Mode/ Voltage Control 4.1.2 Change of the External Low-speed Oscillation Capability The external low-speed oscillation starts with high-current driving capability at LSI power-on. After the oscilla- tion stabilization, the LSI changes the oscillation to low-current driving capability for the low power consump- tion.
  • Page 155: Mode Control Function

    Chapter 4 Clock/ Mode/ Voltage Control 4.2 Mode Control Function This LSI operates in one of the following 5 modes (NORMAL/SLOW/HALT/STOP/IDLE). The CPUM controls the mode transition. LSI reset or interrupts make the LSI recover from STANDBY mode (HALT/STOP). Figure:4.2.1 shows the transition between each operation mode. For detail of transition between operation mode, VDD18 voltage and clock, refer to [4.4 Mode/Voltage/Clock Transition] CPU operation mode...
  • Page 156 Chapter 4 Clock/ Mode/ Voltage Control To make clock switching between HCLK and SCLK stable and synchronized, the frequency of HCLK must be 2.5 times or more than that of SCLK. Although HCLK oscillates in IDLE mode, do not operate the peripheral circuits with HCLK. Peripheral circuits must be enabled with HCLK after the CPU goes to NORMAL mode.
  • Page 157: Normal Mode

    Chapter 4 Clock/ Mode/ Voltage Control 4.2.1 NORMAL Mode Transition from SLOW to NORMAL When the transition from SLOW to NORMAL, the oscillation stabilization wait for HCLK is ensured by hard- ware. Figure:4.2.2 shows the transition procedure to NORMAL. The transition to NORMAL through IDLE can be allowed, when HCLK must be stable in IDLE as shown in Figure:4.2.3.
  • Page 158 Chapter 4 Clock/ Mode/ Voltage Control Clock Change from HRCCLK to HOSCCLK Figure:4.2.4 shows the clock change procedure from HRCCLK to HOSCCLK. NORMAL mode (SYSCLK = HRCCLK) HCLKCNT.HOSCCNT == 1 Start the external high-speed oscillation HCLKCNT.HOSCCNT = 1 External high-speed oscillation stabilization wait time Switching the source oscillation of fosc HCLKCNT.HCLKSEL=1...
  • Page 159: Slow Mode

    Chapter 4 Clock/ Mode/ Voltage Control 4.2.2 SLOW Mode Transition from NORMAL to SLOW Figure:4.2.6 shows the mode transition procedure from NORMAL to SLOW. (The low-speed clock oscillation is enabled in the low-speed oscillation clock control register (SCLKCNT). Fig- ure:4.1.1 shows the Operation Enable signal for external slow-speed oscillation circuit or internal slow-speed oscillation circuit.) NORMAL mode CPUM.XIMOD == 1...
  • Page 160 Chapter 4 Clock/ Mode/ Voltage Control Clock Change from SRCCLK to SOSCCLK Figure:4.2.7 shows the clock change procedure from SRCCLK to SOSCCLK. SLOW mode (SYSCLK = SRCCLK) SCLKCNT.SOSCCNT == 1 Start the external low-speed oscillation SCLKCNT.SOSCCNT = 1 External low-speed oscillation stabilization wait time Switching the source oscillation of SCLK SCLKCNT.SCLKSEL = 0...
  • Page 161: Standby Mode

    Chapter 4 Clock/ Mode/ Voltage Control 4.2.3 STANDBY Mode The transition from CPU operating mode (NORMAL/SLOW) to STANDBY mode (HALT/STOP) is executed by the program. CPU wakes up from STANBY mode by the interrupt. Figure:4.2.9 shows the flow diagram of transi- tion to/from STANDBY mode.
  • Page 162 Chapter 4 Clock/ Mode/ Voltage Control Transition to HALT Mode The system can change from any mode of NORMAL and SLOW to HALT0/HALT1/HALT2/HALT3 mode. In HALT0/HALT1 mode, CPU is stopped operating while the oscillators remain active. In HALT2/HALT3 mode, only the low-speed oscillator remains active and the clock is supplied only to Real time clock. CPU wakes up from HALT mode by interrupt or reset.
  • Page 163 Chapter 4 Clock/ Mode/ Voltage Control NORMAL/SLOW mode CPUM.XIMOD == 1 Start the low-speed oscillation (*) CPUM.XIMOD = 1 The low-speed oscillation stabilization wait time Transition to HALT3 mode (Set the CPUM as described in Table 4.1.3.) (*) When SCLKCNT.SOSCCNT=1, SOSCCLK starts. When SCLKCNT.SRCCNT=1, SRCCLK starts.
  • Page 164 Chapter 4 Clock/ Mode/ Voltage Control Transition to STOP Mode The system changes from any mode of NORMAL and SLOW to STOP0/STOP1 mode. In any case, both oscilla- tion and CPU are stopped. A reset or an interrupt is a source for wake up from STOP mode. Figure:4.2.12 shows the transition procedure from CPU operating mode to STOP mode.
  • Page 165: Note For Transition To Standby Mode

    Chapter 4 Clock/ Mode/ Voltage Control 4.2.4 Note for Transition to STANDBY Mode While PSW.MIE is set to "1", if it can’t be guaranteed that an interrupt for wakeup re-occurs after the transition to STANBY mode since a maskable interrupt for wakeup has occurred before the transition to STANBY mode by setting the CPUM register, CPU can not wake up from STANDBY mode.
  • Page 166 Chapter 4 Clock/ Mode/ Voltage Control NORMAL/SLOW mode Set the PSW.MIE to "0", Disable maskable interrupts and set all interrupt enable bits (xICR.IE) to "0". Enable interrupt which Set the xICR.IE of the return factor to "1". triggers return Return factor interrupt occured Set HALT/STOP mode Watchdog timer...
  • Page 167 Chapter 4 Clock/ Mode/ Voltage Control NORMAL/SLOW mode Set the PSW.MIE to "0", Disable maskable interrupts and set all interrupt enable bits (xICR.IE) to "0". Enable interrupt which Set the xICR.IE of the return factor to "1". triggers return Return factor interrupt occured Set HALT/STOP mode Watchdog timer...
  • Page 168: Voltage Control

    Chapter 4 Clock/ Mode/ Voltage Control 4.3 Voltage Control 4.3.1 Overview The LSI has 3 kinds of power supply voltage; 1.1 V, 1.3 V, and 1.8 V. Depending on the operating supply voltage, operating frequency, and target value of power consumption, power supply voltage is selected and supplied to CPU, the peripheral function, RAM, and ReRAM.
  • Page 169: Power Supply Control Register

    Chapter 4 Clock/ Mode/ Voltage Control 4.3.3 Power Supply Control Register Power Supply Control Register 0 (PWCTR0: 0x03F6C) The power supply control register 0 controls the switching V output of the power supply generation circuit. DD18 Bit name Reserved Reserved Reserved Reserved Reserved...
  • Page 170 Chapter 4 Clock/ Mode/ Voltage Control Power Supply Control Register 1 (PWCTR1: 0x03F6D) The power supply control register 1 controls CPU outage when changing the output voltage, VDD18 and Deep STANDBY mode. DEEP- PWUPTM PWUPTM PWUPTM Bit name Reserved Reserved Reserved Initial value Access...
  • Page 171: Operation

    Chapter 4 Clock/ Mode/ Voltage Control 4.3.4 Operation Voltage Transition of VDD18 by Program Figure:4.3.1 shows the example of voltage transition of VDD18 by program. When SLOW mode, the PWCTR0.VDDLV1-0 are set to change the output voltage, VDD18 and achieve low- power consumption or high-speed operation depending on the operating frequency.
  • Page 172 Chapter 4 Clock/ Mode/ Voltage Control Voltage Transition of VDD18 by Mode Transition Figure:4.3.2 shows the example of voltage transition of VDD18 by mode transition. For the mode transition method, refer to [4.2 Mode Control Function]. When the Deep STANDBY mode control, that change the voltage from 1.3 V or 1.8 V to 1.1 V, is enabled during the mode transition from NORMAL to HALT2/STOP0, the STANBY mode with low-power consumption can be set by just updating the CPUM register.
  • Page 173: Mode/Voltage/Clock Transition

    Chapter 4 Clock/ Mode/ Voltage Control 4.4 Mode/Voltage/Clock Transition The following Table:4.4.1 shows the state transition by changing the operation mode, VDD18 voltage and clock. The mode name in Table:4.4.1 is described in accordance with a rule below. [Operation mode]_[VDD18 voltage]_[SYSCLK]_[Oscillating clock except SYSCLK]_[Special mode] [SYSCLK] is described in NORMAL, SLOW, IDLE, HALT0 or HALT1 mode.
  • Page 174 Chapter 4 Clock/ Mode/ Voltage Control Table:4.4.1 Mode/Voltage/Clock Transition Destination mode RESET NORMAL_18_HCLK_SCLK NORMAL_18_HCLK NORMAL_13_HRC_SCLK NORMAL_13_HRC SLOW_18_SCLK SLOW_13_SCLK SLOW_11_SCLK HALT0_18_HCLK_SCLK HALT0_18_HCLK HALT0_13_HRC_SCLK HALT0_13_HRC HALT1_18_SCLK HALT1_13_SCLK HALT1_11_SCLK HALT2_18_SCLK HALT2_13_SCLK HALT2_11_SCLK_DEEP HALT3_18_SCLK HALT3_13_SCLK HALT3_11_SCLK STOP0_18 STOP0_13 STOP0_11_DEEP STOP1_18 STOP1_13 STOP1_11 IDLE_18_SCLK_HCLK IDEL_13_SCLK_HRC Operation mode change VDD18 voltage change Oscillation stabilization wait process...
  • Page 175: Chapter 5 Watchdog Timer (Wdt

    Chapter 5 Watchdog Timer (WDT)
  • Page 176: Overview

    Chapter 5 Watchdog Timer (WDT) 5.1 Overview The watchdog timer (WDT) generates NMI (WDIRQ) when the dedicated counter (WDT-Counter) is not cleared during the error detect period and overflows. When two consecutive WDIRQs occur without clearing WDT- Counter, the LSI is reset by hardware. The clock source of WDT-Counter is selected from SOSCCLK or SRC- CLK.
  • Page 177: Wdt Control Register

    Chapter 5 Watchdog Timer (WDT) 5.2 WDT Control Register 5.2.1 WDT Control Register WDT Control Register (WDCTR: 0x03F02) Bit name WDCKSEL WDTS2-0 WDEN At reset Access Bit name Description Select watchdog time clock source WDCKSEL 0: SRCCLK 1: SOSCCLK Always read as 0. Watchdog error detect period setup ×...
  • Page 178: Operation

    Chapter 5 Watchdog Timer (WDT) 5.3 Operation 5.3.1 WDT Operation WDT-Counter needs to be cleared periodically to avoid WDT overflow. WDT-Counter is cleared by writing something on the WDCTR. WDT generates WDIRQ when WDT-Counter is not cleared during the error detect period and overflows. WDT-counter should be cleared with BSET instruction (for example, BSET (WDCTR)0) to avoid changing the error detection time etc.
  • Page 179: Setup Example

    Chapter 5 Watchdog Timer (WDT) 5.3.2 Setup Example The following procedure shows the example of WDT operation. SRCCLK is selected as WDCLK, and the error × time period is 2 (1/f WDTCLK Setup Example Step Setup Procedure Register Description Set the error detection period WDCTR Set the WDCKSEL to "0".
  • Page 180 Chapter 5 Watchdog Timer (WDT) V - 6 Operation...
  • Page 181: Chapter 6 Power Supply Voltage Detection

    VI.. Chapter 6 Power Supply Voltage Detection...
  • Page 182: Overview

    Chapter 6 Power Supply Voltage Detection 6.1 Overview 6.1.1 Power Supply Voltage Detection Overview This LSI has the power supply voltage detector (PSVD) to detect power supply voltage and generate interrupt. PSVD compares the power supply voltage (V ) and the detection voltage (V ), and generates the interrupt DD30 (LVIIRQ) when the level of V...
  • Page 183: Control Register

    Chapter 6 Power Supply Voltage Detection 6.2 Control Register 6.2.1 Registers Table:6.2.1 shows the PSVD related registers. Table:6.2.1 Power Supply Voltage Detection Control Registers Symbol Address Register name Page LVICTR0 0x03F66 PSVD control register 0 VI-4 LVICTR1 0x03F67 PSVD control register 1 VI-5 LVICTR2 0x03F68...
  • Page 184: Power Supply Voltage Detection Control Registers

    Chapter 6 Power Supply Voltage Detection 6.2.2 Power Supply Voltage Detection Control Registers PSVD Control Register 0 (LVICTR0: 0x03F66) Bit name Reserved LV4-0 At reset Access Bite name Description Reserved Must be set to 0. Always read as 0. The level of V 00000: 1.10 V 00001: 1.15 V 00010: 1.20 V...
  • Page 185 Chapter 6 Power Supply Voltage Detection PSVD Control Register 1 (LVICTR1: 0x03F67) Bit name LVIOUT LVION At reset Access Bite name Description Always read as 0. monitor bit DD30 ≤ V 0: V LVIOUT DD30 ≥ V 1: V DD30 PSVD enable control LVION 0: Disabled...
  • Page 186 Chapter 6 Power Supply Voltage Detection PSVD Control Register 2 (LVICTR2: 0x03F68) The LVICTR2 controls whether to add the noise filter on the output of PSVD and the sampling frequency of it. Bit name LVINFSCK2-0 LVINFEN At reset Access Bite name Description Always read as 0.
  • Page 187: Setting Example

    Chapter 6 Power Supply Voltage Detection 6.3 Setting Example 6.3.1 PSVD Setting Example Mode Transition Operation with PSVD The following procedure shows that CPU transits from STOP to NORMAL mode when VDD30 exceeds 2.0 V. Setup Procedure Description (1) Disable all maskable interrupts. (1) Clear the MIE bit of PSW to disable all maskable interrupts.
  • Page 188 Chapter 6 Power Supply Voltage Detection Setup Procedure Description (10) When the LVIOUT bit is "0", operating (10) When the monitored LVIOUT bit is "0", the operating mode transits to STOP mode mode transits to STOP mode. CPUM (0x03F00) bp3: STOP = 1 (11) Return from STOP mode by interrupt (11) When the power supply voltage exceeds 2.0 V, an interrupt is generated to return from STOP mode.
  • Page 189: Chapter 7 I/O Port

    VII.. Chapter 7 I/O Port...
  • Page 190: Overview

    Chapter 7 I/O Port 7.1 Overview 7.1.1 I/O Port Overview I/O port is controlled with the following registers. - Output Register (PnOUT) - Input Register (PnIN) - Direction Control Register (PnDIR) - Pull-up Control Register (PnPLU) - Special Function Control Register (PnODC, PnNLC etc.) Table:7.1.1 shows the status of each port at LSI reset.
  • Page 191: Control Registers

    Chapter 7 I/O Port 7.2 Control Registers Table:7.2.1 I/O Port Control Registers List Register Address Function Page P0OUT 0x03F10 Port 0 output register VII-5 P0IN 0x03F20 Port 0 input register VII-8 P0DIR 0x03F30 Port 0 direction control register VII-12 P0PLUP 0x03F40 Port 0 pull-up resistor control register VII-15...
  • Page 192 Chapter 7 I/O Port Register Address Function Page P6PLUP 0x03F46 Port 6 pull-up resistor control register VII-17 P6ODC 0x03F56 Port 6 N-ch open-drain control register VII-21 P6NLC 0x03EC5 Port 6 N-ch current capacity selection register VII-24 P7OUT 0x03F17 Port 7 output register VII-7 P7IN 0x03F27...
  • Page 193: Port N Output Registers

    Chapter 7 I/O Port 7.2.1 Port n Output Registers PnOUT is the register to set output data in when I/O is used as a general purpose port. Port 0 Output Register (P0OUT: 0x03F10) Bit name P0OUT7-0 At reset Access Bit name Description Output data 0: Output "Low"...
  • Page 194 Chapter 7 I/O Port Port 3 Output Register (P3OUT: 0x03F13) Bit name P3OUT7-0 At reset Access Bit name Description Output data 0: Output "Low" (V -level) P3OUT7-0 1: Output "High" (V -level) DD30 Port 4 Output Register (P4OUT: 0x03F14) Bit name P4OUT7-0 At reset Access...
  • Page 195 Chapter 7 I/O Port Port 6 Output Register (P6OUT: 0x03F16) Bit name P6OUT7-0 At reset Access Bit name Description Output data 0: Output "Low" (V -level) P6OUT7-0 1: Output "High" (V -level) DD30 Port 7 Output Register (P7OUT: 0x03F17) Bit name P7OUT7-0 At reset Access...
  • Page 196: Port N Input Registers

    Chapter 7 I/O Port 7.2.2 Port n Input Registers PnIN is the register to read the input data from when I/O is used as a general purpose port. Port 0 Input Register (P0IN: 0x03F20) Bit name P0IN7-0 At reset Access Bit name Description Input data...
  • Page 197 Chapter 7 I/O Port Port 2 Input Register (P2IN: 0x03F22) Bit name P2IN7 P2IN6-0 At reset Access Bit name Description Input data 0: Input "Low" (V -level) P2IN7-0 1: Input "High" (V -level) DD30 Port 3 Input Register (P3IN: 0x03F23) Bit name P3IN7-0 At reset...
  • Page 198 Chapter 7 I/O Port Port 5 Input Register (P5IN: 0x03F25) Bit name P5IN7-0 At reset Access Bit name Description Input data 0: Input "Low" (V -level) P5IN7-0 1: Input "High" (V -level) DD30 Port 6 Input Register (P6IN: 0x03F26) Bit name P6IN7-0 At reset Access...
  • Page 199 Chapter 7 I/O Port Port 8 Input Register (P8IN: 0x03F28) Bit name P8IN5-0 At reset Access Bit name Description Always read as 0. Input data 0: Input "Low" (V -level) P8IN7-0 1: Input "High" (V -level) DD30 Control Registers VII - 11...
  • Page 200: Port N Direction Control Registers

    Chapter 7 I/O Port 7.2.3 Port n Direction Control Registers PnDIR is the register to control I/O direction of I/O when it is used as a general purpose port. Port 0 Direction Control Register (P0DIR: 0x03F30) Bit name P0DIR7-0 At reset Access Bit name Description...
  • Page 201 Chapter 7 I/O Port Port 3 Direction Control Register (P3DIR: 0x03F33) Bit name P3DIR7-0 At reset Access Bit name Description I/O mode selection 0: Intput mode P3DIR7-0 1: Output mode Port 4 Direction Control Register (P4DIR: 0x03F34) Bit name P4DIR7-0 At reset Access Bit name...
  • Page 202 Chapter 7 I/O Port Port 6 Direction Control Register (P6DIR: 0x03F36) Bit name P6DIR7-0 At reset Access Bit name Description I/O mode selection 0: Intput mode P6DIR7-0 1: Output mode Port 7 Direction Control Register (P7DIR: 0x03F37) Bit name P7DIR7-0 At reset Access Bit name...
  • Page 203: Port N Pull-Up Resistor Control Registers

    Chapter 7 I/O Port 7.2.4 Port n Pull-up Resistor Control Registers PnPLU is the register to control the pull-up resistor addition to I/O. Port 0 Pull-up Resistor Control Register (P0PLUP: 0x03F40) Bit name P0PLU7-0 At reset Access Bit name Description Pull-up resistor selection P0PLU7-0 0: Not added...
  • Page 204 Chapter 7 I/O Port Port 3 Pull-up Resistor Control Register (P3PLUP: 0x03F43) Bit name P3PLU7-0 At reset Access Bit name Description Pull-up resistor selection P3PLU7-0 0: Not added 1: Added Port 4 Pull-up Resistor Control Register (P4PLUP: 0x03F44) Bit name P4PLU7-0 At reset Access...
  • Page 205 Chapter 7 I/O Port Port 6 Pull-up Resistor Control Register (P6PLUP: 0x03F46) Bit name P6PLU7-0 At reset Access Bit name Description Pull-up resistor selection P6PLU7-0 0: Not added 1: Added Port 7 Pull-up Resistor Control Register (P7PLUP: 0x03F47) Bit name P7PLU7-0 At reset Access...
  • Page 206: Port N N-Ch Open-Drain Control Registers

    Chapter 7 I/O Port 7.2.5 Port n N-ch Open-drain Control Registers PnODC is the register to control N-ch open-drain control of I/O. Port 0 N-ch Open-drain Control Register (P0ODC: 0x03F50) Bit name P0ODC7 P0ODC5-4 At reset Access Bit name Description N-ch open-drain output selection P0ODC7 0: Push-pull output...
  • Page 207 Chapter 7 I/O Port Port 2 N-ch Open-drain Control Register (P2ODC: 0x03F52) Bit name P2ODC5-3 At reset Access Bit name Description Always read as 0. N-ch open-drain output selection P2ODC5-3 0: Push-pull output 1: N-ch open-drain output Always read as 0. Port 3 N-ch Open-drain Control Register (P3ODC: 0x03F53) Bit name P3ODC7-6...
  • Page 208 Chapter 7 I/O Port Port 4 N-ch Open-drain Control Register (P4ODC: 0x03F54) Bit name P4ODC7-6 P4ODC4-2 P4ODC0 At reset Access Bit name Description N-ch open-drain output selection P4ODC7-6 0: Push-pull output 1: N-ch open-drain output Always read as 0. N-ch open-drain output selection P4ODC4-2 0: Push-pull output 1: N-ch open-drain output...
  • Page 209 Chapter 7 I/O Port Port 6 N-ch Open-drain Control Register (P6ODC: 0x03F56) Bit name P6ODC7-5 At reset Access Bit name Description N-ch open-drain output selection P6ODC7-5 0: Push-pull output 1: N-ch open-drain output Always read as 0. Control Registers VII - 21...
  • Page 210: Port N N-Ch Drive Strength Selection Registers

    Chapter 7 I/O Port 7.2.6 Port n N-ch Drive Strength Selection Registers PnNLC is the register to select the drive strength of Nch output transistor of I/O. Port 0 N-ch Current Capacity Selection Register (P0NLC: 0x03EC0) Bit name P0NLC7-0 At reset Access Bit name Description...
  • Page 211 Chapter 7 I/O Port Port 4 N-ch Current Capacity Selection Register (P4NLC: 0x03EC3) Bit name P4NLC7-0 At reset Access Bit name Description N-ch current capacity selection P4NLC7-0 0: normal current capacity (2mA) 1: Large current capacity (8mA) Port 5 N-ch Current Capacity Selection Register (P5NLC: 0x03EC4) Bit name P5NLC7-0 At reset...
  • Page 212 Chapter 7 I/O Port Port 6 N-ch Current Capacity Selection Register (P6NLC: 0x03EC5) Bit name P6NLC7-0 At reset Access Bit name Description N-ch current capacity selection P6NLC7-0 0: normal current capacity (2mA) 1: Large current capacity (8mA) Port 7 N-ch Current Capacity Selection Register (P7NLC: 0x03EC6) Bit name P7NLC7-0 At reset...
  • Page 213: 8-Bit Timer Output Control Register

    Chapter 7 I/O Port 7.2.7 8-bit Timer output control Register 8-bit Timer output control register selects the pin function (General IO (GIO) or 8-bit Timer output). 8-bit Timer output control Register (TMIOEN0: 0x03F2C) Bit name TM5OEN TM4OEN TM3OEN TM2OEN TM1OEN TM0OEN At reset Access...
  • Page 214: 8-Bit Timer Input/Output Pins Selection Register

    Chapter 7 I/O Port 7.2.8 8-bit Timer input/output pins selection Register 8-bit Timer input/output pins selection register selects the pin of Timer8 (TMnIOA or TMnIOB). 8-bit Timer input/output pins selection Register (TMIOSEL0: 0x03F2D) Bit name IOSEL IOSEL IOSEL IOSEL IOSEL IOSEL At reset Access...
  • Page 215: 16-Bit Timer Output Control Register

    Chapter 7 I/O Port 7.2.9 16-bit Timer output control Register 16-bit Timer output control register selects the pin function (General IO (GIO) or 16-bit Timer output). 16-bit Timer output control Register (TMIOEN1: 0x03F2E) Bit name TM9OEN TM8OEN TM7OEN At reset Access Bit name Description...
  • Page 216: 16-Bit Timer Input/Output Pin Selection Register

    Chapter 7 I/O Port 7.2.10 16-bit Timer input/output pin selection Register 16-bit Timer input/output pin selection register selects the output pin of 16-bit Timer (TMnIOA to TMnIOC). 16-bit Timer input/output pin selection Register (TMIOSEL1: 0x03F2F) Bit name TM9IOSEL1-0 TM8IOSEL1-0 TM7IOSEL1-0 At reset Access Bit name...
  • Page 217: Clock Output / Clock Output Pin Control Register

    Chapter 7 I/O Port 7.2.11 Clock output / Clock output pin control Register Clock output / Clock output pin control register selects output clock and changes between General IO (GIO) and clock output. Clock output / Clock output pin control Register (CLKOUT: 0x03F3E) CLKO Bit name CLKOCNT1-0...
  • Page 218: Analog Input Control Register 0 (Port1)

    Chapter 7 I/O Port 7.2.12 Analog input Control Register 0 (Port1) Analog input control register selects the pin function (General IO (GIO) or A/D input). Analog Input Control Register 0 (Port 1) (ANEN0: 0x03F5C) Bit name ANEN07-0 At reset Access Bit name Description Select the pin function (GIO or A/D input)
  • Page 219: Analog Input Control Register 1 (Port8)

    Chapter 7 I/O Port 7.2.13 Analog input Control Register 1 (Port8) Analog input control register 1 selects the pin function (General IO (GIO) or Analog input). Analog Input Control Register 1 (ANEN1: 0x03F5D) Bit name ANEN15 ANEN14 ANEN13 ANEN12 ANEN11 ANEN10 At reset Access...
  • Page 220: Buzzer Output / Buzzer Output Pin Control Register

    Chapter 7 I/O Port 7.2.14 Buzzer output / Buzzer output pin control Register Buzzer output / Buzzer output pin control register selects the pin function (General IO (GIO) or Buzzer output) and selects the output pin of BUZ/NBUZ (BUZA or BUZB / NBUZA or NBUZB) Buzzer output / Buzzer output pin control Register (BUZCNT: 0x03F5F) Bit name NBUZEN...
  • Page 221: I/O Port Functions

    Chapter 7 I/O Port 7.3 I/O Port Functions Each I/O can be used as a general purpose port, which is controlled with PnOUT, PnIN, PnDIR, PnPLU, PnODC and PnNLC registers. Each port also has a special function, the detail of which is described after [7.4 Port 0]. The assignment and selection of LCD control pins (SEGn and COMn) differ in each product.
  • Page 222: Port 0

    Chapter 7 I/O Port 7.4 Port 0 The following table shows the special functions of Port 0. Table:7.4.1 Port 0 Special function TM9IOC TM4IOB TM2IOB TM8IOC BUZB TM0IOB TM7IOC NBUZB SBO3A SDA3A TM7IOA SBT3A SCL3A TM0IOA TM2IOA CLKOUTA SBI3A TM8IOB SBCS3A TM9IOA 7.4.1...
  • Page 223 Chapter 7 I/O Port Table:7.4.4 P02 Function Selection Setup Function Register TMIOEN0 TM2MD TMIOSEL0 TMIOEN1 TM8MD1 TMIOSEL1 BUZCNT TM8IOSEL Bit name TM2OEN TM2CK1-0 TM2IOSEL TM8OEN TM8CK1-0 BUZEN BUZSEL Other than Other than TM2IO (output) Other than TM2IO (input) Other than TM8IO (output) Other than TM8IO (input)
  • Page 224 Chapter 7 I/O Port Table:7.4.7 P05 Function Selection Setup Function Register SC3MD1 SC23SEL TM0MD TMIOEN0 TM2MD TMIOEN0 TMIOSEL0 CLKOUT TM0IOSE/ CLKOEN/ Bit name SC3SBTS SC3SEL2 TM0CK1-0 TM0OEN TM2CK1-0 TM2OEN TM2IOSEL CLKOSEL Other than Other than 1 (*1) SBT3A/SCL3A Other than Other than TM0IO (output) Other than...
  • Page 225: Setup Of Port 1

    Chapter 7 I/O Port 7.5 Port 1 The following table shows the special functions of Port 1. Table:7.5.1 Port 1 Special function IRQ0A KEY0A IRQ1A KEY1A IRQ4C KEY2A IRQ5C KEY3A IRQ4A KEY4A IRQ5A KEY5A IRQ6A KEY6A KEY7A 7.5.1 Setup of Port 1 Table:7.5.2 P10 Function Selection Setup Function...
  • Page 226 Chapter 7 I/O Port Table:7.5.4 P12 Function Selection Setup Function Register ANEN0 IRQIEN IRQISEL1 KEYIEN KEYSEL Bit name ANEN02 IRQI4EN IRQ4CSEL KEYI2EN KEY2SEL IRQ4C KEY2A Table:7.5.5 P13 Function Selection Setup Function Register ANEN0 IRQIEN IRQISEL1 KEYIEN KEYSEL Bit name ANEN03 IRQI5EN IRQ5CSEL KEYI3EN...
  • Page 227 Chapter 7 I/O Port Table:7.5.8 P16 Function Selection Setup Function Register ANEN0 IRQIEN IRQISEL0 KEYIEN KEYSEL Bit name ANEN06 IRQI6EN IRQ6SEL KEYI6EN KEY6SEL IRQ6A KEY6A Table:7.5.9 P17 Function Selection Setup Function Register ANEN0 KEYIEN KEYSEL Bit name ANEN07 KEYI7EN KEY7SEL KEY7A Port 1 VII - 39...
  • Page 228 Chapter 7 I/O Port 7.6 Port 2 The following table shows the special functions of Port 2. Table:7.6.1 Port 2 Special function SEG42 (*) TM1IOB TM9IOB SEG41 (*) TM5IOA SEG40 (*) SBI2B SEG39 (*) SBO2B SDA2B SEG38 (*) SBT2B SCL2B SEG37 (*) SBCS2B SEG36 (*)
  • Page 229 Chapter 7 I/O Port Table:7.6.3 P21 Function Selection Setup Function Register LCCTR5 TMIOEN0 TM5MD TMIOSEL5 Bit name SEGSL41 TM5OEN TM5CK1-0 TM5IOSEL SEG41 Other than 11 TM5IO (output) TM5IO (input) Other than 11 Table:7.6.4 P22 Function Selection Setup Function Register LCCTR5 SC2MD1 SC23SEL Bit name...
  • Page 230 Chapter 7 I/O Port Table:7.6.7 P25 Function Selection Setup Function Register LCCTR5 SC2MD2 SC23SEL Bit name SEGSL37 SC2SBCSEN SC2SEL3 SEG37 SBCS2B *1 When the LSI outputs the chip select signal, set the P2DIR.P2DIR5 to "1". Table:7.6.8 P26 Function Selection Setup Function Register LCCTR5...
  • Page 231: Setup Of Port 2

    Chapter 7 I/O Port 7.7 Port 3 The following table shows the special functions of Port 3. Table:7.7.1 Port 3 Special function SEG35 (*) SBO1A TXD1A SEG34 (*) SBT1A SEG33 (*) SBCS1A SEG32 (*) BUZA SEG31 (*) TM4IOA TM7IOB NBUZA SEG30 (*) SBI0B RXD0B...
  • Page 232 Chapter 7 I/O Port Table:7.7.3 P31 Function Selection Setup Function Register LCCTR4 SC1MD1 SC01SEL Bit name SEGSL34 SC1SBTS SC1SEL2 SEG34 1 (*1) SBT1A *1 When the LSI is the master of Clock-synchronous communication or communicates on IIC bus, set the P3DIR.P3DIR1 to "1". Table:7.7.4 P32 Function Selection Setup Function...
  • Page 233 Chapter 7 I/O Port Table:7.7.7 P35 Function Selection Setup Function Register LCCTR4 SC0MD1 SC01SEL Bit name SEGSL30 SC0SBIS SC0IOM SC0SEL0 SEG30 SBI0B/RXD0B Table:7.7.8 P36 Function Selection Setup Function Register LCCTR4 SC0MD1 SC01SEL Bit name SEGSL29 SC0SBOS SC0SBIS SC0IOM SC0SEL1 SEG29 1 (*1) - (*2) - (*2)
  • Page 234 Chapter 7 I/O Port 7.8 Port 4 The following table shows the special functions of Port 4. Table:7.8.1 Port 4 Special function SEG27 (*) SBCS0B SEG26 (*) SBI2A SEG25 (*) SBO2A SDA2A SEG24 (*) SBT2A SCL2A SEG23 (*) SBCS2A SEG22 (*) SBI1B RXD1B SEG21 (*)
  • Page 235 Chapter 7 I/O Port Table:7.8.4 P42 Function Selection Setup Function Register LCCTR3 SC2MD1 SC23SEL Bit name SEGSL25 SC2SBOS SC2SBIS SC2IOM SC2SEL1 SEG25 1 (*1) - (*2) - (*2) SBO2A/ SDA2A *1 When serial data is output, set the P4DIR.P4DIR2 to "1". *2 When serial data is input and output, set the bit to "1".
  • Page 236 Chapter 7 I/O Port Table:7.8.8 P46 Function Selection Setup Function Register LCCTR3 SC1MD1 SC01SEL Bit name SEGSL21 SC1SBOS SC1SBIS SC1IOM SC1SEL1 SEG21 1 (*1) - (*2) - (*2) SBO1B/ TXD1B *1 When serial data is output, set the P4DIR.P4DIR6 to "1". *2 When serial data is input and output, set the bit to "1".
  • Page 237 Chapter 7 I/O Port 7.9 Port 5 The following table shows the special functions of Port 5. Table:7.9.1 Port 5 Special function SEG19 (*) SBCS1B SEG18 (*) SBI3B SEG17 (*) SBO3B SDA3B SEG16 (*) SBT3B SCL3B SEG15 (*) KEY0B SBCS3B SEG14 (*) KEY1B TM1IOA...
  • Page 238 Chapter 7 I/O Port Table:7.9.4 P52 Function Selection Setup Function Register LCCTR2 SC3MD1 SC23SEL Bit name SEGSL17 SC3SBOS SC3SBIS SC3IOM SC3SEL1 SEG17 1 (*1) - (*2) - (*2) SBO3B/ SDA3B *1 When serial data is output, set the P5DIR.P5DIR2 to "1". *2 When serial data is input and output, set the bit to "1".
  • Page 239 Chapter 7 I/O Port Table:7.9.8 P56 Function Selection Setup Function Register LCCTR2 KEYIEN KEYSEL TMIOEN0 TM3MD TMIOSEL0 Bit name SEGSL13 KEYI2EN KEY2SEL TM3OEN TM3CK1-0 TM3IOSEL SEG13 Other than 11 KEY2B Other than 11 TM3IO (output) TM3IO (input) Other than 11 Table:7.9.9 P57 Function Selection Setup Function...
  • Page 240: Setup Of Port 6

    Chapter 7 I/O Port 7.10 Port 6 The following table shows the special functions of Port 6. Table:7.10.1 Port 6 Special function SEG11 (*) IRQ0B SEG10 (*) IRQ1B SEG9 (*) IRQ2B SEG8 (*) IRQ3B SEG7 (*) KEY4B SBI0A RXD0A SEG6 (*) KEY5B SBO0A TXD0A...
  • Page 241 Chapter 7 I/O Port Table:7.10.4 P62 Function Selection Setup Function Register LCCTR1 IRQIEN IRQISEL0 Bit name SEGSL9 IRQI2EN IRQ2SEL SEG9 IRQ2B Table:7.10.5 P63 Function Selection Setup Function Register LCCTR1 IRQIEN IRQISEL0 Bit name SEGSL8 IRQI3EN IRQ3SEL SEG8 IRQ3B Table:7.10.6 P64 Function Selection Setup Function Register...
  • Page 242 Chapter 7 I/O Port Table:7.10.8 P66 Function Selection Setup Function Register LCCTR1 KEYIEN KEYSEL SC0MD1 SC01SEL Bit name SEGSL5 KEYI6EN KEY6SEL SC0SBTS SC0SEL2 SEG5 KEY6B 1 (*1) SBT0A *1 When the LSI is the master of Clock-synchronous communication, set the P6DIR.P6DIR6 to "1". Table:7.10.9 P67 Function Selection Setup Function...
  • Page 243: Setup Of Port 7

    Chapter 7 I/O Port 7.11 Port 7 The following table shows the special functions of Port 7. Table:7.11.1 Port 7 Special function COM7 (*) SEG3 (*) IRQ6B COM6 (*) SEG2 (*) IRQ5B COM5 (*) SEG1 (*) IRQ4B TM3IOB COM4 (*) SEG0 (*) TM5IOB COM3 (*)
  • Page 244 Chapter 7 I/O Port Table:7.11.4 P72 Function Selection Setup Function Register LCCTR0 LCDSEL IRQIEN IRQISEL0 TMIOEN0 TM3MD TMIOSEL0 Bit name SEGSL1 COMSL5 IRQI4EN IRQ4SEL TM3OEN TM3CK1-0 TM3IOSEL COM5 SEG1 Other than IRQ4B Other than TM3IO (output) TM3IO (input) Other than Table:7.11.5 P73 Function Selection Setup Function...
  • Page 245 Chapter 7 I/O Port Table:7.11.8 P76 Function Selection Setup Function Register LCCTR0 Bit name COMSL1 COM1 Table:7.11.9 P77 Function Selection Setup Function Register LCCTR0 Bit name COMSL0 COM0 Port 7 VII - 57...
  • Page 246: Setup Of Port 8

    Chapter 7 I/O Port 7.12 Port 8 The following table shows the special functions of Port 8. Table:7.12.1 Port 8 Special function OSC1 IRQ2A OSC2 IRQ3A VLC3 VLC2 7.12.1 Setup of Port 8 Function setup of Port 8 is shown below. Table:7.12.2 P80 Function Selection Setup Function...
  • Page 247 Chapter 7 I/O Port Table:7.12.4 P82 Function Selection Setup Function Register ANEN1 Bit name ANEN12 Table:7.12.5 P83 Function Selection Setup Function Register ANEN1 Bit name ANEN13 Table:7.12.6 P84 Function Selection Setup Function Register ANEN1 Bit name ANEN14 VLC3 Table:7.12.7 P85 Function Selection Setup Function Register...
  • Page 248 Chapter 7 I/O Port VII - 60 Port 8...
  • Page 249: Chapter 8 8-Bit Timer

    VIII.. Chapter 8 8-bit Timer...
  • Page 250: Overview

    Chapter 8 8-bit Timer 8.1 Overview This LSI has six 8-bit timers (Timer 0 to Timer 5). I/O pins used for each 8-bit Timer has three pin groups, Group-A and Group-B. (ex. Timer 0 has TM0IOA and TM0IOB.) In this chapter, the suffix of "A" and "B" is omitted to describe functions of 8-bit Timer. 8.1.1 Functions Table:8.1.1 shows functions that can be used for each timer.
  • Page 251: 8-Bit Timer Block Diagram

    Chapter 8 8-bit Timer 8.1.2 8-bit Timer Block Diagram 8-bit Timer block diagram is shown in Figure:8.1.1 Timer 0, Timer 2 and Timer 4 are described "Timer n", Timer 1, Timer 3 and Timer 5 are described "Timer m". HCLK HCLK/4 TMmOC register HCLK/16...
  • Page 252: 8-Bit Timer Control Registers

    Chapter 8 8-bit Timer 8.2 8-bit Timer Control Registers 8-bit Timer control registers consist of following registers. - Timer prescaler selection registers - Programmable timer registers - Timer mode registers Table:8.2.1 shows registers that control 8-bit Timers. Table:8.2.1 8-bit Timer Control Registers Symbol Address Register Name...
  • Page 253: Timer Prescaler Selection Registers

    Chapter 8 8-bit Timer 8.2.1 Timer Prescaler Selection Registers The timer prescaler selection registers select divided HCLK or SYSCLK as the count clock of 8-bit timer. In addi- tion, these registers control the function of PWM output with additional pulses for Timer 0, 2 and 4. Timer 0 Prescaler Selection Register (CK0MD: 0x03F76) Bit name TM0ADD1-0...
  • Page 254 Chapter 8 8-bit Timer Timer 2 Prescaler Selection Register (CK2MD: 0x03F86) Bit name TM2ADD1-0 TM2ADDEN TM2PSC1-0 TM2BAS At reset Access Bit name Description 7 to 6 Always read as 0. Position of additional pulse (within 4 cycles of PWM basic waveform) 00: No pulse 5 to 4 TM2ADD1-0...
  • Page 255 Chapter 8 8-bit Timer Timer 4 Prescaler Selection Register (CK4MD: 0x03F96) Bit name TM4ADD1-0 TM4ADDEN TM4PSC1-0 TM4BAS At reset Access Bit name Description 7 to 6 Always read as 0. Position of additional pulse (within 4 cycles of PWM basic waveform) 00: No pulse 5 to 4 TM4ADD1-0...
  • Page 256: Programmable Timer Registers

    Chapter 8 8-bit Timer 8.2.2 Programmable Timer Registers The programmable timer register consists of timer n compare register (TMnOC) and timer n binary counter (TMnBC). Timer n Compare Register (TM0OC: 0x03F72, TM1OC: 0x03F73, TM2OC: 0x03F82, TM3OC: 0x03F83, TM4OC: 0x03F92, TM5OC: 0x03F93) Timer n compare register is an 8-bit register which stores a value compared with timer n binary counter.
  • Page 257: Timer Mode Registers

    Chapter 8 8-bit Timer 8.2.3 Timer Mode Registers Timer 0 Mode Register (TM0MD: 0x03F74) Bit name TM0POP TM0MOD TM0PWM TM0EN TM0CK1-0 At reset Access Bit name Description Always read as 0. Initial polarity of output signal select TM0POP 0: Timer output Low→High, PWM High→Low 1: Timer output High→Low, PWM Low→High Pulse width measurement control TM0MOD...
  • Page 258 Chapter 8 8-bit Timer Timer 1 Mode Register (TM1MD: 0x03F75) Bit name TM1CAS TM1EN TM1CK1-0 At reset Access Bit name Description Always read as 0. Timer 1 operation mode select TM1CAS 0: Normal timer operation 1: Cascade connection Timer 1 count enable TM1EN 0: Disabled 1: Enabled...
  • Page 259 Chapter 8 8-bit Timer Timer 2 Mode Register (TM2MD: 0x03F84) Bit name TM2POP TM2MOD TM2PWM TM2EN TM2CK1-0 At reset Access Bit name Description Always read as 0. Initial polarity of output signal select TM2POP 0: Timer output Low→High, PWM High→Low 1: Timer output High→Low, PWM Low→High Pulse width measurement control TM2MOD...
  • Page 260 Chapter 8 8-bit Timer Timer 3 Mode Register (TM3MD: 0x03F85) Bit name TM3CAS TM3EN TM3CK1-0 At reset Access Bit name Description Always read as 0. Timer 3 operation mode select TM3CAS 0: Normal timer operation 1: Cascade connection Timer 3 count enable TM3EN 0: Disabled 1: Enabled...
  • Page 261 Chapter 8 8-bit Timer Timer 4 Mode Register (TM4MD: 0x03F94) Bit name TM4POP TM4MOD TM4PWM TM4EN TM4CK1-0 At reset Access Bit name Description Always read as 0. Initial polarity of output signal select TM4POP 0: Timer output Low→High, PWM High→Low 1: Timer output High→Low, PWM Low→High Pulse width measurement control TM4MOD...
  • Page 262 Chapter 8 8-bit Timer Timer 5 Mode Register (TM5MD: 0x03F95) Bit name TM5CAS TM5EN TM5CK1-0 At reset Access Bit name Description Always read as 0. Timer 5 operation mode select TM5CAS 0: Normal timer operation 1: Cascade connection Timer 5 count enable TM5EN 0: Disabled 1: Enabled...
  • Page 263: 8-Bit Timer

    Chapter 8 8-bit Timer 8.3 8-bit Timer 8.3.1 Operation In the 8-bit timer operation, the timer can generate interrupts periodically. 8-bit Timer Operation (Timer 0 to Timer 5) The interrupt generation cycle of the timer is determined by selecting the clock source and setting the value of TMnOC, in advance.
  • Page 264 Chapter 8 8-bit Timer Count Timing of Timer Operation (Timer 0 to Timer 5) The binary counter counts up with the selected count clock, as shown below. This is the basic operation for all functions of 8-bit timer. Count Clock TMnEN Internal enable...
  • Page 265 Chapter 8 8-bit Timer Stop the timer when switching the count clock. If the count clock is changed during counting, the timer doesn't count correctly . Do not change the TMnMD.TMnEN simultaneously with other bits to avoid errors in opera- tion.
  • Page 266 Chapter 8 8-bit Timer When changing the CPU operation mode (from NORMAL to SLOW) while the high-fre- quency oscillation clock (HCLK) or the prescaler output (TMnPSC) is selected as a clock source, stop the timer before the mode transition. After the mode transition, activate the timer again.
  • Page 267: Setup Example

    Chapter 8 8-bit Timer 8.3.2 Setup Example Timer Operation Setup Example (Timer 0 to Timer 5) Here is an example that the periodic interrupt of Timer 0 is generated to execute the timer function. An interrupt is generated every 250 cycles (200 µs) by selecting SYSCLK/2 (at f = 2.5 MHz operation) as a clock source.
  • Page 268: 8-Bit Event Count

    Chapter 8 8-bit Timer 8.4 8-bit Event Count 8.4.1 Operation In the event count operation, an external input, as a count clock, can be counted. 8-bit Event Count Operation In the event count operation, TMnBC counts the input signal to the TMnIO pin from the external. When the value of TMnBC matches the setting value of timer n compare register, an interrupt request is generated at the next count clock.
  • Page 269 Chapter 8 8-bit Timer When TMnBC is read on the operation, uncertain value on counting up may be read. Writing the value to TMnOC during counting is prohibited. The sampled signal of the TMnMD.TMnEN with the count clock controls start/stop of the binary counter of 8-bit timer on this LSI.
  • Page 270: 8-Bit Event Count Setup Example

    Chapter 8 8-bit Timer 8.4.2 8-bit Event Count Setup Example Event Count Setup Example Here is an example that an interrupt is generated by detecting the falling edge of the TM0IO input 5 times. The setup procedure and the description of each step are shown below. Step Setting Register...
  • Page 271: 8-Bit Timer Pulse Output

    Chapter 8 8-bit Timer 8.5 8-bit Timer Pulse Output 8.5.1 Operation Operation of Timer Pulse Output In the timer pulse output function, a pulse signal with a given frequency can be output from TMnIO pin. Timers can output the signal with twice the cycle which is set in TMnOC. Refer to Table:8.1.1 for the pulse output pin. Count Timing of Timer Pulse Output Count clock...
  • Page 272: Setup Example

    Chapter 8 8-bit Timer 8.5.2 Setup Example Timer Pulse Output Setup Example Here is an example that a 50 kHz pulse is output from TM0IO pin of Timer 0. In order to output a 50 kHz pulse, select SYSCLK/2 for clock source, and set 1/2 cycle (100 kHz) in the Timer 0 compare register (at f = 10 sysclk MHz).
  • Page 273: 8-Bit Pwm Output

    Chapter 8 8-bit Timer 8.6 8-bit PWM Output 8.6.1 Operation (Timer 0, Timer 2 and Timer 4) 8-bit PWM Output Operation Timer 0, Timer 2 and Timer 4 have PWM function. a PWM waveform with a given duty cycle is generated by set- ting TMnOC to "High"...
  • Page 274 Chapter 8 8-bit Timer Count Timing of PWM Output (when the compare register is "0x00") Count clock TMnEN Compare register Binary N+1 N+2 counter TMnIO output (PWM output) Figure:8.6.2 Count Timing of PWM Output (when the compare register is "0x00") Count Timing of PWM Output (when the compare register is "0xFF") Count clock...
  • Page 275: Setup Example

    Chapter 8 8-bit Timer 8.6.2 Setup Example PWM Output Setup Example The PWM output waveform with the 1/4 duty cycle and 19.53 kHz is output from TM0IO output pin of Timer 0. The oscillation of SYSCLK/2 is 5 MHz. The setup procedure and the description of each step are shown below. TM0IO output 19.53 kHz Figure:8.6.4 Output Waveform of TM0IO Output Pin...
  • Page 276: Pwm Output With Additional Pulse (Timer 0, Timer 2, Timer 4)

    Chapter 8 8-bit Timer 8.6.3 PWM Output With Additional Pulse (Timer 0, Timer 2, Timer 4) PWM Output with Additional Pulse Method In this method, a pulse, whose period equals to one count clock period, can be added on a PWM basic waveform. Up to 3 pulses can be added in 4 cycles of the basic PWM waveform.
  • Page 277: Simple Pulse Width Measurement

    Chapter 8 8-bit Timer 8.7 Simple Pulse Width Measurement 8.7.1 Operation (Timer 0, Timer 2 and Timer 4) Simple Pulse Width Measurement Operation by 8-bit Timer The input signal from an external interrupt pin (for the simple pulse width measurement) is sampled at the count clock.
  • Page 278: Setup Example

    Chapter 8 8-bit Timer 8.7.2 Setup Example Setup Example of Simple Pulse Width Measurement by 8-bit Timer Here is an example that Timer 0 measures "Low" pulse width of the input signal of IRQ0. SYSCLK/2 is selected as a clock source for Timer 0. The setup procedure and the description of each step are shown below.
  • Page 279: Operation

    Chapter 8 8-bit Timer 8.8 8-bit Timer Cascade Connection 8.8.1 Operation 16-bit timers in cascade connection are the combination of the following 8-bit timers. Timer 0 connected with Timer 1, Timer 2 connected with Timer3 , or Timer 4 connected with Timer 5 operates as a 16-bit timer in cascade connection.
  • Page 280 Chapter 8 8-bit Timer The binary counters and the compare registers corresponding to two timers in cascade connection operate as a 16- bit register, respectively. When activating the timer, set the TMnMD.TMnEN for lower 8-bit timer to "1". A waveform of the timer pulse and an interrupt request is output from the upper 8-bit timer. Select the clock source with the register for the lower 8-bit timer.
  • Page 281 Chapter 8 8-bit Timer 8.8.2 Setup Example Timer Operation Setup Example of 16-bit Cascade Connection Here is an example of the timer function that the 16-bit timer, Timer 0 connected with Timer 1 in cascade connec- tion, generates a periodic interrupt. An interrupt occurs every 2500 cycles (1 ms) by selecting SYSCLK/2 (at f = 5 MHz) as a clock source.
  • Page 282 Chapter 8 8-bit Timer VIII - 34 8-bit Timer Cascade Connection...
  • Page 283: Chapter 9 16-Bit Timer

    IX.. Chapter 9 16-bit Timer...
  • Page 284: Overview

    Chapter 9 16-bit Timer 9.1 Overview Table:9.1.1 shows the functions of 16-bit Timer. Table:9.1.1 16-bit Timer Functions Timer 7 (TM7) Timer 8 (TM8) Timer 9 (TM9) TM7IRQ TM8IRQ TM9IRQ Interrupt source TM7OC2IRQ TM8OC2IRQ TM9OC2IRQ √ √ √ Timer operation Event count TM7IOA (P04) TM8IOA (P57) TM9IOA (P07)
  • Page 285 Chapter 9 16-bit Timer 16-bit Timer n Block Diagram (n = 7, 8 and 9) 16bit Capture Register (TMnICH, TMnICL) 16bit Preset Register1 (TMnPR1H, TMnPR1L) HCLK HCLK/2 HCLK/4 16bit Compaer Register1 (TMnOC1H, TMnOC1L) HCLK/16 SYSCLK TMnIRQ Match detection SYSCLK/2 SYSCLK/4 Timer/PWM output generation SYSCLK/16 16bit Bynary Counter...
  • Page 286: 16-Bit Timer Control Registers

    Chapter 9 16-bit Timer 9.2 16-bit Timer Control Registers Table:9.2.1 shows the registers that control 16-bit timer. Table:9.2.1 16-bit Timer Control Registers Symbol Address Register Name Page TM7BCL 0x03FA0 Timer 7 binary counter (lower 8 bits) IX-8 TM7BCH 0x03FA1 Timer 7 binary counter (upper 8 bits) IX-8 TM7OC1L 0x03FA2...
  • Page 287 Chapter 9 16-bit Timer Symbol Address Register Name Page TM9BCL 0x03FC0 Timer 9 binary counter (lower 8 bits) IX-8 TM9BCH 0x03FC1 Timer 9 binary counter (upper 8 bits) IX-8 TM9OC1L 0x03FC2 Timer 9 compare register 1 (lower 8 bits) IX-6 TM9OC1H 0x03FC3 Timer 9 compare register 1 (upper 8 bits)
  • Page 288: Programmable Timer Registers

    Chapter 9 16-bit Timer 9.2.1 Programmable Timer Registers Programmable timer registers must be accessed with 16-bit access instruction. Compare registers are 16-bit registers for storing the values compared with binary counters. These registers are loaded with the comparing data stored in preset registers in advance. Timer n Compare Register 1 (Lower 8 bits) (TM7OC1L: 0x03FA2, TM8OC1L: 0x03FB2, TM9OC1L: 0x03FC2) Bit name...
  • Page 289 Chapter 9 16-bit Timer Preset registers are buffer registers for compare registers. When writing data to the preset register while the counting is stopped, the same data is loaded to the compare reg- ister. When writing data to the preset register while counting, the data of preset register is loaded to the compare register at the timing when the binary counter is cleared.
  • Page 290 Chapter 9 16-bit Timer Binary counters are 16-bit up counters. If data is written to the preset register 1 (TMnPR1L to TMnPR1H) while the counting is stopped, the binary counter is cleared to "0x0000". For Timer 7, the binary counters are cleared to "0x0000" while IGBT operation is disabled at IGBT setting. The binary counters for Timer 7 and 8 can be cleared to "0x0000"...
  • Page 291 Chapter 9 16-bit Timer Timer 7 dead time preset register 1 and 2 are buffer registers of dead time compare registers. Timer 7 Dead Time Preset Register 1 (TM7DPR1: 0x03FAE) TM7DPR1 TM7DPR1 TM7DPR1 TM7DPR1 TM7DPR1 TM7DPR1 TM7DPR1 TM7DPR1 Bit name At reset Access Timer 7 Dead Time Preset Register 2 (TM7DPR2: 0x03FAF)
  • Page 292: Timer Mode Registers

    Chapter 9 16-bit Timer 9.2.2 Timer Mode Registers Timer 7 Mode Register 1 (TM7MD1: 0x03FA8) Bit name T7ICEDG1 TM7CL TM7EN TM7PS1-0 TM7CK1-0 At reset Access Bit name Description Always read as 0. Select capture trigger edge T7ICEDG1 0: Falling edge 1: Rising edge Timer output enable TM7CL...
  • Page 293 Chapter 9 16-bit Timer Timer 7 Mode Register 2 (TM7MD2: 0x03FA9) Bit name T7ICEDG0 T7PWMSL TM7BCR TM7PWM TM7IRS1 T7ICEN T7ICT1-0 At reset Access Bit name Description Select capture trigger edge T7ICEDG0 0: Both edges 1: Specified edge Select PWM mode T7PWMSL 0: Set duty through TM7OC1 1: Set duty through TM7OC2...
  • Page 294 Chapter 9 16-bit Timer Timer 7 Mode Register 3 (TM7MD3: 0x03FBE) TM7CK TM7CK Bit name T7IGBTTR T7IGBTDT T7IGBTEN T7IGBT1-0 At reset Access Bit name Description Select sampling clock for capture TM7CKSMP 0: Count clock 1: SYSCLK Always read as 0. Select count edge of TM7IO TM7CKEDG 0: Falling edge...
  • Page 295 Chapter 9 16-bit Timer Timer 7 Mode Register 4 (TM7MD4: 0x03F9E) T7ONE T7CAP Bit name T7NODED T7ICT2 SHOT At reset Access Bit name Description Always read as 0. Select pulse T7ONESHOT 0: Continuous pulse 1: One-shot pulse Set dead time T7NODED 0: Yes 1: No...
  • Page 296 Chapter 9 16-bit Timer Timer 8 Mode Register 1 (TM8MD1: 0x03FB8) Bit name T8ICEDG1 TM8CL TM8EN TM8PS1-0 TM8CK1-0 At reset Access Bit name Description Always read as 0. Select capture trigger edge T8ICEDG1 0: Falling edge 1: Rising edge Timer output enable TM8CL 0: Enabled 1: Disabled (reset)
  • Page 297 Chapter 9 16-bit Timer Timer 8 Mode Register 2 (TM8MD2: 0x03FB9) Bit name T8ICEDG0 T8PWMSL TM8BCR TM8PWM TM8IRS1 T8ICEN T8ICT1-0 At reset Access Bit name Description Select capture trigger edge T8ICEDG0 0: Both edges 1: Specified edge Select PWM mode T8PWMSL 0: Set duty through TM8OC1 1: Set duty through TM8OC2...
  • Page 298 Chapter 9 16-bit Timer Timer 8 Mode Register 3 (TM8MD3: 0x03FBF) TM8CK TM8CK Bit name TM8SEL TM8PWMF TM8PWMO At reset Access Bit name Description Select sampling clock for capture TM8CKSMP 0: Count clock 1: SYSCLK Always read as 0. Select count edge of TM8IO TM8CKEDG 0: Falling edge 1: Both edges...
  • Page 299 Chapter 9 16-bit Timer Timer 8 Mode Register 4 (TM8MD4: 0x03F9F) Bit name T8ICT2 T8CAPCLR At reset Access Bit name Description Always read as 0. Select capture trigger T8ICT2 0: Timer 0 interrupt 1: Timer 1 interrupt Binary counter clear enable at capture T8CAPCLR 0: Disabled (not cleared) 1: Enabled (cleared)
  • Page 300 Chapter 9 16-bit Timer Timer 9 Mode Register 1 (TM9MD1: 0x03FC8) Bit name T9ICEDG1 TM9CL TM9EN TM9PS1-0 TM9CK1-0 At reset Access Bit name Description Always read as "0". Select capture trigger edge T9ICEDG1 0: Falling edge 1: Rising edge Timer output enable TM9CL 0: Enabled 1: Disabled (reset)
  • Page 301 Chapter 9 16-bit Timer Timer 9 Mode Registers 2 (TM9MD2: 0x03FC9) Bit name T9ICEDG0 T9PWMSL TM9BCR TM9PWM TM9IRS1 T9ICEN T9ICT1-0 At reset Access Bit name Description Select capture trigger edge T9ICEDG0 0: Both edges 1: Specified edge Select PWM mode T9PWMSL 0: Set duty through TM9OC1 1: Set duty through TM9OC2...
  • Page 302 Chapter 9 16-bit Timer Timer 9 Mode Register 3 (TM9MD3: 0x03FCE) Bit name TM9CKSMP At reset Access Bit name Description Select sampling clock for capture TM9CKSMP 0: Count clock 1: SYSCLK Always read as 0. When capture function is not used, set the TM9MD3.TM9CKSMP to "0". Set the Timer 9 mode registers while the TM9MD1.TM9EN is "0".
  • Page 303: 16-Bit Timer

    Chapter 9 16-bit Timer 9.3 16-bit Timer 9.3.1 Operation 16-bit Timer Operation (Timer 7, Timer 8 and Timer 9) When the value of TMnBC matches the setting value of TMnOC1, an interrupt request (TMnIRQ) is generated at the next count clock. The source of TMnIRQ can be selected by TMnMD2.TMnIRS1. 16-bit timer can generate another independent interrupt request (TMnOC2IRQ) depending on the setting value of TMnOC2.
  • Page 304 Chapter 9 16-bit Timer Count Timing of Timer Operation (Timer 7, Timer 8 and Timer 9) This is the basic operation for all functions of 16-bit timer. Count clock TMnEN Internal enable Preset register Compare register Binary 0000 0001 0002 0000 0001 0002 0003...
  • Page 305 Chapter 9 16-bit Timer When the value of TMnBC matches the setting value of TMnOC, an interrupt request is gen- erated at the next count clock and the TMnBC is cleared. So set the TMnOC as follows: Setting value of the compare register = (Counts till the interrupt request) -1 When TMnOC1 compare match is selected as a TMnBC clear source and TMnOC2IRQ is used, the setting value of TMnOC2 should be smaller than the one of TMnOC1.
  • Page 306: Setup Example

    Chapter 9 16-bit Timer 9.3.2 Setup Example Timer Operation Setup Example Here is an example that the periodic interrupt of Timer 7 is generated every 1000 cycles (250 µs) with selecting HCLK/2 (at f = 8 MHz) as a clock source. The setup procedure and its description are shown below. HCLK Step Setting...
  • Page 307: 16-Bit Event Count

    Chapter 9 16-bit Timer 9.4 16-bit Event Count 9.4.1 Operation For event count operation, TMnIO input can be used as a count clock source and divided by 1 (not divided), 2, 4 or 16. The event count input pin is shown in Table:9.1.1. Count Timing of TMnIO Input The binary counter counts up at the falling edge of TMnIO input signal that is divided or not.
  • Page 308 Chapter 9 16-bit Timer When reading the value of TMnBC, use a 16-bit instruction, MOVW or write data to TMnIC with a software function. When using the MOVW instruction, indeterminate data during counting may be read. So, read the register value several times and confirm those data are identical. When using the capture function, Writing to TMnIC can capture the count value of TMnBC to TMnIC to read the count value during counting precisely.
  • Page 309 Chapter 9 16-bit Timer Count Timing of TMnIO Input (at Both Edges Selected) (Timer 7 and Timer 8) The binary counter counts up at the falling and rising edges of TMnIO input signal that is divided or not. TMnIO input Count clock TMnEN...
  • Page 310: Setup Example

    Chapter 9 16-bit Timer 9.4.2 Setup Example Event Count Setup Example Here is an example that, using timer 7, detecting the falling edge of the TM7IOA input 5 times generates the first interrupt only, and subsequent interrupts are generated every 4 detections. The setup procedure and its description are shown below.
  • Page 311: 16-Bit Timer Pulse Output

    Chapter 9 16-bit Timer 9.5 16-bit Timer Pulse Output 9.5.1 Operation 16-bit Timer Pulse Output Operation In the timer pulse output function, a pulse signal with an arbitrary frequency can be output from TMnIO pin. Timers can output the signal with twice the cycle which is set in TMnOC1 or twice the cycle of the 16-bit full count.
  • Page 312: Setup Example

    Chapter 9 16-bit Timer In the initial state after releasing reset, the timer pulse output is reset and fixed to "Low". Therefore, release the reset of the timer pulse output by setting the TMnMD1.TMnCL to "0". Regardless of whether TMnBC is stopped or in active, the timer output becomes "Low", when the TMnMD1.TMnCL is set to "1".
  • Page 313: 16-Bit Standard Pwm Output (With Continuously Variable Duty

    Chapter 9 16-bit Timer 9.6 16-bit Standard PWM Output (with Continuously Variable Duty) 9.6.1 Operation In the standard PWM output function, a PWM waveform with a given duty cycle can be generated and output from TMnIO pin. 16-bit Standard PWM Output A PWM waveform with a given duty cycle is generated by setting TMnOC1 to "High"...
  • Page 314 Chapter 9 16-bit Timer State at PWM Output Disabled and Polarity (Timer 8) The TM8MD3.TM8PWMF can control the TM8IO output waveform at PWM output disabled. The polarity of PWM output can be selected with the TM8MD3.TM8PWMO. Count Timing of Standard PWM Output (when compare register 1 is set to "0x0000") Count clock TMnEN...
  • Page 315 Chapter 9 16-bit Timer Count Timing of Standard PWM Output (when compare register 1 is set to "0xFFFF") Count clock TMnEN Compare FFFF register 1 Binary 0000 0001 N+1 N+2 FFFE FFFF 0000 0001 counter TMnIO output (PWM output) Figure:9.6.3 Count Timing of Standard PWM Output (when compare register 1 is set to "0xFFFF") When outputting the standard PWM, set the TMnMD2.TMnBCR to "0"...
  • Page 316: Setup Example

    Chapter 9 16-bit Timer 9.6.2 Setup Example Standard PWM Output Setup Example Here is an example that, using Timer 7, the PWM output waveform with the 1/4 duty cycle and 122.1 Hz is output from TM7IO output pin. HCLK (at f = 8 MHz) is selected as a clock source.
  • Page 317: 16-Bit High-Precision Pwm Output (With Continuously Variable Period/Duty

    Chapter 9 16-bit Timer 9.7 16-bit High-Precision PWM Output (with Continuously Variable Period/Duty) 9.7.1 Operation In the high-precision PWM output function, a PWM waveform with a given period and duty cycle can be gener- ated and output from TMnIO pin. 16-bit High-Precision PWM Output Operation PWM waveform with a given period and duty cycle is generated by setting TMnOC1 to the PWM period and set- ting TMnOC2 to "High"...
  • Page 318 Chapter 9 16-bit Timer Count Timing of High-Precision PWM Output (when compare register 2 is set to "0x0000") Count clock TMnEN Compare register 1 Compare 0000 register 2 Binary 0000 0001 0000 0001 counter TMnIO output (PWM output) Figure:9.7.2 Count Timing of High Precision PWM Output (when compare register 2 is set to "0x0000") The PWM output is "High", while the counter is stopped by setting TMnMD1.TMnEN to "0".
  • Page 319 Chapter 9 16-bit Timer Count Timing of High-Precision PWM Output (when compare register 2 is set to "compare register 1" - 1) Count clock TMnEN Compare register 1 Compare register 2 Binary 0000 0001 0000 0001 counter TMnIO output (PWM output) Figure:9.7.3 Count Timing of High-Precision PWM Output (When TMnOC2 is set to TMnOC1 - 1) When outputting the high-precision PWM, set the TMnMD2.TMnBCR to "1"...
  • Page 320: Setup Example

    Chapter 9 16-bit Timer 9.7.2 Setup Example High Precision PWM Output Setup Example Here is an example that, using Timer 7, the PWM output waveform with the 1/4 duty cycle and 400 Hz is output from TM7IO output pin. HCLK/2 (at f = 8 MHz) is selected as a clock source.
  • Page 321: 16-Bit Timer Capture Function

    Chapter 9 16-bit Timer 9.8 16-bit Timer Capture Function 9.8.1 Operation In the capture function, the value of the binary counter is read at the following: - When one of IRQ0 to IRQ3, which is synchronized with the system clock or the count clock, is input. - When an interrupt of Timer 0 or Timer 1 occurs.
  • Page 322 Chapter 9 16-bit Timer When the system clock (SYSCLK) is selected as the capture clock by setting the TMnMD3.TMnCKSMP to "1", the clock for the binary counter is the one that is selected by setting the TMnMD1.TMnCK1-0 and synchronized with SYSCLK. However, if HCLK or SYSCLK is selected with the TMnMD1.TMnCK1-0, the binary counter doesn't count correctly.
  • Page 323 Chapter 9 16-bit Timer Capture Count Timing with a Trigger of Both Edges of External Interrupt Signal Count clock TMnEN Compare register Binary 0000 0001 0111 0112 0113 0114 5555 5556 5557 5558 counter External interrupt m input signal Capture trigger Capture 0000...
  • Page 324 Chapter 9 16-bit Timer It takes 1 or 2 capture clocks to load the value of the binary counter to the capture register since a capture trigger is sampled at the capture clock. In the initial state after releasing the reset, the setting of the external interrupt signal as a trig- ger is disabled.
  • Page 325 Chapter 9 16-bit Timer Capture Operation with a Trigger of Software Writing A capture trigger can be generated by writing an arbitrary value to TMnIC. Synchronizing with this capture trig- ger, the value of the binary counter is loaded to TMnIC. Count clock TMnEN...
  • Page 326 Chapter 9 16-bit Timer Capture Operation with a Trigger of an Interrupt of Timer 0 or 1 (Timer 7 and Timer 8) A capture trigger of the input capture function is generated at an interrupt signal of Timer 0 or 1. Count clock TMnEN...
  • Page 327 Chapter 9 16-bit Timer Binary Counter Clear Function at Capture (Timer 7 and Timer 8) When selecting the external interrupt input signal or Timer 0, 1 interrupt as a capture trigger, the binary counter can be cleared at a capture operation. When clearing the binary counter at a capture operation, set the TMnMD4.TnCAPCLR to "1".
  • Page 328: Setup Example

    Chapter 9 16-bit Timer 9.8.2 Setup Example Capture Function Setup Example Here is an example that, using Timer 7, the value of the binary counter is loaded to the capture register at the interrupt generation edge of IRQ0 signal to measure the pulse width. The rising edge is selected for the interrupt generation edge and capture trigger generation edge.
  • Page 329: 16-Bit Standard Igbt Output (With Variable Duty

    Chapter 9 16-bit Timer 9.9 16-bit Standard IGBT Output (with Variable Duty) Trigger of the standard IGBT output can be selected from IRQ0, 1, 2 and Timer 7 count operation. After starting the count operation, the other operation is the same as that of the 16-bit standard PWM output. Updating the Timer 7 preset register 1 and 2 is prohibited during IGBT operation.
  • Page 330 Chapter 9 16-bit Timer Count timing of Standard IGBT Output (Normal) (Timer 7) Count clock TM7EN Compare register 1 IGBT trigger Binary 0000 0001 N+1 N+2 FFFE FFFF 0000 0001 0000 0002 counter TM7IO output (IGBT output) Figure:9.9.1 Count timing of Standard IGBT Output (Normal) (A) Once the IGBT trigger is input, the IGBT operation is valid at the next clock.
  • Page 331 Chapter 9 16-bit Timer Count timing of Standard IGBT Output (when compare register 1 = "0x0000") (Timer 7) Count clock TM7EN Compare 0000 register IGBT trigger Binary 0000 0001 N+1 N+2 FFFE FFFF 0000 0001 0000 counter TM7IO output (IGBT output) Figure:9.9.2 Count timing of Standard IGBT Output (When compare register 1 = "0x0000") The IGBT output is "Low"...
  • Page 332: Setup Example

    Chapter 9 16-bit Timer 9.9.2 Setup Example Standard IGBT Output Setup Example Here is an example that, using Timer 7 with HCLK (f = 10 MHz) as the clock source, the IGBT output HCLK waveform with the 1/4 duty cycle and 152.59 Hz is output from TM7IOA output pin using IRQ0 input signal as a trigger.
  • Page 333: 16-Bit High-Precision Igbt Output (With Variable Period/Duty

    Chapter 9 16-bit Timer 9.10 16-bit High-Precision IGBT Output (with Variable Period/Duty) The high-precision IGBT signal is output from TM7IO or TM8IO pin while the timer starts counting up using the external interrupt input signal as a trigger. A trigger of the high-precision IGBT output can be selected from IRQ0, 1, 2 or Timer 7 count operation.
  • Page 334 Chapter 9 16-bit Timer 16-bit High-Precision IGBT Output Operation (Timer 7) When setting the TM7MD4.T7NODED to "1", the IGBT waveform with a specified duty can be generated by set- ting the IGBT cycle in TM7OC1 and the "High" period of duty in TM7OC2. The high-precision IGBT output function can be used in Timer 7.
  • Page 335 Chapter 9 16-bit Timer Count timing of High-Precision IGBT Output (Normal) (Timer 7) Count clock TM7EN Compare register 1 Compare register 2 IGBT trigger Binary 0000 0001 0002 0000 0001 0000 counter TM7IO output (IGBT output) TM8IO output (IGBT output) Figure:9.10.1 Count timing of High-Precision IGBT Output (Normal) •...
  • Page 336 Chapter 9 16-bit Timer Count timing of High-Precision IGBT Output (when compare register 2 = "0x0000") (Timer 7) Count clock TM7EN Compare register 1 Compare 0000 register 2 IGBT trigger Binary 0000 0001 0002 N- 1 0000 0001 0000 counter TM7IO output (IGBT output) TM8IO output...
  • Page 337 Chapter 9 16-bit Timer When using the high-precision IGBT output, set the TM7MD2.TM7BCR to "1" to select the TM7OC1 compare match as the binary counter clear source and the IGBT output set source (to "High" state). Also, set the TM7MD2.T7PWMSL to "1" to select TM7OC2 compare match as the IGBT output reset source (to "Low"...
  • Page 338 Chapter 9 16-bit Timer One-shot Pulse Output of High-Precision IGBT (when compare register 2 = "0x0000") (Timer 7) Count Clock TM7EN Flag Compare Register 1 Compare 0000 Register 2 IGBT Trigger Binary 0000 0001 0002 0000 Counter TM7IO output (IGBT output) TM8IO output (IGBT output) Figure:9.10.5 One-shot Pulse Output of High-Precision IGBT...
  • Page 339: Setup Example

    Chapter 9 16-bit Timer 9.10.2 Setup Example High-Precision IGBT Output Setup Example Here is an example that, using Timer 7 with HCLK (f = 10 MHz) as clock source, the IGBT output wave- HCLK form with the 1/4 duty cycle and 400 Hz is output from TM7IOA output pin using the external interrupt 0 input signal as a trigger.
  • Page 340: Igbt Output With Dead Time

    Chapter 9 16-bit Timer 9.11 IGBT Output with Dead Time The IGBT output with dead time which is delay time for ON/OFF is output from TM7IO or TM8IO pin when the referenced IGBT signal is inverted. The output trigger is selected from IRQ0, 1, 2 and Timer 7 count operation. Updating the Timer 7 preset register 1, 2 and Timer 7 dead time preset register 1, 2 is prohib- ited during IGBT operation.
  • Page 341 Chapter 9 16-bit Timer Count Timing of IGBT Output with Dead Time (Timer 7) Figure:9.11.1 Count Timing of IGBT Output with Dead Time IGBT Output with Dead Time IX - 59...
  • Page 342 Chapter 9 16-bit Timer IGBT output waveform with dead time (at the falling edge setting): (A) Until the IGBT output is valid from the IGBT trigger input, the TM7IO and TM8IO are: TM7IO = "Low", TM8IO = "Low". (B) TM7IO rises after the time, that is one count clock + count clock × "the dead time preset register 1 + 1" from the rising edge of the next count clock of the IGBT trigger input, elapses.
  • Page 343 Chapter 9 16-bit Timer One-shot Pulse Output Setting One-shot pulse can be output by setting the TM7MD4.T7ONESHOT to "1". Figure:9.11.2 IGBT One-shot Pulse Output Timing with dead time IGBT Output with Dead Time IX - 61...
  • Page 344: Setup Example

    Chapter 9 16-bit Timer 9.11.2 Setup Example Setup Example of IGBT Output with Dead Time (Timer 7) Here is an example that, using Timer 7 with HCLK (f = 8 MHz) as a clock source, while the external inter- HCLK rupt 0 input signal is generated, the IGBT output waveform having a duty cycle of 1/4 and a frequency of 200 Hz is output from the TM7IO and TM8IO output pins with a dead time of 0.01 ms or 0.02 ms added.
  • Page 345 Chapter 9 16-bit Timer Step Setting Register Description Set the timer mode register TM7MD3.T7IGBTEN = 1 Enable the IGBT output. TM7MD2.TM7PWM = 1 TM8MD3.TM8SEL = 1 TM7MD1.TM7CL = 0 Select the IGBT output pin TMIOEN1.TM7OEN = 1 Select the IGBT output pin. TMIOEN1.TM8OEN = 1 [Chapter 7 I/O Port] P0DIR.P0DIR4 = 1...
  • Page 346 Chapter 9 16-bit Timer IX - 64 IGBT Output with Dead Time...
  • Page 347: Chapter 10 General-Purpose Time Base/Free-Running Timer

    Chapter 10 General-Purpose Time Base/Free-Running Timer...
  • Page 348: Overview

    Chapter 10 General-Purpose Time Base/Free-Running Timer 10.1 Overview This LSI has a time base timer and an 8-bit free-running timer (timer 6). The time base timer is a 15-bit timer counter. 10.1.1 Functions Table:10.1.1 shows the clock source and the interrupt generation cycle that can be used for the timer 6 and the time base timer.
  • Page 349: Block Diagram

    Chapter 10 General-Purpose Time Base/Free-Running Timer 10.1.2 Block Diagram Timer 6, Time Base Timer Block Diagram Figure:10.1.1 Block Diagram (Timer 6, Time Base Timer) Overview X - 3...
  • Page 350: Control Registers

    Chapter 10 General-Purpose Time Base/Free-Running Timer 10.2 Control Registers The timer 6 consists of the binary counter (TM6BC) and compare register (TM6OC), and is controlled by mode register (TM6MD) setting. The time base timer is controlled by using the mode register (TM6MD) and time base timer clear register (TBCLR).
  • Page 351: Programmable Timer Registers

    Chapter 10 General-Purpose Time Base/Free-Running Timer 10.2.2 Programmable Timer Registers The timer 6 is a 8-bit programmable counter. Programmable counter consists of compare register (TM6OC) and binary counter (TM6BC). Binary counter is a 8-bit up-counter. When the TM6CLRS bit of the timer 6 mode register (TM6MD) is "0" and the interrupt cycle data is written to the compare register (TM6OC), the timer 6 binary counter (TM6BC) is cleared to 0x00.
  • Page 352: Timer 6 Enable Register

    Chapter 10 General-Purpose Time Base/Free-Running Timer 10.2.3 Timer 6 Enable Register This register controls the starting operation of the timer 6 and the time base timer. Timer 6 Enable Register (TM6BEN:0x03F7C) Bit name TBEN TM6EN At reset Access Bit name Description 7 to 2 Always read as 0.
  • Page 353: Timer Mode Register

    Chapter 10 General-Purpose Time Base/Free-Running Timer 10.2.4 Timer Mode Register This is a readable/writable register that controls the timer 6 and the time base timer. Timer 6 Mode Register (TM6MD:0x03F7A) Bit name TM6CLRS TM6IR2 TM6IR1 TM6IR0 TM6CK3 TM6CK2 TM6CK1 TM6ICK0 At reset Access Bit name...
  • Page 354: 8-Bit Free-Running Timer

    Chapter 10 General-Purpose Time Base/Free-Running Timer 10.3 8-bit Free-running Timer 10.3.1 Operation 8-bit Free-running Timer (Timer 6) The generation cycle of the timer interrupt should be set in advance by selecting the clock source and setting the compare register (TM6OC). When the binary counter (TM6BC) reaches the setting value of the compare register, an interrupt request is generated at the next count clock and the binary counter is cleared to restart counting up from 0x00.
  • Page 355 Chapter 10 General-Purpose Time Base/Free-Running Timer Count Timing of Timer Operation (Timer 6) Binary counter counts up with the selected clock source as a count clock. Count clock TM6CLRS Compare register Binary counter Interrupt request Figure:10.3.1 Count Timing of Timer Operation (Timer 6) 1.
  • Page 356 Chapter 10 General-Purpose Time Base/Free-Running Timer Stop the timer when switching the count clock. If the count clock is changed during counting, the timer doesn't count correctly. When the timer 6 binary counter (TM6BC) is read on the operation, uncertain value on count- ing up may be read.
  • Page 357: Setup Example

    Chapter 10 General-Purpose Time Base/Free-Running Timer 10.3.2 Setup Example Timer Operation Setup (Timer 6) The timer 6 generates interrupts regularly for the clock function. Interrupts are generated every 250 dividing (62.5 µs) when selecting SYSCLK (at f = 4 MHz) as a clock source. SYSCLK The setup procedure and the description of each step are shown below.
  • Page 358: Time Base Timer

    Chapter 10 General-Purpose Time Base/Free-Running Timer 10.4 Time Base Timer 10.4.1 Operation Time Base Timer (Time Base Timer) The timer generates interrupts regularly by selecting a clock source and a interrupt generation cycle. Table:10.4.1 shows the interrupt generation cycles on each clock source. Table:10.4.1 Selection of Time Base Timer Interrupt Generation Cycle Selected clock source Interrupt generation cycle...
  • Page 359 Chapter 10 General-Purpose Time Base/Free-Running Timer Count Timing of Timer Operation (Time Base Timer) The counter counts up with the selected clock source as a counter clock. 11 10 HCLK SCLK Figure:10.4.1 Count Timing of Timer Operation (Time Base Timer) •...
  • Page 360: Setup Example

    Chapter 10 General-Purpose Time Base/Free-Running Timer 10.4.2 Setup Example Timer Operation Setup (Time Base Timer) The time base timer generates interrupts regularly by selecting a interrupt generation cycle. The interrupt genera- × 1/2 tion cycle is f (1.024 ms: f = 8 MHz).
  • Page 361: Chapter 11 Rtc Time Base Timer (Rtc-Tbt

    XI.. Chapter 11 RTC Time Base Timer (RTC-TBT)
  • Page 362: Overview

    Chapter 11 RTC Time Base Timer (RTC-TBT) 11.1 Overview RTC time base timer (RTC-TBT) generates 1 Hz clock with SCLK of 32.768 kHz for Real Time Clock (RTC). 11.1.1 Functions Table:11.1.1 shows the function of RTC-TBT. Table:11.1.1 RTC-TBT Function Function Description Clock source SCLK (SOSCCLK or SRCCLK is selected.)
  • Page 363: Control Register

    Chapter 11 RTC Time Base Timer (RTC-TBT) 11.2 Control Register Table:11.2.1 shows registers for controlling RTC-TBT. Table:11.2.1 Control Register Symbol Address Register Name Page TBTCNT0 0x03EEA RTC-TBT control register 0 XI-4 TBTCNT1 0x03EEB RTC-TBT control register 1 XI-5 TBTR 0x03EEC RTC-TBT register XI-6 TBTADJL...
  • Page 364: Rtc-Tbt Control Register

    Chapter 11 RTC Time Base Timer (RTC-TBT) 11.2.1 RTC-TBT Control Register RTC-TBT Control Register 0 (TBTCNT0: 0x03EEA) Bit name TBTCLKSEL ADJCNT1-0 TBTIRQEN TBTIRQSEL2-0 At reset Access Bit name Description Clock source select for RTC-TBT TBTCLKSEL 0: SOSCCLK 1: SRCCLK Adjustment period select for RTC-TBT 00: 128 sec ADJCNT1-0 01: 32 sec...
  • Page 365 Chapter 11 RTC Time Base Timer (RTC-TBT) RTC-TBT Control Register 1 (TBTCNT1: 0x03EEB) Bit name TBTCLKOE TBTCLKOS3-0 At reset Access Bit name Description Clock output enable for RTC-TBT TBTCLKOE 0: Disable 1: Enable Always read as 0. Clock output select for RTC-TBT 0000: 256 Hz 0001: 128 Hz 0010: 64 Hz...
  • Page 366: Rtc-Tbt Register

    Chapter 11 RTC Time Base Timer (RTC-TBT) 11.2.2 RTC-TBT Register RTC-TBT Register (TBTR: 0x03EEC) Bit name T1HZ T2HZ T4HZ T8HZ T16HZ T32HZ T64HZ T128HZ At reset Access Bit name Description T1HZ T1HZ output of RTC-TBT T2HZ T2HZ output of RTC-TBT T4HZ T4HZ output of RTC-TBT T8HZ...
  • Page 367: Rtc-Tbt Frequency Adjustment Register

    Chapter 11 RTC Time Base Timer (RTC-TBT) 11.2.3 RTC-TBT Frequency Adjustment Register The frequency of T1HZ to T128HZ can be adjusted with the TBTADJL and the TBTADJH. The following table shows the frequency adjustment rate of T1HZ. Adjustment value = 128 [sec] × Frequency adjustment rate × 2097152 / Adjustment period [sec] (in decimal) = Frequency adjustment rate ×...
  • Page 368 Chapter 11 RTC Time Base Timer (RTC-TBT) Time Base Timer Frequency Adjustment Register for Lower Bits (TBTADJL: 0x03EEE) Bit name TBTADJ7-0 At reset Access Bit name Description TBTADJ7-0 Frequency adjustment setting (lower 8 bits) Time Base Timer Frequency Adjustment Register for Upper Bits (TBTADJH: 0x03EEF) Bit name TBTADJ10-8 At reset...
  • Page 369: Rtc-Tbt Operation

    Chapter 11 RTC Time Base Timer (RTC-TBT) 11.3 RTC-TBT Operation 11.3.1 RTC-TBT Operation RTC-TBT counts up at the rising edge of SCLK after the internal reset. T128HZ, T64HZ, T32HZ, T16HZ, T8HZ, T4HZ and T2HZ bits of the TBTR register are used as RTC-TBT inter- rupt.
  • Page 370: Operation Setting Example

    Chapter 11 RTC Time Base Timer (RTC-TBT) 11.3.2 Operation Setting Example Interrupt of RTC-TBT 128-Hz periodic interrupt by RTC-TBT is generated. The setup procedure and the description of each step are shown below. Step Setting Symbol Description Disable all maskable interrupts PSW * Set the MIE bit to "0".
  • Page 371: Chapter 12 Real Time Clock (Rtc)

    XII.. Chapter 12 Real Time Clock (RTC)
  • Page 372: Overview

    Chapter 12 Real Time Clock (RTC) 12.1 Overview Real Time Clock (RTC) provides the calendar function. Table:12.1.1 shows functions of RTC. Table:12.1.1 RTC Function Function Description Clock source RTC time base timer output (1 Hz) Time display Auto calender (years with the last two digits from 00 until 99) Adjustment for leap year (Years ending in "00"...
  • Page 373: Control Registers

    Chapter 12 Real Time Clock (RTC) 12.2 Control Registers Table:12.2.1 lists the registers that control RTC. Table:12.2.1 List of Control Registers Symbol Address Register Name Page RTCCTR 0x03ED0 RTC control register XII-4 RTCAL0IRQ 0x03ED3 Alarm 0 interrupt control register XII-5 AL0IRQMI 0x03ED4 Alarm 0 minutes setting register...
  • Page 374: Rtc Control Register

    Chapter 12 Real Time Clock (RTC) 12.2.1 RTC Control Register RTC Control Register (RTCCTR: 0x03ED0) Bit name HDMD CLKEN At reset Access Bit name Description 7 to 4 Always read as 0. Display mode select HDMD 0: 24-hour display mode 1: 12-hour display mode RTC operation control CLKEN...
  • Page 375: Alarm 0 Interrupt Registers

    Chapter 12 Real Time Clock (RTC) 12.2.2 Alarm 0 Interrupt Registers Alarm 0 Interrupt Control Register (RTCAL0IRQ: 0x03ED3) AL0IRQ AL0IRQ AL0IRQ AL0IRQ Bit name MIEN At reset Access Bit name Description Always read as 0. Alarm 0 interrupt control AL0IRQSET 0: Disabled 1: Enabled 5 to 3...
  • Page 376 Chapter 12 Real Time Clock (RTC) Alarm 0 Hours Setting Register (AL0IRQH: 0x03ED5) Bit name AL0IRQH6 AL0IRQH5-0 At reset Access Bit name Description Always read as 0. Alarm 0 "AM/PM" setting 0: AM AL0IRQH6 1: PM * This bit must be set in 12-hour clock mode. In 24-hour clock mode, this bit must be set to "0".
  • Page 377: Alarm 1 Interrupt Registers

    Chapter 12 Real Time Clock (RTC) 12.2.3 Alarm 1 Interrupt Registers Alarm 1 Interrupt Control Register (RTCAL1IRQ: 0x03ED7) AL1IRQ AL1IRQ AL1IRQ AL1IRQ AL1IRQ Bit name MOEN MIEN At reset Access Bit name Description Always read as "0". Alarm 1 interrupt control AL1IRQSET 0: Disabled 1: Enabled...
  • Page 378 Chapter 12 Real Time Clock (RTC) Alarm 1 Hours Setting Register (AL1IRQH: 0x03ED9) Bit name AL1IRQH6 AL1IRQH5-0 At reset Access Bit name Description Always read as 0. Alarm 1 "AM/PM" setting 0: AM AL1IRQH6 1: PM * This bit must be set in 12-hour clock mode. When 24-hour clock mode, this bit must be set to "0".
  • Page 379 Chapter 12 Real Time Clock (RTC) Alarm 1 Month Setting Register (AL1IRQMO: 0x03EDB) Bit name AL1IRQMO4-0 At reset Access Bit name Description 7 to 5 Always read as 0. Alarm 1 "Month" setting 4 to 0 AL1IRQMO4-0 Set a value within the range of "01" to "12" using the BCD format. * The value which doesn’t exist must not be set.
  • Page 380: Periodic Interrupt Control Register

    Chapter 12 Real Time Clock (RTC) 12.2.4 Periodic Interrupt Control Register Periodic Interrupt Control Register (RTCCIRQ: 0x03ED2) Bit name CIRQHEN CIRQMIEN CIRQSEN CIRQS05EN At reset Access Bit name Description 7 to 5 Always read as 0. Periodic interrupt control (The periodic interrupt is generated every hour) CIRQHEN 0: Disable 1: Enable...
  • Page 381: Clock Registers

    Chapter 12 Real Time Clock (RTC) 12.2.5 Clock Registers Seconds Setting Register (RTCSD: 0x03EE0) Bit name SD6-0 At reset Access Bit name Description Always read as "0". "Second" setting Set a value within the range of "00" to "59" using the BCD format. 6 to 0 SD6 to 0 * The value which doesn’t exist must not be set.
  • Page 382 Chapter 12 Real Time Clock (RTC) Hours Setting Register (RTCHD: 0x03EE2) Bit name HD5-0 At reset Access Bit name Description Always read as 0. "AM/PM" setting 0: AM 1: PM * In 24-hour clock mode, bit setting of the HD6 is ignored. "Hour"...
  • Page 383 Chapter 12 Real Time Clock (RTC) Day Setting Register (RTCDD: 0x03EE4) Bit name DD5-0 At reset Access Bit name Description 7 to 6 Always read as 0. "Day" setting Set a value within the range of "01" to "31" using the BCD format. 5 to 0 DD5 to 0 * The value is incremented by one from "01"...
  • Page 384: Rtc Status Register

    Chapter 12 Real Time Clock (RTC) 12.2.6 RTC Status Register RTC Status Register (RTCSTR: 0x03ED1) Bit name LEAPFL At reset Access Bit name Description 7 to 1 Always read as 0. Leap year flag LEAPFL 0: The RTCYD does not show a leap year. 1: The RTCYD shows a leap year.
  • Page 385: Rtc Operation

    Chapter 12 Real Time Clock (RTC) 12.3 RTC Operation When the RTCCTR.CLKEN is set to "1", RTC starts time counting by using the clock registers described in [12.2.5 Clock Registers]. RTC has two types of interrupts, the periodic interrupt and the alarm interrupt. The periodic interrupt occurs according to the condition set in the RTCCIRQ.
  • Page 386: Clock Data Reading Procedure

    Chapter 12 Real Time Clock (RTC) 12.3.1 Clock Data Reading Procedure After RTC is activated, the calendar information can be obtained by reading CALENDAR registers described in Chapter 12.2.5. To avoid misreading the calendar information because of the occurrence of the calendar update while reading it, the following procedure (1) or (2) must be performed.
  • Page 387: Setup Example

    Chapter 12 Real Time Clock (RTC) 12.3.2 Setup Example Periodic Interrupt Setup Example The following is an example to generate a periodic interrupt with a cycle of a minute with the RTC function. Set the initial time to "01:01:00 (Thursday), April 01, 2010" in 24-hour display mode. The setup procedure and the description of each step are shown below.
  • Page 388 Chapter 12 Real Time Clock (RTC) Alarm Interrupt Setup Example The following is an example to generate the Alarm 0 interrupt at 10:23 on Saturday with the RTC function. Set the initial time to "01:01:00 (Thursday)" in 24-hour display mode. The setup procedure and the description of each step are shown below.
  • Page 389: Chapter 13 Serial Interface

    XIII.. Chapter 13 Serial Interface...
  • Page 390: Overview

    Chapter 13 Serial Interface 13.1 Overview The LSI has 4 serial interfaces (SCIF0/SCIF1/SCIF2/SCIF3), which support the following types of communica- tion. Table:13.1.1 Serial Interface Communication Types SCIF0, SCIF1 SCIF2, SCIF3 √ √ Clock-Synchronous √ UART(Full duplex) √ Multi master IIC Table:13.1.2 shows pins used for each SCIF.
  • Page 391: Functions

    Chapter 13 Serial Interface 13.1.1 Functions Table:13.1.3, Table:13.1.4, and Table:13.1.5 show the serial interface functions. Table:13.1.3 Functions of Clock-Synchronous Communication SCIF0/SCIF1/SCIF2/SCIF3 Transfer clock SCIF0/SCIF1: Generated by dividing BRTMn output clock by 1, 8 or 16 SCIF2/SCIF3: Generated by dividing BRTMn output clock by 1 Duty of BRTM output clock BRTM count clock HCLK/2...
  • Page 392 Chapter 13 Serial Interface Table:13.1.5 Functions of IIC Communication SCIF2/SCIF3 Transfer clock Generated by dividing BRTMn output clock by 8 Duty of BRTM output clock 1:1 or 1:N BRTM count clock HCLK/2 (a = 0, 1, 2, 3, 4, 5, 6, 7, 8) SCLK/2 (b = 0, 1, 2, 3, 4, 5, 6, 7, 8) SYSCLK/2...
  • Page 393: Block Diagram

    Chapter 13 Serial Interface 13.1.2 Block Diagram Figure:13.1.1 SCIFn (n = 0, 1) Block Diagram Overview XIII - 5...
  • Page 394 Chapter 13 Serial Interface Figure:13.1.2 SCIFn (n = 2, 3) Block Diagram XIII - 6 Overview...
  • Page 395: Control Registers

    Chapter 13 Serial Interface 13.2 Control Registers Registers of SCIFn and baud rate timer (hereafter indicated as BRTMn) that generates a transfer clock are shown in Table:13.2.1. 13.2.1 Registers Table:13.2.1 Serial Interface Control Registers Register Address Access Register name Page symbol SC0MD0 0x03E30...
  • Page 396 Chapter 13 Serial Interface Register Address Access Register name Page symbol SC3MD0 0x03E60 SCIF3 Mode Register 0 XIII-12 SC3MD1 0x03E61 SCIF3 Mode Register 1 XIII-14 SC3MD2 0x03E62 SCIF3 Mode Register 2 XIII-16 SC3MD3 0x03E63 SCIF3 Mode Register 3 XIII-18 SC3AD 0x03E64 SCIF3 Address Setting Register XIII-22...
  • Page 397: Input/Output Pin Control Register

    Chapter 13 Serial Interface 13.2.2 Input/Output Pin Control Register SCIF01 I/O Pin Switching Control Register (SC01SEL) Bit name SC1SEL3 SC1SEL2 SC1SEL1 SC1SEL0 SC0SEL3 SC0SEL2 SC0SEL1 SC0SEL0 Initial value Access Bit name Description SCIF1 pin group selection 0000: SBCS1A/SBT1A/SBO1A(TXD1A)/SBI1A(RXD1A) SC1SEL3-0 1111: SBCS1B/SBT1B/SBO1B(TXD1B)/SBI1B(RXD1B) *Setting other value is prohibited.
  • Page 398: Receive Data Buffer

    Chapter 13 Serial Interface 13.2.3 Receive Data Buffer SCIFn (n = 0, 1, 2, 3) Reception Data Buffer (RXBUF0, RXBUF1, RXBUF2, RXBUF3) Bit name RXBUFn7 RXBUFn6 RXBUFn5 RXBUFn4 RXBUFn3 RXBUFn2 RXBUFn1 RXBUFn0 Initial value Access Bit name Description RXBUFn7-0 Received data is stored. 13.2.4 Transmit Data Buffer SCIFn (n = 0, 1, 2, 3) Transmission Data Buffer (TXBUF0, TXBUF1, TXBUF2, TXBUF3)
  • Page 399: Mode Register

    Chapter 13 Serial Interface 13.2.5 Mode Register SCIFn (n = 0, 1) Mode Register 0 (SC0MD0, SC1MD0) Bit name SCnCE1 Reserved SCnCTM SCnDIR Reserved Reserved Reserved Reserved Initial value Access Bit name Description Clock polarity selection SCnCE1 0: Initial value "High" 1: Initial value "Low"...
  • Page 400 Chapter 13 Serial Interface SCIFn (n = 2, 3) Mode Register 0 (SC2MD0, SC3MD0) Bit name SCnCE1 SCnCTM IIC3DEM IIC3DIR IIC3STE Reserved Reserved Reserved Initial value Access Bit name Description Clock polarity selection SCnCE1 0: Initial value "High" 1: Initial value "Low" Communication mode selection SCnCTM 0: Single byte communication...
  • Page 401 Chapter 13 Serial Interface SCIFn (n = 0, 1) Mode Register 1 (SC0MD1, SC1MD1) Bit name SCnIOM SCnSBTS SCnSBIS SCnSBOS SCnCKM SCnMST SCnDIV SCnCMD Initial value Access Bit name Description Data input pin selection SCnIOM 0: SBIn 1: SBOn SBTn function control SCnSBTS 0: Disable 1: Enable (Input or Output transfer clock)
  • Page 402 Chapter 13 Serial Interface SCIFn (n = 2, 3) Mode Register 1 (SC2MD1, SC3MD1) Bit name SCnIOM SCnSBTS SCnSBIS SCnSBOS SCnIFS SCnMST Initial value Access Bit name Description Data input pin selection SCnIOM 0: SBIn 1: SBOn SBTn function control SCnSBTS 0: Disable 1: Enable (Input or Output transfer clock)
  • Page 403 Chapter 13 Serial Interface SCIFn (n = 0, 1) Mode Register 2 (SC0MD2, SC1MD2) Bit name SCnFM1 SCnFM0 SCnPM1 SCnPM0 SCnNPE SCnIFS SCnBRKF SCnBRKE Initial value Access Bit name Description UART Frame mode specification 00: Data 7 bit + stop 1 bit SCnFM1-0 01: Data 7 bit + stop 2 bit 10: Data 8 bit + stop 1 bit...
  • Page 404 Chapter 13 Serial Interface SCIFn (n = 2, 3) Mode Register 2 (SC2MD2, SC3MD2) Bit name SCnFDC1 SCnFDC0 SCnRSTN SCnCKPH SCnSBCSEN SCnSBCSLV Initial value Access Bit name Description Output level selection after the final bit of SBOn is transmitted 00: Fixed at "1" (High) output SCnFDC1-0 01: Hold the final data 10: Fixed at "0"...
  • Page 405 Chapter 13 Serial Interface SCIFn (n = 0, 1) Mode Register 3 (SC0MD3, SC1MD3) SCnSBCS SCnSBCS Bit name SCnFDC1 SCnFDC0 SCnRSTN SCnRSRN SCnCKPH Initial value Access Bit name Description Output level selection after the final bit of SBOn is transmitted 00: Fixed at "1"...
  • Page 406 Chapter 13 Serial Interface SCIFn (n = 2, 3) Mode Register 3 (SC2MD3, SC3MD3) Bit name Reserved Reserved IIC3STPC IIC3TMD IIC3REX SCnCMD IIC3ACKS IIC3ACKO Initial value Access Bit name Description Reserved Always set to "0" IIC stop condition generation IIC3STPC 0: None 1: Generate stop condition IIC communication mode...
  • Page 407: Status Register

    Chapter 13 Serial Interface 13.2.6 Status Register SCIFn (n = 0, 1) Status Register (SC0STR, SC1STR) Bit name SCnTBSY SCnRBSY SCnTEMP SCnREMP SCnFEF SCnPEK SCnORE SCnERE Initial value Access Bit name Description Data transmission state SCnTBSY 0: IDLE 1: During transmission Data reception state SCnRBSY 0: IDLE...
  • Page 408 Chapter 13 Serial Interface SCIFn (n = 2, 3) Status Register (SC2STR, SC3STR) Bit name SCnTBSY SCnTEMP SCnREMP SCnORE Initial value Access Bit name Description Data transmission state in Clock-Synchronous communication SCnTBSY 0: IDLE 1: During transmission "0" is always read out. Transmission data buffer empty detection SCnTEMP 0: detected...
  • Page 409 Chapter 13 Serial Interface SCIFn (n = 2, 3) Status Register for IIC (SC2IICSTR, SC3IICSTR) IIC3ABT IIC3ADD IIC3BUS IIC3GC IIC3DATA Bit name IIC3WRS IIC3STRT Reserved _LST _ACC _ERR Initial value Access Bit name Description Transmission/reception mode in slave communication IIC3WRS 0: Reception mode 1: Transmission mode Arbitration lost detection...
  • Page 410: Address Setting Register

    Chapter 13 Serial Interface 13.2.7 Address Setting Register SCIFn (n = 2, 3) Address Setting Register (SC2AD, SC3AD) Bit name IIC3AD7 IIC3AD6 IIC3AD5 IIC3AD4 IIC3AD3 IIC3AD2 IIC3AD1 IIC3AD0 Initial value Access 13.2.8 BRTM Operation Mode Setting Register BRTM Operation Mode Setting Register (BRTM_S_MD) Bit name BRTM_S3_MD BRTM_S2_MD BRTM_S1_MD BRTM_S0_MD Initial value...
  • Page 411: Brtm Operation Enable Register

    Chapter 13 Serial Interface 13.2.9 BRTM Operation Enable Register BRTM Operation Enable Register (BRTM_S_EN) BRTM_S3 BRTM_S2 BRTM_S1 BRTM_S0 Bit name Initial value Access Bit name Description "0" is always read out. BRTM3 count operation BRTM_S3_EN 0: Disabled 1: Enabled BRTM2 count operation BRTM_S2_EN 0: Disabled 1: Enabled...
  • Page 412: Brtm Clock Select Register

    Chapter 13 Serial Interface 13.2.10 BRTM Clock Select Register BRTM Base Clock Select Register (BRTM_S_CKSEL) BRTM_ BRTM_ BRTM_ BRTM_ Bit name S3_CKSEL S2_CKSEL S1_CKSEL S0_CKSEL Initial value Access Bit name Description "0" is always read out BRTM3 base clock BRTM_S3_CKSEL 0: HCLK 1: SCLK BRTM2 base clock...
  • Page 413 Chapter 13 Serial Interface BRTM01 Count Clock Select Register (BRTM_S01_CK) BRTM_S1 BRTM_S1 BRTM_S1 BRTM_S1 BRTM_S0 BRTM_S0 BRTM_S0 BRTM_S0 Bit name _CK3 _CK2 _CK1 _CK0 _CK3 _CK2 _CK1 _CK0 Initial value Access Bit name Description BRTM1 count clock selection 0000: BRT1SCLK 0001: BRT1SCLK/2 0010: BRT1SCLK/4 0011: BRT1SCLK/8...
  • Page 414 Chapter 13 Serial Interface BRTM23 Count Clock Select Register (BRTM_S23_CK) BRTM_S3 BRTM_S3 BRTM_S3 BRTM_S3 BRTM_S2 BRTM_S2 BRTM_S2 BRTM_S2 Bit name _CK3 _CK2 _CK1 _CK0 _CK3 _CK2 _CK1 _CK0 Initial value Access Bit name Description BRTM3 count clock selection 0000: BRT3SCLK 0001: BRT3SCLK/2 0010: BRT3SCLK/4 0011: BRT3SCLK/8...
  • Page 415: Brtm Compare Register

    Chapter 13 Serial Interface 13.2.11 BRTM Compare Register BRTMn (n = 0, 1, 2, 3) Compare Register (BRTM_S0_OC, BRTM_S1_OC, BRTM_S2_OC, BRTM_S3_OC) BRTM_Sn BRTM_Sn BRTM_Sn BRTM_Sn BRTM_Sn BRTM_Sn BRTM_Sn BRTM_Sn Bit name _OC7 _OC6 _OC5 _OC4 _OC3 _OC2 _OC1 _OC0 Initial value Access Bit name Description...
  • Page 416: Clock-Synchronous Communication

    Chapter 13 Serial Interface 13.3 Clock-Synchronous Communication This section describes the Clock-Synchronous communication. The index "n" of serial interface (SCIF) denotes "n = 0, 1, 2, 3", unless otherwise noted. When communicating with Clock-Synchronous by using SCIFn (n = 0, 1), set SCnMD1.SCnCMD to "0". When communicating with Clock-Synchronous by using SCIFn (n = 2, 3), set SCnMD3.SCnCMD to "0".
  • Page 417: Operation

    Chapter 13 Serial Interface 13.3.2 Operation Initialization (Serial Reset) SCIFn has a built-in serial reset function for abnormal operation. Registers other than TXBUFn must be changed during the serial reset of SCIFn. The way of serial reset is as follows. SCIFn (n = 0, 1): SCnMD2.SCnBRKF and SCnSTR are initialized by setting SCnMD3.SCnRSTN to "0".
  • Page 418 Chapter 13 Serial Interface Setting of Transfer Clock (SCnCLK) SCIFn (n = 0, 1) operates with SCnCLK which is generated based on BRTM output clock (BRTM_SCnCLK). When SCnMD1.SCnCKM is "0", SCnCLK is the same as BRTM_SCnCLK. When SCnMD1.SCnCKM is "1", SCnCLK is as follows: When SCnMD1.SCnDIV is "0", SCnCLK is BRTM_SCnCLK divided by 8.
  • Page 419 Chapter 13 Serial Interface While the duty is "1:N" (BRTM_S_MD.BRTM_Sn_MD = 1), the cycle and operation of BRTMn are shown in the figure below. BRTM_SnCLK Cycle = (N + 1) × Count Clock Cycle (N: Setting value of BRTM_Sn_OC, The setting of N = 0x00 is disabled.) HCLK SYSCLK BRTM_Sn_EN...
  • Page 420 Chapter 13 Serial Interface Setting of Clock Pin (SBTn) Figure:13.3.1 shows the relation among SBTn level at bus-idle (serial communication is not executed), active edge of SBTn at data transmission/reception and SCnMD0.SCnCE1, SCnMD3.SCnCKPH (n = 0, 1), and SCnMD2.SCnCKPH (n = 2, 3). "Leading edge"...
  • Page 421 Chapter 13 Serial Interface SBT pin Data is received in synchronization with the falling edge of the clock. SBI pin Data is sent in synchronization with the rising edge of the clock. SBO pin Figure:13.3.7 3-wire Communication Transmission/ Reception Timing (When SCnCKPH = 0 and SCnCE1 = 1) Figure:13.3.8 shows the 4-wire communication waveform when SCnCKPH = 1.
  • Page 422 Chapter 13 Serial Interface SBTn (SCnCE1 = 0) 0.5T(minimum value) SBTn (SCnCE1 = 1) SBIn reception timing SBOn (At master) SBOn (At slave) Last bit data hold period SBCSn (= 0.5´T + (1.5´(SCnCLK frequency )) (At master(output)) SBCSn (At slave(input)) Figure:13.3.9 4-wire Communication Transmission/ Reception Timing (SCnCKPH = 0) XIII - 34 Clock-Synchronous Communication...
  • Page 423 Chapter 13 Serial Interface Transmission Data Buffer (TXBUFn) and Transmission Buffer Empty Flag (SCnTEMP) TXBUFn is the buffer to store the data to be transmitted. SCnSTR.SCnTEMP is set to "1" when data is written to TXBUFn, and is cleared to "0" when data in TXBUFn is transferred to the transmit shift register (SCnTRB) and the serial communication starts.
  • Page 424 Chapter 13 Serial Interface Interrupt Source Select For SCIFn (n = 0, 1), interrupt source can be selected with SCnMD2.SCnIFS. When SCnIFS is "1", an interrupt occurs by an empty detection of TXBUFn (detecting that SCnSTR.SCnTEMP is "0"). When SCnIFS is "0", an interrupt (communication complete interrupt) occurs after single byte communication has finishes.
  • Page 425 Chapter 13 Serial Interface Consecutive Communication Mode When SCnMD0.SCnCTM is "1", consecutive communication mode is selected. In this mode, when the next data is written to TXBUFn by the specified timing, the following communication is executed without a communication blank. To execute a communication without a blank, write the next data to TXBUFn before the 7th bit of data (1 byte) is received after the data in TXBUFn was read out to the transmission shift register (SCnTRB) and SCnTEMP changed to "0".
  • Page 426 Chapter 13 Serial Interface Communication in CPU STANBY Mode In CPU STANBY mode, a communication complete interrupt of slave reception can make CPU operation mode return from CPU STANBY mode to NORMAL mode. Read reception data in RXBUFn after the return to NOR- MAL mode.
  • Page 427: Operation Timing

    Chapter 13 Serial Interface 13.3.3 Operation Timing Transmission Timing Writing period to TXBUFn Twait (when consecutive communication mode) (=3.5T) SBTn SBOn SCnTBSY (Set data to TXBUFn Communication completion interrupt Figure:13.3.11 Transmission Timing (At Falling Edge, SCnCKPH bit = 0) Writing period to TXBUFn Twait (when consecutive communication mode) (=3.5T)
  • Page 428 Chapter 13 Serial Interface Reception Timing Writing period to TXBUFn Twait (when consecutive communication mode) (=3.5T) SBTn SBOn/SBIn SCnRBSY (Set data to TXBUFn Communication completion interrupt Figure:13.3.13 Reception Timing (At Rising Edge, SCnCKPH bit = 0) Writing period to TXBUFn Twait (when consecutive communication mode) (=3.5T)
  • Page 429: Setting Procedure

    Chapter 13 Serial Interface 13.3.4 Setting Procedure Refer to the following pages for the setting procedure in clock synchronous mode. Setting Page Initial setting before communication XIII-42 Data transmission/reception (1-byte communication mode) XIII-43 Data transmission (1-byte communication mode) XIII-43 Data reception (1-byte communication mode) XIII-44 Data transmission/reception (consecutive communication mode) XIII-44...
  • Page 430 Chapter 13 Serial Interface Initial Setting Before Communication Step Setting Register name Description Disable interrupt SCnTICR.SCnTIE = 0 Disable the interrupt for SCIFn to be used. Reset <SCIFn (n = 0, 1 )> Reset SCIFn to be used. SCnMD3.SCnRSTN = 0 <SCIFn (n = 2, 3)>...
  • Page 431 Chapter 13 Serial Interface Data Transmission/Reception (1-byte Communication Mode) Step Setting Register name Description Empty confirmation of transmis- SCnSTR.SCnTEMP Confirm that SCnSTR1.SCnTEMP is 0. sion buffer Data write to TXBUFn TXBUFn Set transmission data in TXBUFn. Wait for communication comple- <SCIFn (n = 0, 1)>...
  • Page 432 Chapter 13 Serial Interface Data Reception (1-byte Communication Mode) Step Setting Register name Description Empty confirmation of transmis- SCnSTR.SCnTEMP Confirm that SCnSTR1.SCnTEMP is 0. sion buffer Dummy data write to TXBUFnTX- TXBUFn Set dummy data in TXBUFn. BUFn Wait for communication comple- <SCIFn (n = 0, 1)>...
  • Page 433 Chapter 13 Serial Interface Data Transmission (Consecutive Communication Mode) Step Setting Register name Description Empty confirmation of transmis- SCnSTR.SCnTEMP Confirm that SCnSTR1.SCnTEMP is 0. sion buffer Data write to TXBUFn TXBUFn Set transmission data in TXBUFn. (The first data transmission) Empty confirmation of transmis- SCnSTR.SCnTEMP Confirm that SCnSTR.SCnTEMP becomes 0 since communi-...
  • Page 434: Full-Duplex Uart Communication

    Chapter 13 Serial Interface 13.4 Full-duplex UART Communication This chapter describes a full-duplex UART communication. The index "n" of serial interface denotes "n = 0, 1", unless otherwise noted. When communicating with UART by using SCIFn, set SCnMD1.SCnCMD to "1". 13.4.1 Communication Form 1-wire UART...
  • Page 435 Chapter 13 Serial Interface Setup of Data Frame and Parity Bit Figure:13.4.1 shows data format of UART communication. Frame Start Parity Stop Character bit Figure:13.4.1 Data Format in UART Communication Data frame consists of following types of bit that are shown in Table:13.4.1. Set character and stop bits with SCnMD2.SCnFM1-0.
  • Page 436: Operation

    Chapter 13 Serial Interface 13.4.2 Operation Circuit Initialization (Serial Reset) SCIFn has a built-in serial reset function for abnormal operation. Registers other than TXBUFn and SCnMD2.SCnBRKE must be changed during serial reset. SCnSTR and SCnMD2.SCnBRKF are initialized by setting both SCnMD3.SCnRSTN and SCnMD3.SCnRSRN to "0".
  • Page 437 Chapter 13 Serial Interface Setting of Transfer Clock (SCnCLK) SCIFn operates with SCnCLK which is generated based on BRTM output clock (BRTM_SCnCLK). Regardless of the setting value of SCnMD1.SCnCKM, SCnCLK is as follows: When SCnMD1.SCnDIV is "0", SCnCLK is generated by dividing BRTM_SCnCLK by 8. When SCnMD1.SCnDIV is "1", SCnCLK is generated by dividing BRTM_SCnCLK by 16.
  • Page 438 Chapter 13 Serial Interface Transmission BUSY Flag When SCnMD1.SCnSBOS is "1", SCnSTR.SCnTBSY is set to "1" by writing data to TXBUFn. When SCnSTR.SCnTEMP is "0" (no data existed in TXBUFn), SCnSTR.SCnTBSY is cleared to "0" when SCn- TICR occurs. While SCnSTR.SCnTEMP is "1" (data existed in TXBUFn), SCnSTR.SCnTBSY is held at "1" when SCnTICR occurs.
  • Page 439 Chapter 13 Serial Interface Data Storage to TXBUFn In MSB first mode, write transmission data to TXBUFn in order from the upper bit. For example, when transmitting 7-bit data, write data to TXBUFn from bp7 to bp1 as shown in Figure:13.4.2. Each bit from A to G is transmitted in the order from G to A.
  • Page 440: Timing

    Chapter 13 Serial Interface 13.4.3 Timing Transmission Twait (=2.5T) Parity Stop Stop SCnTBSY (Set data toTXBUFn) Transmission completion interrupt Figure:13.4.6 Transmission Timing (with Parity Bit) Twait (=2.5T) Stop Stop TXD pin SCnTBSY (Set data to TXBUFn) Transmission completion interrupt Figure:13.4.7 Transmission Timing (without Parity Bit) XIII - 52 Full-duplex UART Communication...
  • Page 441 Chapter 13 Serial Interface Reception Twait (=0.5T) Parity Stop Stop RXDn SCnRBSY Start condition input Reception completion interrupt Figure:13.4.8 Reception Timing (with Parity Bit) Twait (=0.5T) Stop Stop RXDn SCnRBSY Start condition input Reception completion interrupt Figure:13.4.9 Reception Timing (without Parity Bit) Full-duplex UART Communication XIII - 53...
  • Page 442: Setting Procedure

    Chapter 13 Serial Interface 13.4.4 Setting procedure The setting procedure of full-duplex UART is shown as follows. Setting Page Initial Setting Before Communication XIII-54 Data Transmission XIII-55 Data Reception XIII-55 UART Break Transmission XIII-55 Initial Setting Before Communication Step Setting Register name Description Disable interrupt...
  • Page 443 Chapter 13 Serial Interface Data Transmission Step Setting Register name Description Empty confirmation of transmis- SCnSTR.SCnTEMP Confirm that SCnSTR1.SCnTEMP is 0. sion buffer Data write to TXBUFn TXBUFn Set transmission data in TXBUFn. Transmission end Repeat these procedures from step 1 to execute the next communication.
  • Page 444: Iic Communication

    Chapter 13 Serial Interface 13.5 IIC Communication This section describes IIC communication. The index "n" of interface denotes "n = 2, 3", unless otherwise noted. When executing IIC communication with SCIFn, set SCnMD3.SCnCMD to "1". 13.5.1 Format Transfer Format SCIFn supports "7-bit addressing format" in which 7-bit slave addresses are sent following a start condition XXXXXXX Master Data from other IIC...
  • Page 445: Operation

    Chapter 13 Serial Interface 13.5.2 Operation Serial Reset SCIFn has a built-in serial reset function for abnormal operation. SCnMD0-3 other than SCnMD0.IIC3STE, SCnMD3.IIC3STPC, SCnMD3.IIC3REX, and SCnMD3.IIC3ACKO must be changed during the serial reset of SCIFn. SCnSTR.SCnTEMP/SCnREMP/SCnORE, bp6-0 of SCnIICSTR, and SC3MD3.IIC3STPC are initialized by the serial reset when setting SC3MD2.SCnRSTN to "0".
  • Page 446 Chapter 13 Serial Interface Detection of Start/Restart Condition and Stop Condition When a start/restart condition is detected, SC3IICSTR.IIC3STRT is set to "1". When the received slave address is equal to SCnAD, SC3IICSTR.IIC3STRT is cleared to "0" by setting data to TXBUFn during the interrupt processing right after the slave address reception.
  • Page 447 Chapter 13 Serial Interface Detection of Communication Forcibly Terminated When a start/stop condition is detected during the transmission/reception of data, including a slave address and R/ W bit, and ACK bit, SCnIICSTR.IIC3DATA_ERR is set to "1" as judged the serial communication is forced to be terminated.
  • Page 448 Chapter 13 Serial Interface Clock Extension in Master Communication SCLn is sampled at falling edges of SCnCLK in Standard Mode, or rising edges of SCnCLK in High-speed Mode. When the transfer clock output from the LSI is "High" but SCLn is "Low", the high period of the transfer clock is extended since the slave device keeps SCLn "Low".
  • Page 449 Chapter 13 Serial Interface SCnCLK SDAn Transfer clock output from the LSI SCLn 2 ×(SCnCLK) Transfer rate = SCnCLK divided by 8 Figure:13.5.5 SCLn without "Low" Period Extension by Slave Device (High-speed Mode) SCnCLK SDAn "High" period extension Transfer clock output from the LSI 2 ×(SCnCLK) SCLn...
  • Page 450: Timing

    Chapter 13 Serial Interface 13.5.3 Timing Master Transmission Timing address data 8 bits transmission transmission SDAn SCLn SCnTIRQ IIC3BUSBSY Set data to TXBUFn Set data to TXBUFn Set IIC3STPC Figure:13.5.7 Master Transmission Timing (1) Generate start condition by setting data to TXBUFn (2) Transmit Address data (slave address + R/W bit) (3) Receive ACK bit (4) Set data to TXBUFn in interrupt handler...
  • Page 451 Chapter 13 Serial Interface Master Reception Timing address data 8 bits reception transmission SDAn NACK SCLn SCnTIRQ IIC3BUSBSY Set data to TXBUFn Set dummy data to TXBUFn Set IIC3STPC Figure:13.5.8 Master Reception Timing (1) Generate start condition by setting data to TXBUFn (2) Transmit Address data (slave address + R/W bit) (3) Receive ACK bit (4) Set SCnMD3.IIC3REX to "1"...
  • Page 452 Chapter 13 Serial Interface Slave Transmission Timing address data 8-bit transmission reception SDAn SCLn SCnTIRQ IIC3STRT IIC3ADD_ACC IIC3BUSBSY Set data to TXBUFn Set data to TXBUFn Figure:13.5.9 Slave Transmission Timing (1) Detect start condition (2) Receive address data (slave address + R/W bit) (3) Transmit ACK bit (4) Set data to TXBUFn in interrupt handler (5) Transmit data...
  • Page 453 Chapter 13 Serial Interface Slave Transmission Timing (NACK Reception) address data 8 bits transmission reception SDAn NACK SCLn SCnTIRQ IIC3STRT IIC3ADD_ACC IIC3BUSBSY Set data to TXBUFn Figure:13.5.10 Slave Transmission Timing (NACK Reception) (1) Detect start condition (2) Receive address data (slave address + R/W bit) (3) Transmit ACK bit (4) Set data to TXBUFn in interrupt handler (5) Transmit data...
  • Page 454 Chapter 13 Serial Interface Slave Reception Timing (Stop Condition Detection) address data 8-bit reception reception SDAn SCLn SCnTIRQ IIC3STRT IIC3ADD_ACC IIC3BUSBSY Set dummy data to TXBUFn Set dummy data to TXBUFn Figure:13.5.11 Slave Reception Timing (Stop Condition Detection) (1) Detect start condition (2) Receive address data (slave address + R/W bit) (3) Transmit ACK bit (4) Set dummy data to TXBUFn in interrupt handler...
  • Page 455 Chapter 13 Serial Interface Slave Reception Timing (Restart Condition Detection) address data 8 bits reception reception SDAn SCLn SCnTIRQ IIC3STRT IIC3ADD_ACC IIC3BUSBSY Set dummy data to TXBUFn Set dummy data to TXBUFn Figure:13.5.12 Slave Reception Timing (Restart Condition Detection) (1) Detect start condition (2) Receive address data (slave address + R/W bit) (3) Transmit ACK bit (4) Set dummy data to TXBUFn in interrupt handler...
  • Page 456: Setup Example

    Chapter 13 Serial Interface 13.5.4 Setup Example Setting Example of Master Communication (*1) As initial setting, register changed at the time of serial reset is shown below. Please change it if needed, such as interrupt setting or port setting. Master setting at slave address transmission SCnMD0 SCnCE1 Be sure to set it to "0".
  • Page 457 Chapter 13 Serial Interface Setting Example of Slave Communication Note:1 As initial setting, register changed at the time of serial reset is shown below. Please change it if needed, such as interrupt setting or port setting. Master setting at slave address transmission SCnMD0 SCnCE1 Be sure to set it to "0".
  • Page 458 Chapter 13 Serial Interface XIII - 70 IIC Communication...
  • Page 459: Chapter 14 Dma Controller

    XIV.. Chapter 14 DMA Controller...
  • Page 460: Overview

    Chapter 14 DMA Controller 14.1 Overview Direct memory access controller (DMA) allows the direct data access in all memory area without CPU. DMA has priority to access data in memory area over CPU. For internal memory (ReRAM/RAM), CPU can access memory during DMA data transfer if the bus collision between DMA and CPU doesn't happen. DMA has the following features.
  • Page 461: Block Diagram

    Chapter 14 DMA Controller 14.1.1 Block Diagram DMCTRnL/H (n=0,1) DMA control register Access size Timing Whole control signal control IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 ( KEY interrupt ) DMSRCL/M/H Timer 0 interrupt Source address register Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt...
  • Page 462: Dma Controller Control Registers

    Chapter 14 DMA Controller 14.2 DMA Controller Control Registers Table:14.2.1. shows the list of DMA control registers. Table:14.2.1 DMA Control Registers Symbol Address Register Name Page DMCTR0L 0x03E00 DMA control register0 (lower side) XIV-5 DMCTR0H 0x03E01 DMA control register0 (upper side) XIV-6 DMCTR1L 0x03E02...
  • Page 463: Dma Control Register

    Chapter 14 DMA Controller 14.2.1 DMA Control Register DMA Control Register 0 lower side (DMCTR0L: 0x03E00) Bit name DMSAM DMBG4-0 At reset Access Bit name Description Source Address increment control DMSAM 0: Enable (Incremented) 1: Disable (Fixed) Always read as "0". DMA start trigger 00000: software trigger 00001: IRQ0...
  • Page 464 Chapter 14 DMA Controller DMA Control Register 0 upper side (DMCTR0H: 0x03E01) Bit name DMUT DMTM DMDAM At reset Access Bit name Description Always read as "0". Data transmission unit DMUT 0: 8-bit 1: 16-bit Always read as "0". Transfer mode DMTM 0: Burst transfer 1: Single transfer...
  • Page 465 Chapter 14 DMA Controller DMA Control Register 1 lower side (DMCTR1L: 0x03E02) Bit name DMTEN At reset Access Bit name Description Always read as "0". DMA transfer enable control After the DMTEN is set, DMA waits for the DMA start trigger to occur. (When the software trigger is selected in DMCTR0L.DMBG4-0, DMA transfer starts immediately after the DMTEN DMTEN is set to "1".)
  • Page 466 Chapter 14 DMA Controller DMA Control Register 1 upper side (DMCTR1H: 0x03E03) Bit name DMOVF DMRQF At reset Access Bit name Description Always read as "0". DMA-Error detection When the DMA-Error occurs, the DMOVF is set to "1". DMOVF The DMOVF is cleared to "0" by writing DMCTR1L.DMTEN. 0: Not Detect 1: Detect Always read as "0".
  • Page 467: Dma Source Address Register

    Chapter 14 DMA Controller 14.2.2 DMA Source Address Register DMA Source Address Register lower side (DMSRCL: 0x03E04) Bit name DMSA7-0 At reset Access Bit name Description Source address lower side (bit 0 to 7) DMSA7-0 This register shows the address where the next data to be loaded is contained. DMA Source Address Register middle side (DMSRCM: 0x03E05) Bit name DMSA15-8...
  • Page 468: Dma Destination Address Register

    Chapter 14 DMA Controller 14.2.3 DMA Destination Address Register DMA Destination Address Register lower side (DMDSTL: 0x03E08) Bit name DMDA7-0 At reset Access Bit name Description Destination address lower side (bit 0 to 7) DMDA7-0 This register shows the address where the next data from source address is stored. DMA Destination Address Register middle side (DMDSTM: 0x03E09) Bit name DMDA15-8...
  • Page 469: Dma Transfer Word Count Register

    Chapter 14 DMA Controller 14.2.4 DMA Transfer Word Count Register DMA Transfer Word Count Register (DMCNTL: 0x03E0C, DMCNTH: 0x03E0D) Bit name DMCT7-0 At reset Access Bit name DMCT9-8 At reset Access Bit name Description 15-10 Always read as "0". Number of DMA transfer This value is decremented when each transfer is finished.
  • Page 470: Dma Data Transfer

    Chapter 14 DMA Controller 14.3 DMA Data Transfer There are two transfer modes, single transfer and burst transfer, which are selected with the DMCTR0H.DMTM. 14.3.1 Single Transfer Mode When the DMA start trigger occurs, single data, the size of which is decided with DMCTR0H.DMUT, is trans- ferred and the data transfer counter consisting of DMCNTH and DMCNTL are decremented by one.
  • Page 471: Burst Transfer Mode

    Chapter 14 DMA Controller 14.3.2 Burst Transfer Mode When the DMA start trigger occurs, data, the size of which is decided with DMCTR0H.DMUT, is transferred in a single burst until the data transfer counter consisting of DMACNTH and DMACNTL are decremented to zero. When all the data transfer finishes, DMA interrupt occurs.
  • Page 472 Chapter 14 DMA Controller XIV - 14 DMA Data Transfer...
  • Page 473: Chapter 15 Buzzer

    XV.. Chapter 15 Buzzer...
  • Page 474: Overview

    Chapter 15 Buzzer 15.1 Overview Buzzer circuit outputs the square wave generated by dividing HCLK by 1/2 to 1/2 or SCLK by 1/2 to 1/2 HCLK Clock Divider SCLK HCLK HCLK BUZCTR.BUZS2-0 HCLK HCLK Count Clear Buzzer Output(BUZA/BUZB) Output Controller BUZCTR.BUZOE HCLK Inverted Buzzer Output(NBUZA/NBUZB)
  • Page 475: Control Register

    Chapter 15 Buzzer 15.2 Control Register 15.2.1 Registers Table:15.2.1 shows the Buzzer Control Registers. Table:15.2.1 Buzzer Control Registers Symbol Address Register name Page BUZCTR 0x03F7F Buzzer Control Register XV-4 P0DIR 0x03F30 Port 0 direction control register VII-12 P3DIR 0x03F33 Port 3 direction control register VII-13 BUZCNT 0x03F5F...
  • Page 476 Chapter 15 Buzzer 15.2.2 Buzzer Control Register Buzzer Control Register (BUZCTR:0x03F7F) Bit name BUZOE BUZS2-0 At reset Access Bit name Description Buzzer output selection BUZOE 0: Buzzer output disable 1: Buzzer output enable Buzzer output frequency selection 000: f HCLK 001: f HCLK 010: f...
  • Page 477: Operation

    Chapter 15 Buzzer 15.3 Operation 15.3.1 Operation Buzzer Output Frequency The frequency of buzzer output is decided by the setting value of BUZCTR.BUZS2-0 and the frequency of HCLK (f ) and SCLK (f HCLK SCLK Table:15.3.1 Buzzer Output Frequency BUZS2 BUZS1 BUZSO Buzzer output frequency...
  • Page 478: Setup Example

    Chapter 15 Buzzer 15.3.2 Setup Example Setup Example The following example shows how to output the buzzer of 2.44 kHz from BUZB pin under the 10 MHz of f HCLK Step Setup Procedure Register Description Set the buzzer frequency BUZCTR Set the BUZCTR.BUZS to "010". Set the buzzer output pin BUZCNT Select the P02 as the buzzer output pin by...
  • Page 479: Chapter 16 A/D Converter (Adc)

    XVI.. Chapter 16 A/D Converter (ADC)
  • Page 480: Overview

    Chapter 16 A/D Converter (ADC) 16.1 Overview This LSI has an analog-to-digital converter (ADC) with 12 bits resolutions. This ADC has a sample hold circuit, the channel 0 to channel 7 (AN0 to AN7) of analog input can be switched by software. When the ADC is stopped, the power consumption can be reduced by turning the A/D resistor ladder off.
  • Page 481: Block Diagram

    Chapter 16 A/D Converter (ADC) 16.1.2 Block Diagram ADC Block Diagram ANCTR1 ANCTR0 ANCTR2 ANCHS0 ANCHS1 IRQ0/timer 7 ANCHS2 ANLADE interrupt control ANCK0 ANCK1 ANCK2 ANSTSEL0 ADIRQ ANSH0 ANSTSEL1 A/D conversion ANSH1 ANST control ANBUF0 ANBUF1 ANBUF10 ANBUF11 REFP ANBUF12 ANBUF13 ANBUF14 ANBUF04...
  • Page 482: Control Registers

    Chapter 16 A/D Converter (ADC) 16.2 Control Registers The ADC control registers consists of the control registers (ANCTRn) and the data storage buffers (ANBUFn). 16.2.1 Registers Table:16.2.1 shows the registers that control the ADC. Table:16.2.1 ADC Control Registers Symbol Address Register name Page ANCTR0...
  • Page 483 Chapter 16 A/D Converter (ADC) 16.2.2 Control Registers A/D Control Register 0 (ANCTR0: 0x03F60) Bit name ANSH1-0 ANCK2-0 ANLADE At reset Access Bit name Description Sample hold time × 2 00: T ADCLK × 6 01: T ANSH1-0 ADCLK × 18 10: T ADCLK 11: Prohibited...
  • Page 484 Chapter 16 A/D Converter (ADC) A/D Control Register 1 (ANCTR1: 0x03F61) Bit name ANCHS2-0 At reset Access Bit name Description Always read as 0. Analog input channel 000 : AN0 pin 001 : AN1 pin 010 : AN2 pin ANCHS2-0 011 : AN3 pin 100 : AN4 pin 101 : AN5 pin...
  • Page 485: Data Buffers

    Chapter 16 A/D Converter (ADC) 16.2.3 Data Buffers ADC Data Storage Buffer 0 (ANBUF0: 0x03F64) This register stores lower 4 bits data after A/D conversion. Bit name ANBUF07 ANBUF06 ANBUF05 ANBUF04 At reset Access ADC Data Storage Buffer 1 (ANBUF1: 0x03F65) This register stores upper 8 bits after A/D conversion.
  • Page 486: Operation

    Chapter 16 A/D Converter (ADC) 16.3 Operation The following shows the procedures for setting ADC circuit. 1. Set the analog input terminal. Set the analog input terminal by ANEN0. * Be sure to set Analog input control register before applying analog voltage to the terminals. 2.
  • Page 487 Chapter 16 A/D Converter (ADC) Set ANCTR0.ANLADE to "1", then start A/D conversion after waiting for 12 conversion clocks. When ADC is started again after setting ANCTR2.ANST to "0" and ADC was stopped by force during A/D conversion, start ADC after waiting for an equivalent time of (2 system clock) + (2 converter clock) or longer.
  • Page 488 Chapter 16 A/D Converter (ADC) 16.3.1 Setup Input Pins of A/D Conversion Setup Input pins for ADC is selected by the ANCTR1.ANCHS2-0. A/D Conversion Clock Setup The A/D conversion clock is set by the ANCTR0.ANCK2-0. ) between 750 ns and 100 µs. Table:16.3.1 shows the machine clock Set the A/D conversion cycle (T ADCLK (HCLK, SCLK, SYSCLK) and the A/D conversion cycle (T...
  • Page 489 Chapter 16 A/D Converter (ADC) The A/D conversion time indicated in Table:16.3.2 may shorten up to one cycle time of A/D conversion cycle depending on phase differences between system clock and A/D conversion clock. A/D Resistor Ladder Control The ANCTR0.ANLADE is set to "1" to apply current to the resistor ladder for A/D conversion. When A/D con- version is stopped, the ANCTR0.ANLADE is set to "0"...
  • Page 490: Setup Procedure

    Chapter 16 A/D Converter (ADC) 16.3.2 Setup Procedure Initial setup of A/D conversion operation The following flow chart shows the initial setup procedure of A/D conversion operation. START //Analog input pin setting //Analog pin function selection ANEN0.ANEN0 = 1 PnDIR.PnDIRm = 0 PnPLU.PnPLUm = 0 PnODC.PnODCm = 0 //Channel selection...
  • Page 491: Cautions

    Chapter 16 A/D Converter (ADC) 16.3.3 Cautions As A/D conversion could be easily damaged by noise, sufficient anti-noise measures are needed. Anti-noise measures Connect capacitors to analog input pins AN7 to AN0, which is positioned close to VSS pins. In addition, Connect capacitors (the different capacities more than two are recommended.) to ADC reference volt- age pins VREFP, which is positioned close to VSS pins.
  • Page 492 Chapter 16 A/D Converter (ADC) Sample Hold Time This LSI contains a sample hold capacitor (C = 16 pF), input pin capacitor (C = 2 pF) and resistor (R = 4.0 kΩ). Set the sample hold time (T ) based on the time constant (τ) with C and impedance (R ) of external analog signal output circuit.
  • Page 493: Chapter 17 Lcd

    XVII.. Chapter 17 LCD...
  • Page 494: Overview

    Chapter 17 17.1 Overview This LSI has an LCD driver circuit (LCDDRV) which is composed of 43 segment output pins and 4 common out- put pins (39 segment output pins and 8 common output pins). The LCDDRV has an LCD reference voltage circuit (REFVOL) and a voltage booster circuit (BSTVOL).
  • Page 495: Lcd Driver Circuit Block Diagram

    Chapter 17 17.1.1 LCD Driver Circuit Block Diagram Figure:17.1.1 LCD Driver Circuit Block Diagram Overview XVII - 3...
  • Page 496: Control Registers

    Chapter 17 17.2 Control Registers Table:17.2.1 shows the registers that control LCDDRV. Table:17.2.1 LCD Control Registers Register Address Function Page LCDMD0 0x03E80 LCD mode control register 0 XVII-5 LCDMD1 0x03E81 LCD mode control register 1 XVII-6 LCDMD2 0x03E82 LCD mode control register 2 XVII-7 LCDMD3 0x03E83...
  • Page 497: Lcd Mode Control Registers

    Chapter 17 17.2.1 LCD Mode Control Registers LCD Mode Control Register 0 (LCDMD0: 0x03E80) Bit name LCUPEN Reserved LCUPCKDIV2-0 LCUPCKS2-0 At reset Access Bit name Description BSTVOL enable control LCUPEN 0: stop 1: start Reserved Must be set to "0". LCUPCK selection 000: LCUPCKS ×...
  • Page 498 Chapter 17 LCD Mode Control Register 1 (LCDMD1: 0x03E81) Bit name LCVREN LCVRO4-0 At reset Access Bit name Description REFVOL enable control LCVREN 0: stop 1: start Always read as 0. Output voltage of REFVOL (Incremented by 0.05 V) 00000: 0.9 V 00001: 0.95 V LCVRO4-0 10010: 1.8 V...
  • Page 499 Chapter 17 LCD Mode Control Register 2 (LCDMD2: 0x03E82) Bit name LCEN LCMOD1-0 LCMODS Reserved LCDTY2-0 At reset Access Bit name Description LCD display driver control LCEN 0: Stop 1: Start LCD display mode 00: Normal 6 to 5 LCMOD1-0 01: All LCD on 10: All LCD off 11: Setting prohibited...
  • Page 500 Chapter 17 LCD Mode Control Register 3 (LCDMD3: 0x03E83) Bit name Reserved LCCK3-0 LCCKS2-0 At reset Access Bit name Description Reserved Must be set to "0". LCDCLK selection 0000: LCDCLKS/2 0001: LCDCLKS/2 0010: LCDCLKS/2 0011: LCDCLKS/2 0100: LCDCLKS/2 LCCK3-0 0101: LCDCLKS/2 0110: LCDCLKS/2 0111: LCDCLKS/2 1000: LCDCLKS/2...
  • Page 501: Lcd Port Control Registers

    Chapter 17 17.2.2 LCD Port Control Registers LCD port control registers are described the control bits for each product. LCD Port Control Register 0 (LCCTR0: 0x03E86) Bit name SEGSL3 SEGSL2 SEGSL1 SEGSL0 COMSL3 COMSL2 COMSL1 COMSL0 At reset Access Description Bit name MN101LR05D MN101LR04D...
  • Page 502 Chapter 17 LCD Port Control Register 1 (LCCTR1: 0x03E87) Bit name SEGSL11 SEGSL10 SEGSL9 SEGSL8 SEGSL7 SEGSL6 SEGSL5 SEGSL4 At reset Access Description Bit name MN101LR05D MN101LR04D MN101LR03D SEG11/P60 selection SEG11/P50 selection SEGSL11 0: P60 0: P50 Must be set to "0". 1: SEG11 1: SEG11 SEG10/P61 selection...
  • Page 503 Chapter 17 LCD Port Control Register 2 (LCCTR2: 0x03E88) Bit name SEGSL19 SEGSL18 SEGSL17 SEGSL16 SEGSL15 SEGSL14 SEGSL13 SEGSL12 At reset Access Description Bit name MN101LR05D MN101LR04D MN101LR03D SEG19/P50 selection SEG19/P40 selection SEG11/P40 selection SEGSL19 0: P50 0: P40 0: P40 1: SEG19 1: SEG19 1: SEG11...
  • Page 504 Chapter 17 LCD Port Control Register 3 (LCCTR3: 0x03E89) Bit name SEGSL27 SEGSL26 SEGSL25 SEGSL24 SEGSL23 SEGSL22 SEGSL21 SEGSL20 At reset Access Description Bit name MN101LR05D MN101LR04D MN101LR03D SEG27/P40 selection SEG27/P30 selection SEG19/P30 selection SEGSL27 0: P40 0: P30 0: P30 1: SEG27 1: SEG27 1: SEG19...
  • Page 505 Chapter 17 LCD Port Control Register 4 (LCCTR4: 0x03E8A) Bit name SEGSL35 SEGSL34 SEGSL33 SEGSL32 SEGSL31 SEGSL30 SEGSL29 SEGSL28 At reset Access Description Bit name MN101LR05D MN101LR04D MN101LR03D SEG35/P30 selection SEGSL35 0: P30 1: SEG35 SEG34/P31 selection SEGSL34 0: P31 1: SEG34 SEG33/P32 selection SEGSL33...
  • Page 506 Chapter 17 LCD Port Control Register 5 (LCCTR5: 0x03E8B) Bit name SEGSL42 SEGSL41 SEGSL40 SEGSL39 SEGSL38 SEGSL37 SEGSL36 At reset Access Description Bit name MN101LR05D MN101LR04D MN101LR03D Always read as 0. SEG42/P20 selection SEGSL42 0: P20 1: SEG42 SEG41/P21 selection SEGSL41 0: P21 1: SEG41...
  • Page 507 Chapter 17 LCD Display Select Register (LCDSEL: 0x03E8E) Bit name COMSL7 COMSL6 COMSL5 COMSL4 At reset Access Description Bit name MN101LR05D MN101LR04D MN101LR03D Always read as 0. SEG3/COM7 selection COMSL7 0: SEG3 1: COM7 SEG2/COM6 selection COMSL6 0: SEG2 1: COM6 Must be set to "0".
  • Page 508 Chapter 17 Segment Output Latch (LCDATA0-42: 0x03E90-0x03EBA) A 8-bit segment output latch (LCDATAn) is assigned for each segment. Each bit is read in synchronization with the COMn timing and is output from the SEGn. LCDATAn can be read or written like RAM, and the values of them are not valid at reset.
  • Page 509: Operation

    Chapter 17 17.3 Operation 17.3.1 LCDDRV Operation LCDDRV displays data with SEGn and COMn in static, 1/2-duty with 1/2 bias or 1/3 to 1/8 duty with 1/3 bias. When LCDDRV is turned off, the voltage of V is output from COMn and SEGn. At reset, all the common and segment pins are in high-impedance.
  • Page 510: Voltage Booster Circuit (Bstvol)

    Chapter 17 17.3.2 Voltage Booster Circuit (BSTVOL) This LSI has a built-in booster circuit (BSTVOL) for LCD drive which generates a voltage of 2 or 3 times the LCD reference voltage. 2 or 3 Times Boosting When BSTVOL generates 2 or 3 times, input the LCD reference voltage (V ) from VLC3 pin.
  • Page 511: Lcd Drive Voltage Selection

    Chapter 17 17.3.4 LCD Drive Voltage Selection LCD drive voltage can be generated with one of the three method described in Table:17.3.1. Table:17.3.1 LCD Drive Voltage Supply Method Method of generating LCD drive voltage Description Generate the drive voltage Supply the voltage generated outside of the LSI to VLC1, VLC2 outside the LSI and VLC3.
  • Page 512 Chapter 17 <1> In the case of generating the drive voltage outside the LSI Supply each voltage described in Table:17.3.2 to VLC1, VLC2 and VLC3. Figure:17.3.1 shows the connection with the external resistors, and each capacitor should be 0.1 µF. Table:17.3.2 Voltage level of VLC1/VLC2/VLC3 Pin Name Voltage Level...
  • Page 513 Chapter 17 In Figure:17.3.1, power is consumed at resistors all the time. Figure:17.3.2 is the method to stop the above power consumption. VDD30 input DD30 VLC1 VLC2 VLC3 DD30 Port Figure:17.3.2 Connection example for LCD power supply Operation XVII - 21...
  • Page 514 Chapter 17 <2> In the case of generating the drive voltage with BSTVOL (The reference voltage is supplied from outside of the LSI.) When BSTVOL is used with the input reference voltage from outside of the LSI, the LCD drive voltage described in Figure:17.3.3 is generated.
  • Page 515 Chapter 17 <3> In the case of generating the drive voltage with BSTVOL (The reference voltage is generated with REFVOL.) REFVOL output the reference voltage between 0.9 V and 1.8 V, and BSTVOL generate 2, 3 times higher voltage of the reference voltage. Table:17.3.4.
  • Page 516: Lcd Frame Frequency Setup

    Chapter 17 17.3.5 LCD Frame Frequency Setup LCD Frame Frequency Setup The frequency of LCDCLK is determined with the LCDMD3.LCCKS2-0 and LCDMD3.LCCK3-0. LCD frame frequency is determined with the frequency of the LCDCLK and the LCDMD2.LCDY2-0. The following table shows the relation between the typical input frequency, SCLK (32 kHz) and LCD clocks. Table:17.3.5 Input Frequency and LCD Clock (Static) Clock source Clock...
  • Page 517: Setup Examples Of Refvol And Bstvol

    Chapter 17 17.3.6 Setup Examples of REFVOL and BSTVOL The following example shows how to display "23" on a 8-segment type LCD panel by using SEG0-SEG3 and COM0-COM3, with the voltage generated with REFVOL and BSTVOL. The display mode with 1/4 duty output and 1/3 bias is selected. Setup Procedure Description of BSTVOL...
  • Page 518: Lcd Display Examples

    Chapter 17 17.4 LCD Display Examples This section describes how to connect the segment and common signals to LCD panel, and shows the LCD dis- play and waveforms in static, 1/2 duty, 1/3 duty and 1/4 duty by using MN101LR05D. 17.4.1 LCD Display Example (static) Static...
  • Page 519 Chapter 17 Frame period COM0 SEG4 (data) SEG6 (data) "A" electrode (COM0-SEG4) (OFF) "B" electrode (COM0-SEG6) (ON) Figure:17.4.1 LCD display example in static LCD Display Examples XVII - 27...
  • Page 520: Lcd Operation Setup Example (Static)

    Chapter 17 17.4.2 LCD Operation Setup Example (static) The following example is to display "2" on a 8-segment type LCD panel (one digit display) through segment pins, SEG0 to SEG7 and a common pin, COM0 in static, supplied from external voltage source. Other conditions are described as follows;...
  • Page 521: Lcd Display Example (1/2 Duty)

    Chapter 17 17.4.3 LCD Display Example (1/2 duty) 1/2 duty Segment Latch ... 0x03EBA 0x03E97 0x03E96 0x03E95 0x03E94 0x03E93 0x03E92 0x03E91 0x03E90 bit3 COM3 open bit2 COM2 open bit1 COM1 bit0 COM0 ... SEG42 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 "A"...
  • Page 522 Chapter 17 Frame period COM1 COM0 SEG6 (data) +1/2V "A" electrode (COM1-SEG6) -1/2V (OFF) (ON) +1/2V "B" electrode (COM0-SEG6) -1/2V (OFF) (OFF) Figure:17.4.2 LCD display example in 1/2 duty XVII - 30 LCD Display Examples...
  • Page 523: Lcd Operation Setup (1/2 Duty)

    Chapter 17 17.4.4 LCD Operation Setup (1/2 duty) The following example is to display "23" on a 8-segment type LCD panel (two-digit display) through segment pins, SEG0 to SEG7 and common pins, COM0 to COM1 with 1/2 duty and 1/2 bias, supplied from external volt- age divider.
  • Page 524: Lcd Display Example (1/3 Duty)

    Chapter 17 17.4.5 LCD Display Example (1/3 duty) 1/3 duty Segment Latch ... 0x03EBA 0x03E95 0x03E94 0x03E93 0x03E92 0x03E91 0x03E90 bit3 COM3 open bit2 COM2 bit1 COM1 bit0 COM0 ... SEG42 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 "A" electrode "B" electrode : ON : OFF LCDPANEL...
  • Page 525 Chapter 17 Frame period COM2 COM1 COM0 SEG5 (data) +1/3V "A" electrode (COM2-SEG5) -1/3V (OFF) (OFF) (OFF) +1/3V "B" electrode (COM1-SEG5) -1/3V (OFF) (ON) (OFF) Figure:17.4.3 LCD display example in 1/3 duty LCD Display Examples XVII - 33...
  • Page 526: Lcd Operation Setup (1/3 Duty)

    Chapter 17 17.4.6 LCD Operation Setup (1/3 duty) The following example is to display "23" on a 8-segment type LCD panel (two-digit display) through segment pins, SEG0 to SEG5 and common pins, COM0 to COM2 with 1/3 duty and 1/3 bias, supplied from external volt- age divider.
  • Page 527: Lcd Display Example (1/4 Duty)

    Chapter 17 17.4.7 LCD Display Example (1/4 duty) 1/4 duty Segment Latch ... 0x03EBA 0x03E93 0x03E92 0x03E91 0x03E90 bit3 COM3 bit2 COM2 bit1 COM1 bit0 COM0 ... SEG42 SEG3 SEG2 SEG1 SEG0 "A" electrode "B" electrode : ON LCDPANEL : OFF LCD ON LCD OFF COM = S...
  • Page 528 Chapter 17 Frame period COM3 COM2 COM1 COM0 SEG3 (data) +1/3V "A" electrode (COM3-SEG3) -1/3V (OFF) (OFF) (OFF) (OFF) +1/3V "B" electrode (COM1-SEG3) -1/3V (OFF) (ON) (OFF) (OFF) Figure:17.4.4 LCD display example in 1/4 duty XVII - 36 LCD Display Examples...
  • Page 529: Lcd Operation Setup (1/4 Duty)

    Chapter 17 17.4.8 LCD Operation Setup (1/4 duty) LCD Operation Setup Example (1/4 duty) The following example is to display "23" on a 8-segment type LCD panel (two digits) through segment pins, SEG0 to SEG3 and common pins, COM0 to COM3 with 1/4 duty and 1/3 bias, supplied from external voltage divider.
  • Page 530 Chapter 17 XVII - 38 LCD Display Examples...
  • Page 531: Chapter 18 Reram

    XVIII.. Chapter 18 ReRAM...
  • Page 532: Overview Of Reram

    Chapter 18 ReRAM 18.1 Overview of ReRAM Table:18.1.1 shows the outline of ReRAM specifications. Table:18.1.1 Outline of ReRAM Specifications Function Description Memory size 64 KB Program area (62 KB): 1000 times (Min.) Program endurance Data area (2 KB): 100,000 times (Min.) : 1.8 V to 3.6 V Programming Voltage DD30...
  • Page 533: Reram Area

    Chapter 18 ReRAM 18.1.2 ReRAM Area Table:18.1.2 shows program, data and reserved areas in ReRAM. Table:18.1.2 Application of ReRAM area Area Application Access cycle Rewriting 0x04000 to 0x040FF Program area 1 cycle Available 0x04900 to 0x13FFF - Store the user program Data area 0x04100 to 0x048FF - Store the data...
  • Page 534: Self-Programming Rewriting Method

    Chapter 18 ReRAM 18.2 Self-programming Rewriting Method Self-programming allows the ReRAM data programming by setting the FBEWER to "0x4B" and using software libraries in the ReRAM reserved area. Address MAP (FBEWER ≠ "0x4B") Address MAP (FBEWER = "0x4B") Address Address 0x03D82 0x03D82 Registers for...
  • Page 535: Procedures For Rewriting

    Chapter 18 ReRAM 18.2.1 Procedures for Rewriting Figure:18.2.2 shows the ReRAM programming flow. Start Rewriting 1.Set the FBEWER to "0x4B" Command Library Start 2.Set the necessary parameters in the control registers(*1). Call 3.Subroutine-call Software ReRAM Library. (*2) Programming Return 4.Set the FBEWER to any value other than "0x4B"...
  • Page 536: Reram Control Registers

    Chapter 18 ReRAM 18.3 ReRAM Control Registers Table:18.3.1 shows the ReRAM control registers. Table:18.3.1 ReRAM Control Registers Register Address Access Register name and function symbol Rewriting enable register FBEWER 0x03D80 0x4B: Enable programming Others: Disable programming WADDR_L 0x03D82 Rewrite address register WADDR_M 0x03D83 Specify the address to be rewritten...
  • Page 537: Command Library

    Chapter 18 ReRAM 18.4 Command Library Table:18.4.1 shows command libraries for rewriting of the ReRAM. Table:18.4.1 Command Libraries Library name Address Function Write_Code_Lib 0x6F205 Programming Data in Program Area - Specified byte number (2-64 bytes) is programmed. Write_Data_Lib 0x6F20A Programming Data in Data Area - Specified byte number (2-64 bytes) is programmed.
  • Page 538 Chapter 18 ReRAM XVIII - 8 Command Library...
  • Page 539: Chapter 19 On-Board Debugger

    XIX.. Chapter 19 On-Board Debugger...
  • Page 540 It is unnecessary to implement the monitor program in user program area. Refer to the following URL for the details of the on-board debugging. http://www.semicon.panasonic.co.jp/e-micom/onboard/panax_ex.html When LSI is connected to PanaX-EX, VDD18 is always set to 1.8V even when the 1.1V or 1.3V is set by software.
  • Page 541: List Of On-Board Debugging Functions

    Chapter 19 On-Board Debugger 19.2 List of on-board debugging functions Table:19.2.1 List of on-board debugging functions Support or Not On-board Debugging Functions Descriptions (number of support channels ) Single step Step execution as a source line or a unit of assembler Supported execution Functional step...
  • Page 542 Chapter 19 On-Board Debugger XIX - 4 List of on-board debugging functions...
  • Page 543: Chapter 20 Appendix

    XX.. Chapter 20 Appendix...
  • Page 544: Symbol Definitions

    Chapter 20 Appendix 20.1 Symbol Definitions Following is the list of symbols used in the instruction specifications. Nibble is a unit for expressing size, and a nibble is equivalent to half-byte (4 bits). Reg, Reg1, Reg2 : register ( used for general meaning ) Dn, Dm : Data register ( 8 bits ) DWn, DWm, DWk...
  • Page 545 Chapter 20 Appendix : Displacement ( 11 bits ) : Displacement ( 12 bits ) : Displacement ( 16 bits ) : Bit position ( bit0 to 7 ) bpdata : 8-bit data whose bp bit contains ‘ ’ when bp is 0: b’00000001’ when bp is 1: b’00000010’...
  • Page 546 Refer to [LSI manual] for details. And, it may increase by the pipeline stall (instruction supply shortfall, register conflict, etc.). Refer to [MN101L Series Instruction Manual] for details. EX.1 BSET (abs8)bp Cycle: 2+2d If the data access cycle is 1 (d = 0), then the execution cycle becomes 2 + 2 * 0 = 2 cycles.
  • Page 547: Instruction Set

    Chapter 20 Appendix 20.2 Instruction set MN101L SERIES INSTRUCTION SET Flag Code Execution Machine Code Group Mnemonic Operation Notes VF NF CF ZF Size Cycle Ext. Data Transfer Instructions → MOV Dn, Dm 1010 DnDm → MOV imm8, Dm imm8...
  • Page 548 Chapter 20 Appendix MN101L SERIES INSTRUCTION SET Flag Code Execution Machine Code Group Mnemonic Operation Notes VF NF CF ZF Size Cycle Ext. → Am MOVW imm16, Am imm16 1101 111a <#16 ...> → Am MOVW SP , Am...
  • Page 549 Chapter 20 Appendix MN101L SERIES INSTRUCTION SET Flag Code Execution Machine Code Group Mnemonic Operation Notes VF NF CF ZF Size Cycle Ext. → Dm NOT Dn 0010 0010 10Dn → temp, Dn.lsb → CF ASR Dn Dn.msb 0010 0011 10Dn Dn >>...
  • Page 550 Chapter 20 Appendix MN101L SERIES INSTRUCTION SET Flag Code Execution Machine Code Group Mnemonic Operation Notes VF NF CF ZF Size Cycle Ext. if(CF | ZF=0), PC+5+d7(label)+H → PC BHI label 1/3+i 0010 0010 0010 <d7..H *2 *4 if(CF | ZF=1), PC+5 → PC if(CF | ZF=0), PC+6+d11(label)+H →...
  • Page 551 Chapter 20 Appendix MN101L SERIES INSTRUCTION SET Flag Code Execution Machine Code Group Mnemonic Operation Notes VF NF CF ZF Size Cycle EXT. TBZ (abs16)bp, label 4+d/6+d+i 0011 1110 0bp. <abs 16..> <d7..H *1 *3 if(mem8(abs16)bp=0), PC+9+d7(label)+H → PC if(mem8(abs16)bp=1), PC+9 →...
  • Page 552 *1 When the value of SP is odd number, the execution cycle is added "(1+d)". *2 imm3 = 1 : repeat count = 0 (rep : imm3 - 1) Other than the instruction of MN101L Series, the assembler of this Series has the following instructions as macro instructions.
  • Page 553: Instruction Map

    Chapter 20 Appendix 20.3 Instruction map MN101L SERIES INSTRUCTION MAP 1st nibble / 2nd nibble POP An ADD #8,Dm MOVW #8,DWm MOVW #8,Am MOV #8,(io8) CMP #8,(abs8) / (abs12) JSR d12(label) JSR d16(label) PUSH An OR #8,Dm AND #8,Dm MOV #8,(abs8) / (abs12)
  • Page 554 Chapter 20 Appendix Extension code : b'0011' 2nd nibble / 3rd nibble TBZ (abs8)bp,d7 TBZ (abs8)bp,d11 TBNZ (abs8)bp,d7 TBNZ (abs8)bp,d11 CMP Dn,Dm ADD Dn,Dm TBZ (io8)bp,d7 TBZ (io8)bp,d11 TBNZ (io8)bp,d7 TBNZ (io8)bp,d11 OR Dn,Dm AND Dn,Dm BSET (io8)bp BCLR (io8)bp JMP abs18(label) JSR abs18(label) XOR Dn,Dm / XOR #8,Dm...
  • Page 555 Chapter 20 Appendix Instruction map XX - 13...
  • Page 556 Record of Changes Details of revision from Ver.1.4 to Ver.1.5 in MN101LR05D/04D/03D/02D LSI User's Manual is shown below. According to the details of revision, "Definition" of the table below is classified into seven groups. Revision concerning descriptions in LSI User's Manual: Writing error correction / Description change / Description addition / Description deletion Revision concerning LSI specifications: Specification change / Specification addition / Specification deletion...
  • Page 557 Details of revision from Ver.1.3 to Ver.1.4 in MN101LR05D/04D/03D/02D LSI User's Manual is shown below. According to the details of revision, "Definition" of the table below is classified into seven groups. Revision concerning descriptions in LSI User's Manual: Writing error correction / Description change / Description addition / Description deletion Revision concerning LSI specifications: Specification change / Specification addition / Specification deletion Modification (Ver.1.4)
  • Page 558 Details of revision from Ver.1.2 to Ver.1.3 in MN101LR05D/04D/03D/02D LSI User's Manual is shown below. According to the details of revision, "Definition" of the table below is classified into seven groups. Revision concerning descriptions in LSI User's Manual: Writing error correction / Description change / Description addition / Description deletion Revision concerning LSI specifications: Specification change / Specification addition / Specification deletion Modification (Ver.1.3)
  • Page 559 Modification (Ver.1.3) Details of Revision Definition Page Title Line Ver.1.2 Ver.1.3 IV-6 Note 1 Description addition Set the PSW.MIE to "0" before chang- ing the data of CPU or CKCTR... Note 2 Description addition The instruction for changing the data of CPUM or CKCTR must not be exe- cuted in the internal RAM.
  • Page 560 Modification (Ver.1.3) Details of Revision Definition Page Title Line Ver.1.2 Ver.1.3 Writing error correction ← When returning from STOP mode, ← When the transition corresponds to IV-24 Figure:4.2.15 wait for oscillation to stabilize (*1) in Figure: 4.2.1, the oscillation stabilization wait time is inserted. NORMAL/SLOW mode NORMAL/SLOW mode ←...
  • Page 561 If you have questions regarding technical information on this manual, please visit the following URL. Panasonic Corporation URL: http://www.semicon.panasonic.co.jp/en • Microcomputer Home Page http://www.semicon.panasonic.co.jp/e-micom MN101LR05D/04D/03D/02D LSI User's Manual October 7, 2013 1st Edition 5th Printing Issued by Panasonic Corporation  Panasonic Corporation 2013...
  • Page 562 1 Kotari-yakemachi, Nagaokakyo City, Kyoto 617-8520, Japan Tel : 81-75-951-8151 http://www.semicon.panasonic.co.jp/en 010413 Printed in Japan...
  • Page 563 Authorized Distribution Brand: Website: Welcome to visit www.ameya360.com Contact Us: Address: 401 Building No.5, JiuGe Business Center, Lane 2301, Yishan Rd Minhang District, Shanghai , China Sales: Direct +86 (21) 6401-6692 Email amall@ameya360.com 800077892 Skype ameyasales1 ameyasales2 Customer Service: Email service@ameya360.com Partnership:...

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