Instruction Set - Panasonic MN101L Series User Manual

20.2 Instruction set

MN101L SERIES INSTRUCTION SET
Group Mnemonic
Data Transfer Instructions
MOV MOV Dn, Dm Dn
MOV imm8, Dm imm8
MOV Dn, PSW Dn
MOV PSW, Dm PSW
MOV (An), Dm mem8(An)
MOV (d8,An), Dm mem8(d8+An)
MOV (d16,An), Dm mem8(d16+An)
MOV (d4,SP), Dm mem8(d4+SP)
MOV (d8,SP), Dm mem8(d8+SP)
MOV (d16,SP), Dm mem8(d16+SP)
MOV (io8), Dm mem8(IOTOP+io8)
MOV (abs8), Dm mem8(abs8)
MOV (abs12), Dm mem8(abs12)
MOV (abs16), Dm mem8(abs16)
MOV Dn, (Am) Dn
MOV Dn, (d8,Am) Dn
MOV Dn, (d16,Am) Dn
MOV Dn, (d4,SP) Dn
MOV Dn, (d8,SP) Dn
MOV Dn, (d16,SP) Dn
MOV Dn, (io8) Dn
MOV Dn, (abs8) Dn
MOV Dn, (abs12) Dn
MOV Dn, (abs16) Dn
MOV imm8, (io8) imm8
MOV imm8, (abs8) imm8
MOV imm8, (abs12) imm8
MOV imm8, (abs16) imm8
MOV Dn, (HA) Dn
MOVW MOVW (An), DWm mem16(An)
MOVW (An), Am mem16(An)
MOVW (d4,SP), DWm mem16(d4+SP)
MOVW (d4,SP), Am mem16(d4+SP)
MOVW (d8,SP), DWm mem16(d8+SP)
MOVW (d8,SP), Am mem16(d8+SP)
MOVW (d16,SP), DWm mem16(d16+SP)
MOVW (d16,SP), Am mem16(d16+SP)
MOVW (abs8), DWm mem16(abs8)
MOVW (abs8), Am mem16(abs8)
MOVW (abs16), DWm mem16(abs16)
MOVW (abs16), Am mem16(abs16)
MOVW DWn, (Am) DWn
MOVW An, (Am) An
MOVW DWn, (d4,SP) DWn
MOVW An, (d4,SP) An
MOVW DWn, (d8,SP) DWn
MOVW An, (d8,SP) An
MOVW DWn, (d16,SP) DWn
MOVW An, (d16,SP) An
MOVW DWn, (abs8) DWn
MOVW An, (abs8) An
MOVW DWn, (abs16) DWn
MOVW An, (abs16) An
MOVW DWn, (HA) DWn
MOVW An, (HA) An
MOVW imm8, DWm sign(imm8)
MOVW imm8, Am zero(imm8)
MOVW imm16, DWm imm16
Flag Code
Operation
VF NF CF ZF Size
→
Dm - - - -
→
Dm - - - -
→ PSW
→
Dm - - - -
→
Dm - - - -
→
Dm - - - -
→
Dm - - - -
→
Dm - - - -
→
Dm - - - -
→
Dm - - - -
→
Dm - - - -
→
Dm - - - -
→
Dm - - - -
→
Dm - - - -
→ mem8(Am)
- - - -
→ mem8(d8+Am)
- - - -
→ mem8(d16+Am)
- - - -
→ mem8(d4+SP)
- - - -
→ mem8(d8+SP)
- - - -
→ mem8(d16+SP)
- - - -
→ mem8(IOTOP+io8)
- - - -
→ mem8(abs8)
- - - -
→ mem8(abs12)
- - - -
→ mem8(abs16)
- - - -
→ mem8(IOTOP+io8)
- - - -
→ mem8(abs8)
- - - -
→ mem8(abs12)
- - - -
→ mem8(abs16)
- - - -
→ mem8(HA)
- - - -
→ DWm
- - - -
→ Am
- - - -
→ DWm
- - - -
→ Am
- - - -
→ DWm
- - - -
→ Am
- - - -
→ DWm
- - - -
→ Am
- - - -
→ DWm
- - - -
→ Am
- - - -
→ DWm
- - - -
→ Am
- - - -
→ mem16(Am)
- - - -
→ mem16(Am)
- - -
-
→ mem16(d4+SP)
- - - -
→ mem16(d4+SP)
- - - -
→ mem16(d8+SP)
- - -
-
→ mem16(d8+SP)
- - - -
→ mem16(d16+SP)
- - - -
→ mem16(d16+SP)
- - -
-
→ mem16(abs8)
- - - -
→ mem16(abs8)
- - - -
→ mem16(abs16)
- - -
-
→ mem16(abs16)
- - - -
→ mem16(HA)
- - - -
→ mem16(HA)
- -
- -
→ DWm
- - - -
→ Am
- - - -
→ DWm
- -
- -
Execution
REP
Cycle Ext. 1 2
2 1 1010 DnDm
4 1 1010 DmDm <#8.
3 2 0010 1001 01Dn
3 1 0010 0001 01Dm
2 1+d 0100 1ADm
4 1+d 0110 1ADm <d8.
7 1+d 0010 0110 1ADm <d16
3 1+d 0110 01Dm <d4>
5 1+d 0010 0110 01Dm <d8.
7 1+d 0010 0110 00Dm <d16
4 1+d 0110 00Dm <io8
4 1+d 0100 01Dm <abs
5 1+d 0100 00Dm <abs
7 1+d 0010 1100 00Dm <abs
2 1+d 0101 1aDn
4 1+d 0111 1aDn <d8.
7 1+d 0010 0111 1aDn <d16
3 1+d 0111 01Dn <d4>
5 1+d 0010 0111 01Dn <d8.
7 1+d 0010 0111 00Dn <d16
4 1+d 0111 00Dn <io8
4 1+d 0101 01Dn <abs
5 1+d 0101 00Dn <abs
7 1+d 0010 1101 00Dn <abs
6 2+d 0000 0010 <io8
6 2+d 0001 0100 <abs
7 2+d 0001 0101 <abs
9 2+d 0011 1101 1001 <abs
2 1+d 1101 00Dn
2 1+d 1110 00Ad
3 1+d 0010 1110 10Aa
3 1+d 1110 011d <d4>
3 1+d 1110 010a <d4>
5 1+d 0010 1110 011d <d8.
5 1+d 0010 1110 010a <d8.
7 1+d 0010 1110 001d <d16
7 1+d 0010 1110 000a <d16
4 1+d 1100 011d <abs
4 1+d 1100 010a <abs
7 1+d 0010 1100 011d <abs
7 1+d 0010 1100 010a <abs
2 1+d 1111 00ad
3 1+d 0010 1111 10aA
3 1+d 1111 011D <d4>
3 1+d 1111 010A <d4>
5 1+d 0010 1111 011D <d8.
5 1+d 0010 1111 010A <d8.
7 1+d 0010 1111 001D <d16
7 1+d 0010 1111 000A <d16
4 1+d 1101 011D <abs
4 1+d 1101 010A <abs
7 1+d 0010 1101 011D <abs
7 1+d 0010 1101 010A <abs
2 1+d 1001 010D
2 1+d 1001 011A
4 1 0000 110d <#8.
4 1 0000 111a <#8.
6 1 1100 111d <#16
*1 d8 sign-extention
*2 d4 zero-extention
*3 d8 zero-extention
*4 A = An, a = Am
*5 #8 sign-extention
*6 #8 zero-extention
*7 When the access address is odd number, the execution cycle is added "( 1 + d )" .
Machine Code
3 4 5 6 7 8 9
...>
...>
.... .... ...>
...>
.... .... ...>
...>
8..>
12.. ...>
16.. .... ...>
...>
.... .... ...>
...>
.... .... ...>
...>
8..>
12.. ...>
16.. .... ...>
...> <#8. ...>
8..> <#8. ...>
12.. ...> <#8. ...>
16.. .... ...> <#8. ...>
...>
...>
.... .... ...>
.... .... ...>
8..>
8..>
16.. .... ...>
16.. .... ...>
...>
...>
.... .... ...>
.... .... ...>
8..>
8..>
16.. .... ...>
16.. .... ...>
...>
...>
.... .... ...>
Instruction set
Chapter 20
Appendix
Notes
10 11
*1
*2
*3
*1
*2
*3
*4 *7
*4 *7
*2 *7
*2 *7
*3 *7
*3 *7
*7
*7
*7
*7
*7
*7
*7
*4 *7
*2 *7
*2 *7
*3 *7
*3 *7
*7
*7
*7
*7
*7
*7
*7
*7
*5
*6
XX - 5